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path: root/src/soc/mediatek/mt8183
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* treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh2020-06-132-0/+4
* src: Remove redundant includesElyes HAOUAS2020-06-022-2/+0
* soc/mediatek/mt8183: Set CA and DQ vref range to correct valueHuayang Duan2020-05-203-8/+12
* src: Remove unused '#include <stddef.h>'Elyes HAOUAS2020-05-132-2/+0
* soc/mediatek: improve ca53 frequency change procedureWeiyi Lu2020-05-132-0/+23
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-1151-51/+0
* treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi2020-05-062-22/+2
* Revert "soc/mediatek/mt8183: Force retraining memory if requested"Julius Werner2020-04-301-2/+1
* soc/mediatek: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-0551-663/+102
* security/vboot: Decouple measured boot from verified bootBill XIE2020-03-311-1/+1
* soc/mediatek/mt8183: Fix wrong setting of DRS configHuayang Duan2020-03-181-3/+4
* soc/mediatek/mt8183: Improve the AC timing of DRAMCHuayang Duan2020-03-181-6/+16
* soc: Remove copyright noticesPatrick Georgi2020-03-1853-53/+0
* vboot: remove extraneous vboot_recovery_mode_memory_retrainJoel Kitching2020-03-121-1/+2
* soc/mediatek/mt8183: Improve the DRAMC runtime config flowHuayang Duan2020-03-063-123/+109
* soc/mediatek/mt8183: Do TX tracking for DRAM DVFS featureHuayang Duan2020-03-065-14/+776
* soc/mediatek/mt8183: Correct EMI bandwidth threshold for DVFS switchHuayang Duan2020-03-061-2/+4
* soc/mediatek/mt8183: Fix programming error of DRAMC settingHuayang Duan2020-02-251-3/+3
* soc/mediatek: Fix typos in commentsElyes HAOUAS2020-02-251-1/+1
* soc/mediatek: dsi: Increase pcw precisionYu-Ping Wu2020-02-171-14/+10
* soc/mediatek/mt8183: Restore vcore after DRAM calibrationHuayang Duan2020-01-101-1/+11
* soc/mediatek/mt8183: Use DDR clock to compute Tx delay cellHuayang Duan2019-12-201-6/+14
* soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>Elyes HAOUAS2019-12-191-1/+0
* soc/mediatek/mt8183: skip fast calibration for high frequency of TX RX windowHuayang Duan2019-12-121-4/+5
* Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner2019-12-0413-807/+807
* soc/mediatek/mt8183: disable BBLPM of DCXO coreWeiyi Lu2019-11-261-2/+2
* include: Make stdbool.h a separate fileJulius Werner2019-11-181-0/+2
* soc/mediatek/mt8183: Get more space for PreRAM memconsoleHung-Te Lin2019-11-161-6/+6
* lib/fmap: Add optional pre-RAM cacheJulius Werner2019-11-141-1/+2
* soc/mediatek: Add missing '#include <console/console.h>'Elyes HAOUAS2019-11-111-0/+1
* arch/arm64: Pass cbmem_top to ramstage via calling argumentArthur Heymans2019-11-031-1/+1
* soc/{mediatek,sifive}: Remove unused 'include <arch/barrier.h>'Elyes HAOUAS2019-11-011-1/+0
* soc/mediatek/mt8183: Disable DRAM DVFS in recovery modeYu-Ping Wu2019-10-313-2/+7
* soc/mediatek/mt8183: Pass MR values as function argumentsYu-Ping Wu2019-10-286-49/+58
* soc/mediatek/mt8183: Add udelay after setting voltagesYu-Ping Wu2019-10-241-0/+2
* soc/mediatek/mt8183: Improve DRAM calibration logsYu-Ping Wu2019-10-244-24/+19
* soc/mediatek/mt8183: Correct continuation line indentYu-Ping Wu2019-10-241-4/+4
* soc/mediatek/mt8183: Force retraining memory if requestedHung-Te Lin2019-10-241-1/+2
* soc/mediatek/mt8183: Fix incorrect usage of sizeofYu-Ping Wu2019-10-231-4/+4
* src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'Elyes HAOUAS2019-10-212-2/+0
* soc/mediatek/mt8183: Force DRAM retraining if hotkey pressedYu-Ping Wu2019-10-211-0/+6
* soc/mediatek/mt8183: Skip fast calibration in recovery modeYu-Ping Wu2019-10-211-8/+25
* src: Remove unused 'include <string.h>'Elyes HAOUAS2019-10-202-2/+0
* soc/mediatek/mt8183: Compress calibration blob with LZ4Hung-Te Lin2019-10-181-1/+1
* soc/mediatek/mt8183: Pass impedance data as a function argumentYu-Ping Wu2019-10-186-37/+52
* soc/mediatek/mt8183: Run calibration with multiple frequencies for DVFS switchHuayang Duan2019-10-185-26/+207
* soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequencyHuayang Duan2019-10-181-0/+28
* soc/mediatek/mt8183: Allow modifying vddq voltageHsin-Hsiung Wang2019-10-182-0/+108
* soc/mediatek/mt8183: Allow modifying vdram1 voltageHsin-Hsiung Wang2019-10-182-0/+26
* soc/mediatek/mt8183: Share console for calibration blob outputHung-Te Lin2019-10-182-0/+2
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