summaryrefslogtreecommitdiffstats
path: root/src/soc/mediatek/mt8195/include/soc
Commit message (Collapse)AuthorAgeFilesLines
* soc/mediatek: Move common definitions to dramc_soc_common.hRex-BC Chen2022-08-031-16/+2
| | | | | | | | | | | | | | Some definitions are the same in dramc_soc.h for MT8192, MT8195 and MT8186, so we move them to dramc_soc_common.h TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3095333e62abf98de1f2d27033baeeba7a4cad79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66276 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Create GET_TICK_DLY_REG macro for SPI tick delay settingRex-BC Chen2022-07-291-1/+2
| | | | | | | | | | | | | | | MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which is different from previous SoCs, so we define a macro to get the designated register. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move common definitions from rtc.h to rtc_reg_common.hRex-BC Chen2022-07-291-126/+1
| | | | | | | | | | | | | | | Move the common definitions to rtc_reg_common.h, so we can reuse those definitions on MT8188. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia1d916a88b7cb875b35ee5813b7b52d9e98f5009 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66180 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move struct mtk_auxadc_regs to auxadc_common.hRex-BC Chen2022-07-291-11/+0
| | | | | | | | | | | | | | The AUXADC register definitions are the same for all MediaTek SoCs, so we move struct mtk_auxadc_regs to auxadc_common.h. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I48978a93137a7de42f8ea2873be3130cb8f534f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/cherry: Introduce mainboard_needs_pcie_initYu-Ping Wu2022-07-271-0/+3
| | | | | | | | | | | | | | | | | | Implement mainboard_needs_pcie_init() for cherry as a callback for mt8195 SoC to determine whether to initialize PCIe. When the SKU id is unknown or unprovisioned (for example at the beginning of the factory flow), we should still initialize PCIe. Otherwise the devices with NVMe will fail to boot. BUG=b:238850212 TEST=emerge-cherry coreboot BRANCH=cherry Change-Id: I2ed0ceeb37d2924ca16485fb2d130959a7eff102 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* soc/mediatek: Move SPMI device table to SoC folderHui Liu2022-07-131-0/+4
| | | | | | | | | | | | | | | | | The SPMI devices on MT8188 are different from previous SoCs, so we move them to SoC folder. We also move SoC-specific definitions to soc/pmif.h. TEST=build pass BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I666c2a8222a2bd8cd460e2225a7ae48b001da9d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65757 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Move wdt_set_req() to common folderBo-Chen Chen2022-07-061-0/+14
| | | | | | | | | | | | | | | | | | | There are more and more variables which are SoC-specific, so add soc/wdt.h for each SoC and rename common/wdt.h to common/wdt_common.h. wdt_set_req() is almost the same for mt8192, mt8195 and mt8186, so move it to a common file wdt_req.c. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I7a334b3e7cd4f24a848dd31aca546dc7236d5fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65636 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: Add early init supportJianjun Wang2022-03-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add early init support for MT8195 platform. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I4eb7da53ff76c385cab18bbf84970e96b61662ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/63020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/cherry: support max98390 audio ampTrevor Wu2022-03-291-0/+1
| | | | | | | | | | | | | | | | | | | The Cherry follower projects may choose Max98390 for audio output so we have to add a new config CHERRY_USE_MAX98390. Also, the 'dojo' device is the first one to use it. BUG=b:204391159 BRANCH=cherry TEST=emerge-cherry coreboot TEST=Verify beep function through CLI in depthcharge successfully Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63083 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Update audio and adsp power controlChun-Jie Chen2022-03-271-3/+10
| | | | | | | | | | | | | | | | To control I2S in MT8195 for dojo project, we need to enable adsp power before audio power. Therefore, we need to update bus protection steps to correct the setting. TEST=build pass BUG=b:204391159 BRANCH=cherry Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: I0bcf1ddeebf0d3df0a1d6b22273123be1aaf85a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63106 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Add chip config for setting PCIe configJianjun Wang2022-03-162-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Add chip config for setting PCIe config. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: Add driver to configure PCIeJianjun Wang2022-03-101-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new function 'mtk_pcie_pre_init' to assert the PCIe reset at early stage to reduce the impact of 100ms delay. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: Update header version from 1.8.1 to 1.9.1Ryan Chuang2022-03-041-1/+1
| | | | | | | | | | | | | | Move some structures to common folder (CB:61293), so we need to update header version. BUG=none TEST=dram calibration pass Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Id82cbef9cb10dba71489ea96f67c329de9aadc49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* src/mediatek: Refactor dramc_param to share more structuresXi Chen2022-02-231-60/+0
| | | | | | | | | | | | | The ddr_base_info struct, which stores basic DDR information, should be platform independent. Currently the struct is defined in each SoC's dramc_parah.h. To prevent code duplication, move it as well as other related structs and enums to a common header. Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I99772427f9b0755dc2c778b5f4150b2f8147bcc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195/include/soc/addressmap.h: Remove space before tabElyes Haouas2022-02-171-1/+1
| | | | | | | | | | | | Spaces before tabs are not allowed. Change-Id: I2732c01fd87c56227d47a4c0104de8e227b0cc34 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62018 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Extract dramc_param_header to a common headerXi Chen2022-01-241-12/+2
| | | | | | | | | | | | | | | | To be shared with different SOCs, move the dramc_param_header struct as well DRAMC_PARAM_FLAG and DRAMC_PARAM_CONFIG enums to a common header file dramc_param_common.h. TEST=fast calibration pass BUG=b:204226005 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I087971799803e47e34c30063b2b0bd0cfc5795ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61132 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Drop duplicated includesElyes HAOUAS2022-01-011-1/+0
| | | | | | | | | | | <types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/mediatek/mt8195: Move some definations of devapc to common folderRex-BC Chen2021-12-281-45/+0
| | | | | | | | | | | | | Move some definations of devapc for sharing between MT8195 and MT8186. BUG=b:202871018 TEST=emerge-cherry coreboot; emerge-corsola coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia1769ede790f106a320ead9be7e2a596fe96930a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/medaitek/mt8195: adjust USB phy shift valueRex-BC Chen2021-12-261-1/+16
| | | | | | | | | | | | | | | | | There is a design issue of bit shift which will drop a bit for USB3 phy on MT8195. Therefore, we add this patch to set USB phy registers from value of efuse. BUG=b:211528577 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Signed-off-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com> Tested-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com> Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60312 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: add support for tracker version oneRex-BC Chen2021-12-141-0/+8
| | | | | | | | | | | | | | | | | There are two versions for tracker system: Version 1 for MT8186, and version 2 for MT8192 and MT8195. Reference document: MT8169_bus_dbg_tracker_cfg_reg.xls from MediaTek internal. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Idb146974da118b1cf5a349370bf7b2fa13f1aba8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59989 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: complete devapc settingsNina Wu2021-12-062-13/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In previous patch (CB:56764), only basic settings were added. Now complete devapc settings on MT8195. 1. Update permission setting 2. Updtate master domain setting: - domain 1: PCIE0, PCIE1 - domain 2: SPM, SSPM, CPU_EB 3. Set domain remap - MMSYS (4-bit to 2-bit) - TINYSYS (4-bit to 3-bit) - TINYSYS (3-bit to 4-bit) - TINYSYS to EMI (3-bit to 4-bit) - INFRA2 (3-bit to 4-bit) 4. Set SCP domain and ADSP domain - domain 3: SCP - domain 4: ADSP BUG=b:204347737 TEST=sanity test pass Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59746 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: move i2c function to common folderRex-BC Chen2021-11-171-0/+4
| | | | | | | | | | | | | | | Move mtk_i2c_max_step_cnt, mtk_i2c_check_ac_timing, mtk_i2c_speed_init and mtk_i2c_calculate_speed to common folder to share with MT8186. TEST=test on tomato ok TEST=emerge-asurada coreboot BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: move functions of mmu operation to common folderRex-BC Chen2021-11-151-1/+1
| | | | | | | | | | | | | | Move mtk_soc_disable_l2c_sram and mtk_soc_after_dram to common folder which are the same between MT8192, MT8195 and MT8186. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I8f49214b932a8d28ed2ca0d764dc745fa8ad330d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: Add APU device apc driverFlora Fu2021-11-122-0/+41
| | | | | | | | | | | | | | | | | | | | | | | Add APU device apc driver and set up permissions. APU has its own device apc for control access by domains. For Domain 0, the access to the following slaves are restricted to security read and write: apusys_ao-2, apusys_ao-4, apusys_ao-5, apu_sctrl_reviser, apu_iommu0_r1 apu_iommu0_r2, apu_iommu0_r3, apu_iommu0_r4 apu_iommu1_r1, apu_iommu1_r2, apu_iommu1_r3,apu_iommu1_r4 For VPU, D0/D5 are set as no protection, other domains are forbidden. For other slaves, the D0 is no protection, other domains are forbidden. BUG=b:203145462 BRANCH=cherry TEST=boot cherry, check dump log and test permissions Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: move timer enum variables to timer_v2.hRex-BC Chen2021-11-031-12/+0
| | | | | | | | | | | | | | | Some enum variables of timer v2 are the same between MT8195 and MT8186, so we move them to common timer_v2.h. TEST=emerge-cherry coreboot BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I89891a19e622aa24783025e73c38c4ffa43aa166 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58829 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: add apusys init flowFlora Fu2021-11-032-0/+32
| | | | | | | | | | | | | | Set up APU mbox's functional configuration registers. BUG=b:203145462 BRANCH=cherry TEST=boot cherry correctly Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: I5053d5e1f1c2286c9dce280ff83e8b8611b573b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58794 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: add tracker dumpZhenguo Li2021-10-131-4/+8
| | | | | | | | | | | | | Tracker is a debugging tool, include AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. Signed-off-by: Zhenguo Li <ot_zhenguo.li@mediatek.corp-partner.google.com> Change-Id: If457f4a096cd63038bf6b40552aa3caaba33d5fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58243 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Fix I2C failures by adjusting AC timing and bus speedDaolong Zhu2021-10-021-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | 1. The original algorithm for I2C speed cannot always make the timing meet I2C specification so a new algorithm is introduced to calculate the timing parameters more correctly. 2. Some I2C buses should be initialized in a different speed while the original implementation was fixed at fast mode (400Khz). So the mtk_i2c_bus_init is now also taking an extra speed parameter. There is an equivalent change in kernel side: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1 BUG=b:189899864 TEST=Test on Tomato, boot pass and timing pass at 100/300/400/500/800/1000Khz. Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: initialize DFDRex-BC Chen2021-09-291-0/+12
| | | | | | | | | | | | | | | | | DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values could be showed for debugging. BUG=b:192429713 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507c99b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57980 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: add HDMI low power settingRex-BC Chen2021-08-231-0/+33
| | | | | | | | | | Add HDMI low power setting to reduce power consumption. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ica91645789e5de3401131e7050d2b1ee06c535dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/57042 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Add devapc basic driversNina Wu2021-08-041-0/+178
| | | | | | | | | | | | | | | | | | | | | Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. 1. Initialize devapc. 2. Set master domain and secure side band. 3. Set domain remap. 4. Set default permission. Change-Id: I3677657a117caed0d73526f78b0ebe8180148335 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* helpers: Add GENMASK macroYu-Ping Wu2021-08-021-2/+0
| | | | | | | | | | | | | | | | | | | | | | | The GENMASK is defined in multiple files (with various names such as MASKBIT), which sets certain consecutive bits to 1 and leaves the others to 0. To avoid duplicate macros, add GENMASK macro to helpers.h. GENMASK(high, low) sets bits from `high` to `low` (inclusive) to 1. For example, GENMASK(39, 21) gives us the 64-bit vector 0x000000ffffe00000. Remove duplicate macro definitions. Also utilize GENMASK for _BF_MASK in mmio.h. BUG=none TEST=make tests/commonlib/bsd/helpers-test TEST=emerge-cherry coreboot BRANCH=none Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/mediatek/mt8195: modify mt6360 interfaceRex-BC Chen2021-07-211-10/+4
| | | | | | | | | | | | With the new definition of mt6360_regulator_id, merge the MT6360 LDO and PMIC interfaces into one. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7ccc32cb0a9481d5f55349c152267a44fe09d20a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: redefine mt6360_regulator_idRex-BC Chen2021-07-211-21/+21
| | | | | | | | | | | | On MT8195 platforms with BC1.2, we have to use EC to control MT6360 so the mt6360_regulator_id is redefined to match the numbers defined in EC driver. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I9437edb9776442759ce04c31d315c3760078ffb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56434 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: fine tune pmif spi hardware settings for stabilityJames Lo2021-07-121-0/+1
| | | | | | | | | | Update IO driving setting for pmif spi. Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I48268cda8845a591592d8ca828ffe492e6dfe0ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/56166 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Add dramc_param.hRyan Chuang2021-07-071-0/+152
| | | | | | | | | | | | The dramc_param.h defines the header version, structure and APIs for the DRAM calibration parameters stored on the flash, and should be platform independent. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ib8a6ea1b6cf1538854890b653d5d9a934f7f687e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: Enable DCMGarmin Chang2021-07-071-0/+41
| | | | | | | | | | | | Enable DCM settings on the MT8195 platform. DCM means dynamic clock management, and it can dynamically slow down or gate clocks during CPU or bus idle. Change-Id: Ib431a0334c157d440d6e89dcb154241d980d97ce Signed-off-by: Garmin Chang <garmin.chang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: Add mt6360 driver for PMIC accessAndrew SH Cheng2021-06-231-2/+47
| | | | | | | | Signed-off-by: Andrew SH Cheng <andrew-sh.cheng@mediatek.com> Change-Id: Ieaf234f35f2b7d440bdf1e6ec4c455af7b311623 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55710 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: add mt6691 driverhenryc.chen2021-06-181-0/+37
| | | | | | | | | | | | Add mt6691 buck control for DRAM to run fast calibration test. It is needed to get and set voltage during testing. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Change-Id: I4fb9f7245d44383a6a3a0cf8d00f7f503cbdeb06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55575 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: add eDP supportJitao Shi2021-06-184-0/+5180
| | | | | | | | | | | BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I37326ad053295aa4944c8291e4e7a7d69c8f3f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55573 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Add ddp driver to support eDP outputjason-jh.lin2021-06-161-0/+372
| | | | | | | | | | | | | | | Add ddp (display controller) driver that supports overlay, read/write DMA, etc. The output goes to display interface DP_INTF0 directly. Add ddp gclast and output_clamp settings on mt8195 to support multi-layer display. BUG=b:189985956 Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Change-Id: I9d5dd1025c4766218c2b1d86b9b1f97f2eab53d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55509 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Add base addresses for displayJitao Shi2021-06-101-0/+4
| | | | | | | | | | | | | Add disp_dsc/disp_merge/dp_intf/edptx base addresses. BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Change-Id: I694da1449154e5b167c10d6d43d25ee2c5c0ec36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55332 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: add power and power control for eDPJitao Shi2021-06-101-0/+6
| | | | | | | | | | | | | | 1. Add API of TVD_PLL1 mt_pll_set_tvd_pll1_freq() for setting rate. 2. Add API of TVD_PLL1 edp_mux_set_sel() for mux sel. 3. Add eDP power domain control. BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I9e43e0ffeb7b8bcd1786a8d2f5acbf22d5ab501f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55346 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: fix GPIO register offsetsZhiqiang Ma2021-06-051-43/+43
| | | | | | | | | | | | | | | Correct the offsets by MT8195 Register Map V0.2-1 chapter: 3.2 GPIO Controller (page 3272) Control register names: PUPD_CFG0 PU_CFG0 Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com> Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55163 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Enable mt8195 auxadcZhiqiang Ma2021-06-053-1/+40
| | | | | | | | | | Enable auxadc on MediaTek mt8195 platform. Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com> Change-Id: Ie79420e20c9ed6155791b490e1b5e4b44a579a49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: add SPM loaderDawei Chien2021-06-041-13/+432
| | | | | | | | | | | | | | | | | This patch adds support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. TEST=program counter of SPM is correct value after booting up. Change-Id: Ia0f9b9f86e44b293c1cc47213946304c64aea75e Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55140 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Initialize MCUPMalex.miao2021-05-261-0/+2
| | | | | | | | | | | | | Load MCUPM firmware and boot up MCUPM in ramstage. TEST=can see MCUPM log from AP console Signed-off-by: alex.miao <alex.miao@mediatek.corp-partner.google.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I9e8c45ce7166644b94319ec2e7836d3d3c8008dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/54899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: Initialize DRAM in romstageRex-BC Chen2021-05-142-10/+50
| | | | | | | | | | | Initialize DRAM in romstage and configure to support fast calibration. Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54229 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Enable SCP SRAMRex-BC Chen2021-05-131-0/+14
| | | | | | | | | | | | Enable SCP SRAM to allow module in SCPSYS to access DRAM. TEST=AFE acess DRAM successfully Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I40862f8d74e5aa17361f1c91ea31a10b0a4ffb31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54014 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Disable UFS reference clockYidi Lin2021-05-111-1/+1
| | | | | | | | | | | | | UFS reference clock (refclk) is enabled by default, which will cause the UFSHCI to hold the SPM signal and lead to suspend failure. Since UFS kernel driver is not built-in, disable refclk in coreboot stage. Change UFSHCI base register to 0x11270000. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I1386e59f802a9e3c938a7e8dbeea547fbcb02709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-23 14:31:10 +0000