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* soc/intel/common/pch: Add a block specific to Apollo LakeSean Rhodes2022-09-224-27/+41
* soc/amd/picasso: Add support for PSP NVRAM base addr and sizeRitul Guru2022-09-221-0/+10
* common/block/fast_spi: Add extended BIOS window as reserved regionWerner Zeh2022-09-222-5/+5
* soc/intel/spi: Move BIOS flash SPI controllers to fast SPI driverWerner Zeh2022-09-2210-31/+15
* soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registersLiju-Clr Chen2022-09-222-0/+10
* soc/intel/meteorlake: Skip the TCSS D3 cold entry sequencezhaojohn2022-09-211-1/+7
* Revert "soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown"Tim Wawrzynczak2022-09-201-8/+5
* soc/intel/alderlake: Explicitly disable Energy Efficiency TurboJeremy Compostella2022-09-201-0/+3
* qualcomm/sc7280: initialize tu struct with zerosVinod Polimera2022-09-201-3/+1
* soc/intel/alderlake: Add power state thresholdsGaggery Tsai2022-09-202-0/+12
* soc/intel/apollolake: LZ4 Compress FSP-MArthur Heymans2022-09-191-0/+1
* soc/intel/apollolake: Add bits of GEN_PMCON2 registerSean Rhodes2022-09-191-0/+5
* soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdownSean Rhodes2022-09-191-5/+8
* amd/mendocino/root_complex: Throttle SOC during low/no batteryTim Van Patten2022-09-191-0/+12
* amd/mendocino/acpi/soc: Add DPTC SupportTim Van Patten2022-09-191-0/+7
* soc/amd/mendocino: Add low/no battery VRM limit registersTim Van Patten2022-09-191-0/+4
* amd/mendocino/root_complex: Set DPTC VRM limit valuesTim Van Patten2022-09-191-3/+19
* soc/amd/mendocino: Add VRM limit DPTC registersTim Van Patten2022-09-191-0/+4
* soc/amd/acpi: Add low/no battery mode to DPTCTim Van Patten2022-09-193-0/+42
* soc/amd/mendocino/acpi: Add support for shared TPM_I2C controllerJan Dabros2022-09-191-0/+7
* soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU IDJeremy Soller2022-09-162-2/+4
* soc/intel/alderlake: Set FSP-S GnaEnable based on devicetreeJeremy Soller2022-09-161-0/+7
* soc/intel/common: Update comment on HFSTS1.spi_protection_modeSridhar Siricilla2022-09-161-5/+7
* Revert "drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver"Subrata Banik2022-09-161-0/+4
* soc/intel/meteorlake: Enable `SOC_INTEL_COMMON_BLOCK_CNVI` configSubrata Banik2022-09-161-0/+1
* amd/mendocino: Control DPTC with only KconfigTim Van Patten2022-09-152-7/+3
* amd/cezanne: Control DPTC with only KconfigTim Van Patten2022-09-152-7/+3
* zork: Control DPTC with only KconfigTim Van Patten2022-09-152-8/+3
* soc/amd: Do SMM relocation via MSRArthur Heymans2022-09-152-6/+9
* soc/intel/skylake: Assign device ops in chipset devicetreeNico Huber2022-09-1519-272/+94
* soc/intel/xeon_sp: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas2022-09-1510-33/+33
* soc/intel/meteorlake: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas2022-09-152-3/+3
* zork/Kconfig: Move SOC_AMD_COMMON_BLOCK_ACPI_DPTCTim Van Patten2022-09-141-1/+0
* acpi/soc: Conditionally include dptc.aslTim Van Patten2022-09-143-0/+6
* soc/amd/cezanne/Kconfig: add defaults for FSP_M_FILE and FSP_S_FILEFelix Held2022-09-141-0/+14
* soc/amd/common/fsp: only check FSP_M size if ADD_FSP_BINARIES selectedFelix Held2022-09-141-4/+2
* cpu/amd: Move locking SMM as part of SMM initArthur Heymans2022-09-144-38/+11
* cpu/amd/smm: Move MP & SMM init in a common placeArthur Heymans2022-09-146-140/+38
* soc/amd/common: Add common function to get cpu countArthur Heymans2022-09-144-10/+12
* soc/amd: Recalculate the field power in PSS table entryZheng Bao2022-09-143-9/+12
* soc/amd/mendocino: Add support for separate RW A/B partition SPL fileFelix Held2022-09-142-1/+24
* soc/intel/cannonlake: Read HPR_CAUSE0 registerAngel Pons2022-09-143-0/+5
* soc/mediatek: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas2022-09-145-7/+7
* soc/mediatek/mt8188: Set PLLs to hardware default valuesGarmin Chang2022-09-141-84/+84
* soc/mediatek/mt8188: Fix indention in pll.cGarmin.Chang2022-09-141-1/+1
* soc/mediatek/mt8188: Change vpp_sel default mux for 4k supportGarmin Chang2022-09-141-2/+2
* soc/mediatek/mt8188: Fix some wrong settings for PLLsGarmin Chang2022-09-141-18/+18
* timer: Change timer util functions to 64-bitRob Barnes2022-09-1413-18/+18
* soc/intel/mtl: Fix GPIO group pad base for ACPIKapil Porwal2022-09-141-9/+9
* soc/intel/meteorlake/retimer: Change loglevel prefixIvy Jian2022-09-141-1/+1
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