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Commit message (
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)
Author
Age
Files
Lines
*
soc/amd/mendocino: Add svc_set_fw_hash_table
Karthikeyan Ramasubramanian
2022-09-23
2
-0
/
+14
*
soc/common/lockdown: Guard sa_lock_pam
Sean Rhodes
2022-09-22
2
-1
/
+7
*
soc/intel/common/pch: Add a block specific to Apollo Lake
Sean Rhodes
2022-09-22
4
-27
/
+41
*
soc/amd/picasso: Add support for PSP NVRAM base addr and size
Ritul Guru
2022-09-22
1
-0
/
+10
*
common/block/fast_spi: Add extended BIOS window as reserved region
Werner Zeh
2022-09-22
2
-5
/
+5
*
soc/intel/spi: Move BIOS flash SPI controllers to fast SPI driver
Werner Zeh
2022-09-22
10
-31
/
+15
*
soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registers
Liju-Clr Chen
2022-09-22
2
-0
/
+10
*
soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence
zhaojohn
2022-09-21
1
-1
/
+7
*
Revert "soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown"
Tim Wawrzynczak
2022-09-20
1
-8
/
+5
*
soc/intel/alderlake: Explicitly disable Energy Efficiency Turbo
Jeremy Compostella
2022-09-20
1
-0
/
+3
*
qualcomm/sc7280: initialize tu struct with zeros
Vinod Polimera
2022-09-20
1
-3
/
+1
*
soc/intel/alderlake: Add power state thresholds
Gaggery Tsai
2022-09-20
2
-0
/
+12
*
soc/intel/apollolake: LZ4 Compress FSP-M
Arthur Heymans
2022-09-19
1
-0
/
+1
*
soc/intel/apollolake: Add bits of GEN_PMCON2 register
Sean Rhodes
2022-09-19
1
-0
/
+5
*
soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown
Sean Rhodes
2022-09-19
1
-5
/
+8
*
amd/mendocino/root_complex: Throttle SOC during low/no battery
Tim Van Patten
2022-09-19
1
-0
/
+12
*
amd/mendocino/acpi/soc: Add DPTC Support
Tim Van Patten
2022-09-19
1
-0
/
+7
*
soc/amd/mendocino: Add low/no battery VRM limit registers
Tim Van Patten
2022-09-19
1
-0
/
+4
*
amd/mendocino/root_complex: Set DPTC VRM limit values
Tim Van Patten
2022-09-19
1
-3
/
+19
*
soc/amd/mendocino: Add VRM limit DPTC registers
Tim Van Patten
2022-09-19
1
-0
/
+4
*
soc/amd/acpi: Add low/no battery mode to DPTC
Tim Van Patten
2022-09-19
3
-0
/
+42
*
soc/amd/mendocino/acpi: Add support for shared TPM_I2C controller
Jan Dabros
2022-09-19
1
-0
/
+7
*
soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU ID
Jeremy Soller
2022-09-16
2
-2
/
+4
*
soc/intel/alderlake: Set FSP-S GnaEnable based on devicetree
Jeremy Soller
2022-09-16
1
-0
/
+7
*
soc/intel/common: Update comment on HFSTS1.spi_protection_mode
Sridhar Siricilla
2022-09-16
1
-5
/
+7
*
Revert "drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver"
Subrata Banik
2022-09-16
1
-0
/
+4
*
soc/intel/meteorlake: Enable `SOC_INTEL_COMMON_BLOCK_CNVI` config
Subrata Banik
2022-09-16
1
-0
/
+1
*
amd/mendocino: Control DPTC with only Kconfig
Tim Van Patten
2022-09-15
2
-7
/
+3
*
amd/cezanne: Control DPTC with only Kconfig
Tim Van Patten
2022-09-15
2
-7
/
+3
*
zork: Control DPTC with only Kconfig
Tim Van Patten
2022-09-15
2
-8
/
+3
*
soc/amd: Do SMM relocation via MSR
Arthur Heymans
2022-09-15
2
-6
/
+9
*
soc/intel/skylake: Assign device ops in chipset devicetree
Nico Huber
2022-09-15
19
-272
/
+94
*
soc/intel/xeon_sp: Use "if (!ptr)" in preference to "if (ptr == NULL)"
Elyes Haouas
2022-09-15
10
-33
/
+33
*
soc/intel/meteorlake: Use "if (!ptr)" in preference to "if (ptr == NULL)"
Elyes Haouas
2022-09-15
2
-3
/
+3
*
zork/Kconfig: Move SOC_AMD_COMMON_BLOCK_ACPI_DPTC
Tim Van Patten
2022-09-14
1
-1
/
+0
*
acpi/soc: Conditionally include dptc.asl
Tim Van Patten
2022-09-14
3
-0
/
+6
*
soc/amd/cezanne/Kconfig: add defaults for FSP_M_FILE and FSP_S_FILE
Felix Held
2022-09-14
1
-0
/
+14
*
soc/amd/common/fsp: only check FSP_M size if ADD_FSP_BINARIES selected
Felix Held
2022-09-14
1
-4
/
+2
*
cpu/amd: Move locking SMM as part of SMM init
Arthur Heymans
2022-09-14
4
-38
/
+11
*
cpu/amd/smm: Move MP & SMM init in a common place
Arthur Heymans
2022-09-14
6
-140
/
+38
*
soc/amd/common: Add common function to get cpu count
Arthur Heymans
2022-09-14
4
-10
/
+12
*
soc/amd: Recalculate the field power in PSS table entry
Zheng Bao
2022-09-14
3
-9
/
+12
*
soc/amd/mendocino: Add support for separate RW A/B partition SPL file
Felix Held
2022-09-14
2
-1
/
+24
*
soc/intel/cannonlake: Read HPR_CAUSE0 register
Angel Pons
2022-09-14
3
-0
/
+5
*
soc/mediatek: Use "if (!ptr)" in preference to "if (ptr == NULL)"
Elyes Haouas
2022-09-14
5
-7
/
+7
*
soc/mediatek/mt8188: Set PLLs to hardware default values
Garmin Chang
2022-09-14
1
-84
/
+84
*
soc/mediatek/mt8188: Fix indention in pll.c
Garmin.Chang
2022-09-14
1
-1
/
+1
*
soc/mediatek/mt8188: Change vpp_sel default mux for 4k support
Garmin Chang
2022-09-14
1
-2
/
+2
*
soc/mediatek/mt8188: Fix some wrong settings for PLLs
Garmin Chang
2022-09-14
1
-18
/
+18
*
timer: Change timer util functions to 64-bit
Rob Barnes
2022-09-14
13
-18
/
+18
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