summaryrefslogtreecommitdiffstats
path: root/src/soc
Commit message (Expand)AuthorAgeFilesLines
* soc/intel/common/cse: Drop CSE library usage in bootblockSubrata Banik2022-01-271-1/+0
* soc/intel/skylake: move heci_init() from bootblock to romstageMatt DeVillier2022-01-272-4/+3
* src: Add missing 'void' in function definitionElyes HAOUAS2022-01-264-9/+9
* soc/intel/cannonlake: Add PcieRpHotPlug config to FSP-MMatt DeVillier2022-01-261-0/+1
* soc/intel/denverton_ns: Fix logging levelKyösti Mälkki2022-01-261-2/+2
* soc/intel/alderlake: Add GPIO Controller device ID for ADL-NUsha P2022-01-261-0/+5
* soc/mediatek/mt8186: Use BIT() macro for arbiter enable bitRex-BC Chen2022-01-261-20/+20
* soc/intel/alderlake: Choose non-posted write to lock GPIO PADSubrata Banik2022-01-261-0/+1
* soc/intel/alderlake: Skip FSP to unlock GPIO PadsSubrata Banik2022-01-261-1/+1
* soc/intel/common/gpio: Rework PAD config macro to add lock supportSubrata Banik2022-01-263-21/+95
* soc/intel/common/gpio: Perform GPIO PAD lock outside SMMSubrata Banik2022-01-261-56/+114
* soc/amd/cezanne,picasso,sabrina: factor out get_threads_per_coreFelix Held2022-01-265-9/+11
* soc/mediatek/mt8186: Update PWRAP arbiter enable bitRex-BC Chen2022-01-261-13/+22
* soc/amd/common: Don't reserve VERSTAGE region when using PSP verstageRaul E Rangel2022-01-261-1/+1
* soc/amd/cezanne: FSP: Add UPD entry for eDP tuningZheng Bao2022-01-252-0/+23
* soc/intel/ehl: Add Kconfig option to disable reset on TCO expirationWerner Zeh2022-01-252-0/+19
* soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-253-9/+4
* soc/intel/common: Include Alder Lake-N device IDsUsha P2022-01-256-0/+14
* soc/intel/elkhartlake: Add PSE TSN supportLean Sheng Tan2022-01-254-39/+116
* soc/intel/elkhartlake: Introduce Intel PSELean Sheng Tan2022-01-255-1/+173
* soc/mediatek: Save dramc_param header to mrc_cacheXi Chen2022-01-251-8/+5
* soc/amd/sabrina/include/aoac_defs: add additional UARTsFelix Held2022-01-251-2/+3
* soc/amd/sabrina/include/iomap: update MMIO device mappingsFelix Held2022-01-251-2/+6
* soc/amd/cezanne: Increase PRERAM_CBMEM_CONSOLE_SIZE to 0x2000Raul E Rangel2022-01-251-1/+1
* soc/amd/sabrina: use correct PCI IDsFelix Held2022-01-252-35/+17
* soc/amd/common/block/include/psp_efs: update defines for sabrinaFelix Held2022-01-251-1/+1
* soc/amd/sabrina: add new SoC as copy of soc/amd/cezanneFelix Held2022-01-2562-0/+5478
* soc/intel/common/block/pcie/rtd3: Fix PMC IPC method for CPU PCIe RPTim Wawrzynczak2022-01-241-1/+1
* soc/amd/common: Make the function in cpu.c available in romstageZheng Bao2022-01-241-0/+1
* soc/mediatek: Extract dramc_param_header to a common headerXi Chen2022-01-244-36/+34
* soc/amd/{common,cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZERaul E Rangel2022-01-235-5/+56
* soc/intel/alderlake: Implement get_soc_cpu_type helper functionSridhar Siricilla2022-01-221-0/+21
* soc/intel/common/cse: Add support to get CSME timestampsBora Guvendik2022-01-213-0/+170
* soc/intel/common/gpio: Add PCH `Pad Configuration Lock` optionsSubrata Banik2022-01-211-0/+15
* soc/intel/common/gpio: Use const variable to get gpio bitmaskSubrata Banik2022-01-211-1/+3
* soc/intel/alderlake: Add ADL-P 2+8+2 (28W) VR configCurtis Chen2022-01-213-3/+8
* soc/intel/ehl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-212-9/+1
* soc/intel/icl: Rework on HECI1 disable configsSubrata Banik2022-01-213-10/+5
* soc/amd/picasso/bootblock: drop unused includesFelix Held2022-01-201-4/+0
* soc/amd/cezanne,picasso: factor out common early non-car cache setupFelix Held2022-01-205-155/+85
* soc/amd/cezanne/include/espi.h: add missing include guardsFelix Held2022-01-201-0/+5
* soc/amd/common/vboot: Verify the size of the transfer bufferRaul E Rangel2022-01-201-1/+1
* soc/intel/alderlake: Add method to determine the cpu typeSridahr Siricilla2022-01-194-0/+82
* soc/intel/common/cpu: Use SoC overrides to get CPU privilege levelSubrata Banik2022-01-1920-4/+116
* soc/intel/alderlake: Rework the GPIO PAD Pin numbersSubrata Banik2022-01-191-420/+485
* soc/amd/{picasso,cezanne}: Enable CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTSRaul E Rangel2022-01-182-0/+2
* soc/intel/alderlake: Add eMMC device into chipset.cbKrishna Prasad Bhat2022-01-181-0/+2
* soc/intel/common: Add Alder Lake N eMMC device IDKrishna Prasad Bhat2022-01-181-0/+1
* soc/intel/{adl,common}: Support alderlake host device id 0x4619Kane Chen2022-01-183-0/+3
* pci_ids.h: Make Denverton IDs consistent with other Intel SoCsJeff Daly2022-01-179-12/+12
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 14:21:27 +0000