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* soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3Tim Wawrzynczak2021-12-131-5/+79
| | | | | | | | | | | | | | | | | | | | | | | | For additional power savings during RTD3, the PMC can power-gate the ModPHY lanes that are used by the PCH PCIe root ports. Therefore, using the previous PCIe RP-type detection functions, implement ModPHY PG support for the PCH PCIe RPs. This involves: 1) Adding a mutex so only one power resource accesses the PMC registers at a time 2) OperationRegions to access the PMC's PG registers 3) Adding ModPHY PG enable sequence to _OFF 4) Adding ModPHY PG disable sequence to _ON BUG=b:197983574 TEST=50 S0ix suspend/resume cycles on brya0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59855 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Define soc_get_pcie_rp_typeTim Wawrzynczak2021-12-133-2/+62
| | | | | | | | | | | | | | In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Alder Lake. While we're here, add PCIe RP group definitions for PCH-M chipsets. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* soc/intel/tigerlake: Define soc_get_pcie_rp_typeTim Wawrzynczak2021-12-133-0/+56
| | | | | | | | | | | | | | In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Tiger Lake. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* drivers/intel/mipi_camera: Add ACPI entry to provide silicon type infoSugnan Prabhu S2021-12-131-0/+6
| | | | | | | | | | | | | | | | | | Add entry in ACPI table under IPU device to provide silicon type information to IPU driver. IPU kernel driver can decide the type of firmware to load based on this information. BUG=b:207721978 BRANCH=none TEST=Check for the ACPI entry in the SSDT after booting to kernel Change-Id: I4e0af1dd50b9c014cae5454fcd4f9f76d0e0a85f Cq-Depend: chromium:3319905 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/cannonlake: Configure common FSP memory settings only onceFelix Singer2021-12-131-2/+2
| | | | | | | | | | | | | | `meminit_memcfg()` does common memory configuration, which is not specific to each DIMM. Thus, move it out of the for-loop and call it once. Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/elkhartlake: Hook up public microcodeArthur Heymans2021-12-122-1/+3
| | | | | | | | Change-Id: I1d975713129d0a7bce823232d225ed17ee28a04d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* soc/intel/jasperlake: Hook up public microcodeArthur Heymans2021-12-122-1/+2
| | | | | | | | Change-Id: I9e511de5e5b79936ed09538b3877655f78de15a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* soc/intel/cannonlake: Rename SA_DEV_SLOT_DSPFelix Singer2021-12-122-5/+5
| | | | | | | | | | | | Device 4 was introduced with a wrong name, since it is the SA Thermal Subsystem and it does nothing have to do with DSP. Thus, rename it accordingly. Change-Id: I8edc764413df5f323098e60d0a3f0f87a7e656cb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60049 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/{skylake/cannonlake}: Fix bug in vr_configAngel Pons2021-12-102-2/+2
| | | | | | | | | | | | | | | | The `cpu_get_power_max()` function returns the TDP in milliwatts, but the vr_config code interprets the value in watts. Divide the value by 1000 to fix this. This also fixes an integer overflow when `cpu_get_power_max()` returns a value greater than 65535 (UINT16_MAX). Change-Id: Ibe9e0db6762eee5cc363f8b371c8538eb92f6308 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* soc/intel/cse: config to enable oem key manifestRavindra N2021-12-102-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CB change will enable the CSE region sub-partition OEMP, where the OEMP binary will be stitched. OEM KM has Audio FW's key hash. So, CSE uses this information to authenticate Audio FW. BUG=b:207820413 TEST: Boot to kernel and check for the audio authentication is successful localhost ~ # aplay -l **** List of PLAYBACK Hardware Devices **** card 0: sofrt5682 [sof-rt5682], device 0: max357a-spk (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 1: Headset (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 2: HDMI1 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 3: HDMI2 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 4: HDMI3 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 5: HDMI4 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 Cq-Depend: chrome-internal:4286038 Signed-off-by: Ravindra N <ravindra@intel.corp-partner.google.com> Change-Id: I3620adb2898efc002104e0ba8b2afd219c31f230 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
* soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer2021-12-092-3/+1
| | | | | | | | | | | | | | | | | | Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/tigerlake: Drop unused SataEnable settingFelix Singer2021-12-091-1/+0
| | | | | | | | | | | | | `SataEnable` is set by some boards, but it doesn't have any effect since its related FSP option is hooked up to the devicetree state. Thus, drop it. Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer2021-12-092-4/+1
| | | | | | | | | | | | | | | | | | | Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0Tim Wawrzynczak2021-12-091-1/+1
| | | | | | | | | | | The macro was defined using PCH_DEV_SLOT_CPU_1, which doesn't exist, so replace it with the correct value of SA_DEV_SLOT_CPU_1. Change-Id: If6d294d681907c51ac5678c9251364d4d6df4329 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* soc/amd/stoneyridge: use common fch_spi_early_initFelix Held2021-12-092-69/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All SPI interface setup related functionality that Stoneyridge implemented in its southbridge code is already present in the common AMD SoC code, so use that code instead. The common fch_spi_early_init function requires the SPI controller's base address to be set, so call lpc_set_spibase(SPI_BASE_ADDRESS) right before it. fch_spi_early_init then calls lpc_enable_spi_rom and lpc_enable_spi_prefetch which can be removed from the board code now. Next it calls fch_spi_configure_4dw_burst which does the same as the now removed sb_disable_4dw_burst function when SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST is set to n which is the default. This option can also only be set to y for SoCs that aren't Stoneyridge. Finally fch_spi_early_init calls fch_spi_config_modes which configures the SPI mode and speed settings according to the Kconfig settings and the settings in the amdfw part. On Kahlee this was done by calls to sb_read_mode and sb_set_spi100 before. The previous patch added the remaining Kconfig settings, so the resulting register values don't change in the non-EM100 case. In the EM100 case the TPM speed is changed from 64 to 16 MHz. TEST=Both the non-EM100 mode with a real SPI flash and the EM100 mode with a first-generation EM100 results in Google/Barla reaching the payload and the show_spi_speeds_and_modes call in bootblock prints the expected settings: relevant bootblock console output in non-EM100 case: SPI normal read speed: 33.33 MHz SPI fast read speed: 66.66 Mhz SPI alt read speed: 66.66 Mhz SPI TPM read speed: 66.66 Mhz SPI100: Enabled SPI Read Mode: Dual IO (1-2-2) relevant bootblock console output in EM100 case: SPI normal read speed: 16.66 MHz SPI fast read speed: 16.66 MHz SPI alt read speed: 16.66 MHz SPI TPM read speed: 16.66 MHz SPI100: Enabled SPI Read Mode: Normal Read (up to 33M) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f37a3b040808d6a5a8e07d39b6d4a1e1981355c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/common/block/psp: add psp_efs.c to build for both PSP GEN1&2Felix Held2021-12-091-3/+3
| | | | | | | | | | | | | The PSP EFS code to get the SPI mode and speed from the amdfw part of the firmware image also works for Stoneyridge which is the one SoC that selects SOC_AMD_COMMON_BLOCK_PSP_GEN1. Also amdblocks/psp_efs.h already handles the SOC_AMD_STONEYRIDGE case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibddd3f9237e561d9f0f6b4ad70f59cce1f956986 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/mediatek/mt8186: Enable ARM Trusted Firmware integrationRex-BC Chen2021-12-092-0/+3
| | | | | | | | | | | | | | | Enable configuration to build with MT8186 arm-trusted-firmware drivers. TEST=build pass BUG=b:202871018 Cq-Depend: chromium:3189573 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ib23b112a0bf3d056b932a87b86aaff79508ef50c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/intel/common/pch: Fix return value documentation for CHIPSET_LOCKDOWNJingle Hsu2021-12-082-4/+4
| | | | | | | | | | | | | | Fixed according to the declaration in soc/intel/common/block/include/intelblocks/cfg.h. Change-Id: I50dbc00806fefda8f4dac8bfa21dc714a9504566 Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resumeRaul E Rangel2021-12-084-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardware_Specification.html#pm1-event-grouping > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit (and thus passing control to OSPM). For ACPI > only platforms (where SCI_EN is always set), when transitioning from > either the mechanical off (G3) or soft-off state to the G0 working > state this register is cleared prior to entering the G0 working state. This means we don't want to clear the PM1 register on resume. By clearing it the linux kernel can't correctly increment the wake count when the power button is pressed. The AMD platforms implement the _SWS ACPI methods, but the linux kernel doesn't actually use these methods. BUG=b:172021431 TEST=suspend zork and push power button and verify power button wake_count increments. Verified other wake sources still work. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/stoneyridge/southbridge: drop ENV_X86 checkFelix Held2021-12-081-2/+1
| | | | | | | | | | | | | | | Stoneyridge selects ARCH_X86 unconditionally and all coreboot code will run on the x86 cores. On Picasso and later, the Chromebooks run verstage on the PSP which is an ARM V7 core which needs some special handling cases in the code, but this doesn't apply to Stoneyridge. TEST=Timeless build results in an identical image for Google/Careena. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I013efd13b56c0191af034a8c4b58e9b26a31c6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/{cezanne,picasso,stoney}: Clear PM/GPE when enabling ACPIRaul E Rangel2021-12-083-0/+3
| | | | | | | | | | | | | | | | | | | | | According to https://uefi.org/specs/ACPI/6.4/16_Waking_and_Sleeping/sleeping-states.html?highlight=power%20states# > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit. This change makes sure we clear the PM/GPE blocks are cleared before enabling the SCI_EN bit. BUG=b:172021431 TEST=Boot guybrush and morphius to OS and verify suspend resume still works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icc6f542185dc520f8d181423961b74481c0b5506 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100Felix Held2021-12-081-1/+1
| | | | | | | | | | | | | | | | Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities of the SPI interface. The reference code for Stoneyrige also only sets the SPI_USE_SPI100 bit and doesn't zero out the other bits. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4d32fc2084bb34ea57924bae68511c6836587790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/common/block/spi: fix setting SPI_USE_SPI100 in SPI100_ENABLEFelix Held2021-12-081-1/+1
| | | | | | | | | | | | | | | | | | Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities of the SPI interface. The reference code for both Picasso and Cezanne also only sets the SPI_USE_SPI100 bit and doesn't zero out the other bits. TEST=Verified that Mandolin still boots. It didn't show any signs of possibly related instabilities before though, so this test doesn't say much. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71c2ec1729d5cb4cdff6444b637af29caaa6f1c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/common/block/include/spi: update fch_spi_early_init descriptionFelix Held2021-12-081-1/+1
| | | | | | | | | | | | | | commit 90ac882a32075b44435aa19ea664b89b79cac76e (soc/amd/common/block/ spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST) introduced a Kconfig option to enable/disable the 4DW burst support in the SPI flash data prefetcher, but missed to update the documentation above the fch_spi_early_init prototype, so update the outdated documentation now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I07c4b0b02251da63d34a172e2636894e99845d6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/mediatek/mt8186: Correct SPI_HZ for PLLRex-BC Chen2021-12-081-2/+2
| | | | | | | | | | | | | The SPI speed is 218.4MHz, so correct the value of SPI_HZ. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I6e8ba10a851e1507405cdd41939a176462734487 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: revise SPI NOR GPIO selectionRex-BC Chen2021-12-081-11/+13
| | | | | | | | | | | | | | | The setting of SPI NOR GPIOs should be: CS: pull up. CLK/IO0/IO1: pull down. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ideacb797a1dc9999ab6ba00cf33adbbbc24213dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_initRaul E Rangel2021-12-081-3/+0
| | | | | | | | | | | | | | | | | These functions can't be weak, because they actually need to configure the GPIOs for eSPI and the TPM. With this change zork boots again. I also noticed that zork doesn't use the early table in bootblock. This means that zork will only boot if psp_verstage is enabled. BUG=b:209465425 TEST=boot zork to ramstage Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* soc/amd: use KiB and MiB definitionsFelix Held2021-12-083-3/+3
| | | | | | | | | | | Use KiB and MiB instead of multiplying/dividing with/by the numeric value when doing region size calculations. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I56c380190b11aa3214cce31b82974327e3d15000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* soc/intel/alderlake: enable gpio lockingNick Vaccaro2021-12-072-0/+58
| | | | | | | | | | | | | | | | | This change supplies a list of ADL gpios that are connected to non-host (x86) controllers and should be locked after initial configuration. Set SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS to enable GPIO locking. BUG=b:210430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/intel/common: add generic gpio lock mechanismNick Vaccaro2021-12-074-40/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For added security, there are some gpios that an SoC will want to lock once initially configured, such as gpios attached to non-host (x86) controllers, so that they can't be recofigured at a later point in time by rogue code. Likewise, a mainboard may have some gpios connected to secure busses and/or devices that they want to protect from being changed post initial configuration. This change adds a generic gpio locking mechanism that allows the SoC to export a list of GPIOs to be locked down and allows the mainboard to export a list of GPIOs that it wants locked down once initialization is complete. Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to enable this feature. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify brya0 boots successfully to kernel. Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Add ADL-P 6+8+2 (28W) VR configCurtis Chen2021-12-061-0/+5
| | | | | | | | | | | | | | We only have ADL-P 6+8+2 (45W) VR configuration now. Based on the power map, fill in correct ADL-P 6+8+2 (28W) VR configuration. BUG=b:202486131 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: Ie8dbd95b2d8e49b5898b2a97aff72e0e64868c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/mediatek/mt8195: complete devapc settingsNina Wu2021-12-063-143/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In previous patch (CB:56764), only basic settings were added. Now complete devapc settings on MT8195. 1. Update permission setting 2. Updtate master domain setting: - domain 1: PCIE0, PCIE1 - domain 2: SPM, SSPM, CPU_EB 3. Set domain remap - MMSYS (4-bit to 2-bit) - TINYSYS (4-bit to 3-bit) - TINYSYS (3-bit to 4-bit) - TINYSYS to EMI (3-bit to 4-bit) - INFRA2 (3-bit to 4-bit) 4. Set SCP domain and ADSP domain - domain 3: SCP - domain 4: ADSP BUG=b:204347737 TEST=sanity test pass Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59746 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Add support for ADL-N CPU TypeUsha P2021-12-062-0/+12
| | | | | | | | | | | Add Alder Lake-N case for adl_cpu_type and get_supported_lpm_mask. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratioSridhar Siricilla2021-12-061-3/+2
| | | | | | | | | | | | | The patch refectors cpu_set_p_state_to_max_non_turbo_ratio(). The function is updated to use cpu_get_max_non_turbo_ratio(). TEST=Build the code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If73df17faaf7b870ae311460a868d52352683c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common: Add CPU related APIsSridahr Siricilla2021-12-062-0/+68
| | | | | | | | | | | | | | | | | The patch defines below APIs : cpu_is_hybrid_supported() : Check whether CPU is hybrid CPU or not. cpu_get_bus_frequency() : Get CPU's bus frequency in MHz cpu_get_max_non_turbo_ratio() : Get CPU's max non-turbo ratio cpu_get_cpu_type() : Get CPU type. The function must be called if executing CPU is hybrid. TEST=Verified the APIs on the Brya board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I680f43952ab4abce6e342206688ad32814970a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.hTim Wawrzynczak2021-12-062-10/+11
| | | | | | | | | | | | | | This enum is useful to have around for more than just the one file, so move it to a common header file, and while we're there, also add an option for UNKNOWN. TEST=boot test on brya0 Change-Id: I9ccf0ed9504dbf6c60e521a45ea4b916d3dcbeda Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* soc/intel/adl: Add override skip_cse_sub_part_update() for alderlakeKrishna Prasad Bhat2021-12-031-0/+6
| | | | | | | | | | | | | Check the Alderlake CPU ID to determine if cse sub-paritition update is required or not. BUG=b:202143532 Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common: Add support for CSE IOM/NPHY sub-parition updateKrishna Prasad Bhat2021-12-035-4/+454
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the following support to coreboot 1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B partition of BIOS 2. Helper functions to support update. Pre-requisites to enable IOM/NPHY FW Update: 1. NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and FW_MAIN_B through board configuration files. CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path 2. Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition NPHY/IOM update. coreboot follows below procedure to update NPHY and IOM: NPHY Update: 1. coreboot will navigate through the CSE region, identify the CSE’s NPHY FW version and BIOS NPHY version. 2. Compare both versions, if there is a difference, CSE will trigger an NPHY FW update. Otherwise, skips the NPHY FW update. IOM Update: 1. coreboot will navigate through the CSE region, identify CSE's IOM FW version and BIOS IOM version. 2. Compares both versions, if there is a difference, coreboot will trigger an IOM FW update.Otherwise, skip IOM FW update. Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only if CSE boots from CSE RO Boot partition. Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then triggers update of NPHY and IOM FW in the CSE Region(RO and RW). coreboot triggers NPHY/IOM update procedure in all ChromeOS boot modes(Normal and Recovery). BUG=b:202143532 BRANCH=None TEST=Build and verify CSE sub-partitions IOM and NPHY are getting updated with CBFS IOM and NPHY blobs. Verified TBT, type-C display, NVMe, SD card, WWAN, Wifi working after the update. Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common: Add check before sending HMRFPO_ENABLE commandSridhar Siricilla2021-12-031-0/+6
| | | | | | | | | | | | | | | | This patch adds a check to determine if the CSE's current operation mode is ME_HFS1_COM_SECOVER_MEI_MSG or not before sending HMRFPO_ENABLE command to CSE. If CSE is already in the ME_HFS1_COM_SECOVER_MEI_MSG, coreboot skips sending HMRFPO_ENABLE command to CSE to unlock the CSE RW partition. TEST=Verify sending HMRFPO_ENABLE command on Brya system. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common: Rename compare_cse_version() function nameSridhar Siricilla2021-12-031-3/+4
| | | | | | | | | | | | | | | | The patch renames the compare_cse_version() function to the cse_compare_sub_part_version(). It makes the function generic so that it can be used to compare version of any CSE sub-partition like IOM, NPHY etc. TEST=Verified build for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I88a44a3c0ba2ad8a589602a35ea644dab535b287 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59689 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Add support for ADL-N PCHUsha P2021-12-032-0/+11
| | | | | | | | | | | | | | | | | | | | Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to specify the correct amount of PCIe I/O. Document number 645550 indicates that Alder Lake-N has 12 PCH root ports and no CPU root ports. Document number 645548 indicates ADL-N has 5 clock sources and 5 clock request signals. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Add the CnviDdrRfim configurationRonak Kanabar2021-12-032-0/+8
| | | | | | | | | | | | | | | | FSP v2422_01 introduced new FSPM UPD CnviDdrRfim. Add CnviDdrRfim config to control the CnviDdrRfim UPD from devicetree. Setting CnviDdrRfim to 1 enable CNVi DDR RFIM BUG=b:201724512 BRANCH=None TEST=Build and boot brya with debug FSP and verify CnviDdrRfim UPD value. Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Add TDP to give correct VR configurationCurtis Chen2021-12-032-37/+38
| | | | | | | | | | | | | | | | | The VR configuration should be based on the different Soc SKU type. And we also have different SKU in the same SA PCI ID. Therefore, add TDP to recognize the correct SKU and give the correct power setting. BUG=b:202486131 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: I4d31e7afc76d9a8c772781671f92ec08f9d8713f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/amd/cezanne: Enable secure countersKarthikeyan Ramasubramanian2021-12-031-0/+1
| | | | | | | | | | | | | | | | | Guybrush uses secure counters to protect against High Definition (HD) protected content rollback. These secure counters are hosted in TPM NVRAM. Enable secure counters so that they are defined in PSP verstage. BUG=b:205261728 TEST=Build and boot to OS in Guybrush. Ensure that the secure counters are defined successfully in TPM NVRAM. Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/intel/alderlake: Add Kconfigs for all PCH typesAngel Pons2021-12-022-7/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | The Alder Lake code currently supports the PCH-M and PCH-P types, which have some differences (so far, only the amount of PCIe I/O). Mainboards can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which PCH type they use: select the option to choose PCH-M, do not select the option to choose PCH-P. While this works, it can be confusing once more PCH types are added. Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards have to explicitly choose a PCH type. Also, use this option to restrict the PCH-P defaults for PCH-dependent settings to avoid unintended reuse of the PCH-P defaults when adding a new PCH type. To make sure only one PCH type is selected, add some preprocessor in `bootblock.h` to provoke a build-time error if this requirement is not met. Kconfig doesn't seem to have a mechanism to describe sets of mutually-exclusive bool options that allows said options to be selected (a `choice` block doesn't allow its elements to be selected). Finally, adapt the ADL boards accordingly. Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* soc/intel/common/pmc: Drop unnecessary pmc_ipc.c entrySubrata Banik2021-12-011-1/+1
| | | | | | | | | | | This patch drops unnecessary `pmc_ipc.c` from Makefile as this file is getting included upon CONFIG_PMC_IPC_ACPI_INTERFACE selection. Change-Id: Ie66f0833daf033ec16210221610508f9fbb1e6c7 Signed-off-by: Subrata Banik <subi.banik@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1Felix Held2021-11-305-34/+36
| | | | | | | | | | | | | Despite Stoneyridge being one only SoC in soc/amd that uses the first generation of the PSP mailblox interface, this code is common for all SoCs that use the first PSP mailbox interface generation, so move it to the common PSP generation 1 code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59701 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: add missing PM_ACPI_* bit definitionsFelix Held2021-11-301-0/+16
| | | | | | | | | | | This part was copied from Picasso but Cezanne has some more bits used so add the definitions now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defsFelix Held2021-11-301-0/+2
| | | | | | | | | | | | | Both SPI_ROM_BIOS_SEMAPHORE and SPI_ROM_EC_SEMAPHORE bits in the LPC_PCI_CONTROL are defined in the Stoneyridge BKDG #55072 Rev 3.04, Raven1 and Picasso PPR #55570 Rev 3.18, Raven2 PPR #55772 Rev 3.08 and Cezanne PPR #56569 Rev 3.03 which are all platforms that use this code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* intel: cse_lite: Use cbfs_unverified_area APIJulius Werner2021-11-301-30/+8
| | | | | | | | | | | | This patch replaces the use of the deprecated cbfs_locate_file_in_region() API with the new cbfs_unverified_area_map(). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If4855280d6d06cf1aa646fded916fd830b287b30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-01 14:27:18 +0000