summaryrefslogtreecommitdiffstats
path: root/src/vendorcode/amd
Commit message (Expand)AuthorAgeFilesLines
* AGESA f15tn: Fix building IDS tracing supportAngel Pons2021-08-2216-38/+37
* AGESA f15tn: Hook up IDS options to KconfigAngel Pons2021-08-222-26/+61
* AGESA f15tn: Factor out common OptionsIds.hAngel Pons2021-08-222-1/+33
* AGESA f15tn: Drop `IDSOPT_ASSERT_ENABLED`Angel Pons2021-08-223-80/+0
* soc/amd/cezanne: enable crypto in psp_verstageKangheui Won2021-07-211-0/+52
* vc/amd/sb800: Cast to UINT32 for shift out of bounds fixPaul Menzel2021-07-121-3/+3
* vc/amd/sb800: Cast variable to 32-bit before shiftPaul Menzel2021-07-121-44/+44
* vc/amd/sb800: SBCMN: Cast to 32-bit before shiftPaul Menzel2021-07-121-6/+6
* vc/amd/fsp/cezanne/FspmUpd: add hda_enable UPDFelix Held2021-06-211-1/+2
* soc/amd/cezanne: Supply SMBIOS/DMI Type 17 dataNikolai Vyssotski2021-06-131-0/+236
* soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOBNikolai Vyssotski2021-06-071-2/+2
* cezanne/psp_verstage: add reset/timer svcKangheui Won2021-06-071-0/+35
* vc/amd/pi/00630F01: Remove unused directory and codeMichał Żygowski2021-05-2636-17356/+2
* soc/amd/cezanne: add support for the changed AMD FSP API for USB PHYJulian Schroeder2021-05-262-21/+63
* soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driverFelix Held2021-05-212-8/+0
* vc/amd/pi/00660F01: Remove unused code and directoryMichał Żygowski2021-05-1233-18238/+0
* src: Drop "This file is part of the coreboot project" linesAngel Pons2021-05-101-1/+0
* vc/amd/fsp/cezanne: Add AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUIDRaul E Rangel2021-05-061-0/+4
* vc/amd/fsp/cezanne/FspGuids: add AMD_FSP_ACPI_ALIB_HOB_GUIDFelix Held2021-05-051-0/+4
* vendorcode: add code for cezanne psp_verstageKangheui Won2021-05-025-0/+435
* amd/cezanne: Add telemetry setting to UPDChris Wang2021-04-301-2/+6
* vc/amd/agesa/f15tn/Config/PlatformInstall.h: enable the AMD CPB featureMike Banon2021-04-271-1/+1
* amd/cezanne: Add slow_ppt_time & thermctl_limit to UPDMartin Roth2021-04-261-1/+3
* src/vendorcode/amd/fsp/picasso: Add HDMI 2.0 Disable setting section of FspmU...Patrick Huang2021-04-261-1/+3
* vc/amd/fsp/cezanne:Add s0i_enable upd controlJason Glenesk2021-04-261-1/+2
* vc/amd/fsp/cezanne: update SMU setting section of FspmUpd.hFelix Held2021-04-201-15/+15
* vc/amd/fsp/cezanne/FspmUpd: use arrays for DXIO/DDI descriptorsFelix Held2021-04-071-19/+5
* vc/amd/fsp/cezanne: update UPD headersMatt Papageorge2021-04-072-99/+108
* vc/amd/fsp/cezanne: add platform_descriptors.hFelix Held2021-04-071-0/+218
* vc/amd/fsp/picasso/platform_descriptors: fix typos in enum element namesFelix Held2021-04-051-2/+2
* soc/amd: GOP: add UPD for VBIOS bufferNikolai Vyssotski2021-03-122-3/+5
* vc/amd/fsp/picasso: fix DDI enum name prefixFelix Held2021-03-041-3/+3
* vc/amd/fsp/picasso: increase FSPS UPD block size from 0x152 to 0x202Nikolai Vyssotski2021-03-031-2/+2
* src: use ARRAY_SIZE where possiblePatrick Georgi2021-02-1549-181/+188
* vc/amd/fsp/cezanne: add FspGuids.hFelix Held2021-02-091-0/+16
* soc/amd/picasso: add UPD for RV2 USB3 phy setting adjustChris Wang2021-02-051-1/+12
* drivers/intel/fsp2_0: Fix running on x86_64Patrick Rudolph2021-02-042-4/+17
* vendorcode/amd/fsp/cezanne: add UPD structs from FSP buildFelix Held2021-02-042-2/+99
* soc/amd/picasso: clean up and re-sort UPD tableChris Wang2021-02-031-20/+16
* soc/amd/picasso: Add UPDs for support eDP power sequence adjustChris Wang2021-01-251-10/+19
* soc,vendorcode/amd/cezanne: add basic FSP integrationFelix Held2021-01-244-0/+122
* sb/amd/pi/hudson: Enable use of common GPIO APIKyösti Mälkki2020-12-281-1/+1
* soc/amd/picasso: Add UPDs for support eDP phy tunning adjustChris Wang2020-12-211-1/+11
* amd_blobs: Always set default pathsNico Huber2020-12-051-5/+5
* src: Remove redundant use of ACPI offset(0)Elyes HAOUAS2020-12-032-4/+0
* vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profileMike Banon2020-12-0210-3/+337
* vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profilesMike Banon2020-12-025-24/+227
* cpu/amd/pi: Remove unused cpu code 00660F01Martin Roth2020-11-222-13/+2
* vc/amd/pi/00670F00: Add raw AGESA binary only to COREBOOT CBFSFurquan Shaikh2020-11-221-0/+1
* soc/amd/picasso: Update coreboot UPD variable names to include unitsZheng Bao2020-11-061-21/+21
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 18:13:20 +0000