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* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v3091_00Ronak Kanabar2022-03-071-2/+7
| | | | | | | | | | | | | | | | The headers added are generated as per FSP v3091_00 Previous FSP version was v2511_04 Changes include: - Update MemInfoHob.h BUG=b:222415800 BRANCH=None Change-Id: I260544e0502174ab141fa31ac78ede803b4f161e Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04Nick Vaccaro2022-01-132-77/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2511_04 Previous FSP version was v2471_02 Changes include: - UPDs description update in FspsUpd.h and FspmUpd.h - Adjust UPD Offset in FspmUpd.h - Name change of UPDs in FspmUpd.h and FspsUpd.h - Copyright year is updated in FspmUpd.h and FspsUpd.h - Updated spd_upds and dq_upds structure variables in meminit.c - Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask in fsp_params.c BUG=b:213959910 BRANCH=None TEST=Build and boot brya Cq-Depend: chrome-internal:4448696, chrome-internal:4445910 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> Change-Id: I39646c6812afbf622171361b8206daeacdaafac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* Revert "Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP ↵Tim Wawrzynczak2021-12-262-9/+8
| | | | | | | | | | | | | | | | v2471_02"" This reverts commit a4dddfc3a3a48727ebcec727a0b1fd87eb4c14ad. Reason for revert: Ready to land FSP 2471.02 Change-Id: I2d858edee2eb24506c3e55a1cb808a1ccbd58da2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
* Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02"Nick Vaccaro2021-12-212-8/+9
| | | | | | | | | | | | | | | | | This reverts commit ae0ea32c52905d6bcb527b04727463bc2d1b9e09. This change should not have merged until the 2471_02 FSP change is ready for merge. BUG=b:211481222 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot brya0 to kernel. Change-Id: Iae5b0c53ace196053e1e155efd2e08f438979ba7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02Ronak Kanabar2021-12-132-9/+8
| | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2471_02. Previous FSP version was v2422_01. Changes Include: - UPDs description update in FspsUpd.h - Adjust UPD Offset in FspmUpd.h and FspsUpd.h BUG=b:208336249 BRANCH=None TEST=Build and boot brya Change-Id: I4d04652c06a1c1823d3859be209710c273a2ae8c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01Ronak Kanabar2021-11-151-26/+28
| | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2422_01. Previous FSP version was v2374_01. Changes Include: - Add CnviDdrRfim UPD in FspmUpd.h - UPDs description update in FspmUpd.h BUG=b:205512463 BRANCH=None TEST=Build and boot brya Change-Id: Id25f7199ffd08a4a74585ea1269d927efa733b8c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2374_01Ronak Kanabar2021-09-282-8/+8
| | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2374_01. Previous FSP version was v2347_00. Changes Include: - Offset change in FspmUpd.h and FspsUpd.h BUG=b:201239436 BRANCH=None TEST=Build and boot brya Cq-Depend: chrome-internal:4150766 Change-Id: I097e854bcb4033bdaf2498fb97b255e87d3dd70f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57920 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2347_00Ronak Kanabar2021-09-101-3/+3
| | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2347_00. Previous FSP version was v2265_01. Changes include: - UserBd UPD description update in FspmUpd.h BUG=b:199359579 BRANCH=None TEST=Build and boot brya Change-Id: I5e4dd58e5fb1a744b035a4de96986053a02610d3 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2265_01Ronak Kanabar2021-07-302-30/+32
| | | | | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2265_01. Previous FSP version was v2237_00. Changes Include: - Add Irms UPD in FspsUpd.h - Adjust Reserved UPD Offset in FspsUpd.h - Few UPDs description update in FspmUpd.h BUG=b:194032028 BRANCH=None TEST=Build and boot brya Change-Id: I49b1187d9dcedade47951274db49b7bdc437679f Cq-Depend:chrome-internal:4004482 Cq-Depend:chrome-internal:4003608 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56511 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSPEric Lai2021-07-291-14/+17
| | | | | | | | | | | | | | | Sync the MemInfoHob.h with current FSP code. BUG=b:190339677 TEST=dmidecode -t 17 can show the memory information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I80d1252b1f12b164d4f6d3a01221507cdfbe4d08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00Ronak Kanabar2021-07-132-15/+22
| | | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2237_00. Previous FSP version was v2207_01. Changes Include: - Add VccInAuxImonIccImax in FspsUpd.h - Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:192199787 BRANCH=None TEST=Build and boot brya Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c Cq-Depend:chrome-internal:3970327,chrome-internal:3925290 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55896 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2207_01Ronak Kanabar2021-06-212-108/+121
| | | | | | | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2207_01. Previous FSP version was v2162_00. Changes Include: - Add IbeccProtectedRangeEnable, IbeccProtectedRangeBase and IbeccProtectedRangeMask in FspmUpd.h - Add UsbTcPortEn in FspsUpd.h - Adjust Reserved UPD Offset in FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:189731004 BRANCH=None TEST=Build and boot brya Change-Id: Ice44dfbd41e8eca4f171b76e7a3dcdf133a516fd Cq-Depend: chrome-internal:3876956, chrome-internal:3909162, chrome-internal:3909163 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55094 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSPEric Lai2021-06-101-0/+26
| | | | | | | | | | | | | Sync the MemInfoHob.h with current FSP code. BUG=b:190339677 TEST=dmidecode -t 17 can show the memory information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifd3e6a264131437c67d17ec80f37f5e8d0a03a79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00Ronak Kanabar2021-05-162-1082/+1084
| | | | | | | | | | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2162_00. Previous FSP version was v2117_00. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Remove DisableDimmMc*Ch* Upds in FspmUpd.h - Add DisableMc*Ch* Upds in FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid compilation failure other change related to UPDs name change will be part of next patch in relation chain. BUG=b:187189546 BRANCH=None TEST=Build and boot ADLRVP using all the patch in relation chain. Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2117_00Ronak Kanabar2021-04-162-72/+68
| | | | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2117_00. Previous FSP version was v2081_02. Changes Include: - Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h - Remove FivrFaults and FivrEfficiency Upds from FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:184129128 BRANCH=None TEST=Build and boot ADLRVP Change-Id: I068552084b1ef3e5c4fba7a46240d116c92c7b5b Cq-Depend: TBD Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02Ronak Kanabar2021-03-232-188/+5289
| | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2081_02. Previous FSP version was v2081_02. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Add UPDs in Fsps.h and Fspm.h BUG=b:180918805 BRANCH=None TEST=Build and boot ADLRVP Change-Id: I69611de8286a570c59a6b4a44b9164384e9be81f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51632 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02Ronak Kanabar2021-03-102-314/+331
| | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2081_02. Previous FSP version was v2037. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Add DevIntConfigPtr and NumOfDevIntConfig UPDs in Fsps.h BUG=b:180758116 BRANCH=None TEST=Build and boot ADLRVP Cq-Depend: chrome-internal:3669105 Change-Id: Ib99748a428709ffad27d47f600e00bd91b70d8f3 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51248 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2037Ronak Kanabar2021-02-252-78/+166
| | | | | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2037. Previous FSP version was v2037. Changes Include: - add BootFrequency, RMTBIT, RmtPerTask, RMTLoopCount and MrcFastBoot UPDs in Fspm.h - add EnableFastMsrHwpReq, VbtSize, CpuPcieComplianceTestMode, LidStatus and PcieComplianceTestMode UPDs in Fsps.h BUG=b:178461282,b:180627057 BRANCH=None TEST=Build and boot ADLRVP Change-Id: I5496dfebc7b65a94abb31244ef2b400d89d6d444 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50914 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp: Change line endings to unixMartin Roth2021-02-172-1871/+1871
| | | | | | | | | | | | These files have windows line endings. Change to unix to match the rest of the tree. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5bb3338745a6a47b6714aa268d16866aada27790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.hSubrata Banik2021-02-041-17/+10
| | | | | | | | | | | | | | | | The recent merge of Intel ADL FSP 2017.00 appears to have introduced a new dependency within the file MemInfoHob.h. Adding required macros to resolve the dependency. BUG=b:178846328 Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50254 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037Subrata Banik2021-02-032-215/+219
| | | | | | | | | | | | | | | List of changes: 1. FSP-M Header: - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust UPD Offset for Reservedxx Change-Id: I808cf619f43e629c6150726f2aa29e732e05fc33 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1514_11Subrata Banik2020-12-231-50/+64
| | | | | | | | | | | | | | List of changes: FSP-S Header: - Add UPD MicrocodeRegionBase and MicrocodeRegionSize - Adjust UPD Offset for Reservedxx Change-Id: I376abf6cd64dcf8c848901074e2c2f30d4f302da Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1512_11Subrata Banik2020-12-181-29/+29
| | | | | | | | | | | | | | List of changes: FSP-S Header: - Adjust UPD Offset for Reservedxx - Rename UPD Offset UnusedUpdSpace44 -> UnusedUpdSpace45 Change-Id: If0c18cbb556fc41786391464b76d7c9cc19eab0d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1483_11Subrata Banik2020-11-262-89/+88
| | | | | | | | | | | | | | | | | List of changes: 1. FSP-M Header: - Adjust UPD Offset for Reservedxx - Rename UPD Offset UnusedUpdSpace32 -> UnusedUpdSpace29 2. FSP-S Header: - Rename UPD Offset UnusedUpdSpace46 -> UnusedUpdSpace44 Change-Id: Ia1ef59e4cf6ccce8f48908af51535aea761cd972 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47901 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1474_11Subrata Banik2020-11-212-59/+55
| | | | | | | | | | | | | | List of changes: 1. FSP-M Header: - Rename UPD Offset UnusedUpdSpace33 -> UnusedUpdSpace32 2. FSP-S Header: - Adjust UPD Offset for Reservedxx Change-Id: I99294da825f47135d1336a6ad90b1c9bb73eb849 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1454Subrata Banik2020-11-132-36/+46
| | | | | | | | | | | | | | | | | | List of changes: 1. FSP-M Header: - Add new UPD Lp5CccConfig - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust UPD Offset for Reservedxx, PsOnEnable, RpPtmBytes, PmSupport, GtFreqMax, Hwp, TccActivationOffset, Cx, PchLockDownGlobalSmi, PcieRpLtrMaxSnoopLatency, PcieRpLtrMaxNoSnoopLatency, UnusedUpdSpace45 Change-Id: I973f48b2af0336f04ee16cd1c4c91940a49af0e3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47244 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp/fsp2_0/adl: Update FSP header file version to 1432Subrata Banik2020-10-252-272/+291
| | | | | | | | | | | | | | | | | | | List of changes: 1. FSP-M Header: - Add new UPD GpioOverride - Change help text for PlatformDebugConsent UPD - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust Reservedxx UPD Offset - PcieRpLtrMaxSnoopLatency and PcieRpLtrMaxNoSnoopLatency array grew by 4 elements Change-Id: I54aabd759b99df792b224f91ce94927275dd9b80 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46695 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp/fsp2_0/adl: Update FSP header to version 1332.01Subrata Banik2020-10-141-22/+32
| | | | | | | | | | | | | | | List of changes: - Add FSP-M UPD 'TmeEnable' TEST=Build and boot ADLRVP platform. Change-Id: Ic5fad998e880e9302b068fc78c28074fa432f1ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46295 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/intel/fsp/alderlake: Fix FSPS_ARCH_UPD redefinition issueSubrata Banik2020-09-101-30/+0
| | | | | | | | | | | | | | FSPS_ARCH_UPD struct is part of edk2-stable202005 branch (FspApi.h) hence local definition of FSPS_ARCH_UPD inside FspsUpd.h is causing compilation issue. Change-Id: Id5b3637d9ab6d87aab6da810f9c83d3258900a29 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
* vendorcode/intel/fsp/fsp2_0/adl: Add FSP header file version 1332Subrata Banik2020-09-095-0/+2258
List of changes: 1. Select FSP_HEADER_PATH 2. Select FSP_FD_PATH 3. Select PLATFORM_USES_FSP2_2 4. Select UDK_202005_BINDING Change-Id: Ic5b09bad3c23b84c6ff6b1ea9e1dc684d7463c27 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-10 11:59:52 +0000