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* mb/google/brya/variants/nereid: Add DPTF passive and critical policies for ↵Vidya Gopalakrishnan2022-06-031-0/+52
| | | | | | | | | | | | | | | | | | | Nereid BUG=b:233030505 BRANCH=None TEST=Build FW and test on Nereid board. Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: I195f4b507ee57948751f0119735d8350dfce984b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
* ec/google/chromeec/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer2022-06-031-1/+1
| | | | | | | | | | Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Iea86e77df6c76756ed336f57a906ac0757aef1cf Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/google/chromeec/acpi: Replace Divide(a,b,,c) with ASL 2.0 syntaxFelix Singer2022-06-032-6/+6
| | | | | | | | | | Replace `Divide (a, b, , c)` with `c = a / b`. Change-Id: I26117087c09109cfc480cbe01d3761a02a12c61b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/google/chromeec/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-06-034-11/+11
| | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: I4d79080ecfe457766983b20a0217ccadcd188fcf Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/google/chromeec/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer2022-06-031-1/+1
| | | | | | | | | | Replace `LLess(a, b)` with `a < b`. Change-Id: I65225a890f9085574a2295e6ccd2cdc3e84f71e0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* arch/x86/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer2022-06-032-3/+3
| | | | | | | | | | Replace `LGreater(a, b)` with `a > b`. Change-Id: I0cabf4f69191fe345fd72619847db384db2e0e87 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/google/chromeec/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-06-031-1/+1
| | | | | | | | | | Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: I72875f68e143f9384c91588cd453d2987fda526d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* cpu/x86/smm_module_loader: Update loggingArthur Heymans2022-06-031-1/+1
| | | | | | | | | | | | Some logging is superfluous and logging that code is being copied is 'SPEW' level. Change-Id: I84d49a394cc53d78f1e1d3936502ac16810daf9f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/nissa/craask: Configure the external V1p05/Vnn/VnnSxTyler Wang2022-06-031-0/+15
| | | | | | | | | | | | | | | | | | | | This patch configures external V1p05/Vnn/VnnSx rails for Craask to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:233717182 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I95d24c0836f3ee02006868341ccc72d762c155d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* soc/intel/elkhartlake: Select SOC_INTEL_RAPL_DISABLE_VIA_MCHBARUwe Poeche2022-06-031-0/+1
| | | | | | | | | | | | | | | | Since of moving RAPL disabling to common code a config switch is available to select that RAPL disabling has to be done via MCHBAR. This patch selects the switch for EHL. Test: Boot mc_ehl1 and ensure that relevant bits in MCHBAR are the same as before the patch. Change-Id: I1d0b7f650aa3ccf89c5c35d9b60a83a1ce48c74f Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/google/nissa/var/nivviks: Enable ISH when UFS is presentReka Norman2022-06-031-0/+3
| | | | | | | | | | | | | | | | | | | | | In order to enable the UFS controller (PCI device 12.7), the PCI specification says that the device at function 0 in the same slot must also be enabled, which is the ISH. Therefore, enable ISH when UFS is present. For more context on why this is necessary, see CB:62662 which enabled UFS and ISH for adlrvp_n. BUG=b:234136500 TEST=Build test. Will test that UFS works once we have hardware. Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: Ib60d44322cfbd8f82c33ecac7598881dfb1d0c3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Daniil Lunev <dlunev@chromium.org>
* amdblocks/smm.h: Add header guardsArthur Heymans2022-06-031-0/+5
| | | | | | | | | | Change-Id: I5d01c36fa4695ee42d18701a90d1b96bceb5045f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* intel/common/block: move RAPL disabling to common codeUwe Poeche2022-06-034-21/+32
| | | | | | | | | | | | | | | | | | This patch brings the feature of disabling RAPL to common code. It replaces the current solution for APL and EHL. For special case if RAPL disabling is only working via changes in MCHBAR a new config switch was introduced. Test: Boot mc_apl4/5 with this patch and ensure that the relevant bits in MSR 0x610 are the same as before the patch. Change-Id: I2098ddcd2f19e3ebd87ef00c544e1427674f5e84 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/purism/librem_mini: Hide Linux GPIO LED from WindowsMatt DeVillier2022-06-021-0/+1
| | | | | | | | | | | | | | | | | Hide the Linux gpio-led ACPI device from Windows by setting the device status (_STA) to 0xB (enabled, hidden) so Windows doesn't show an unknown device/missing drivers in Device Manger. Linux doesn't care about the _STA value. Test: build/boot Windows (10/11) and Linux (PureOS 10) on a Librem Mini v2, verify LED works under Linux, is ignored under Windows Change-Id: If3ee0db685a2f7dab505602afa98c3c2d5adf5d3 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* mb/google/brya: Add new skolas baseboardNick Vaccaro2022-06-0220-1/+2176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the skolas baseboard, which is basically the brya baseboard, but using an Intel Raptor Lake-P SoC instead of an Alder Lake SoC. This commit also adds the skolas baseboard variant skolas4es. Since this baseboard is identical to the brya baseboard with the exception of the SoC used, the new baseboard and the new baseboard's first variant will be a copy of the current brya baseboard and brya0 variant. For now, the skolas baseboard and skolas4es variant will continue to use ADL-P. This allows for two benefits: 1. software to be proven out on existing hardware prior to RPL SoC support landing, and 2. allows us not to have to wait for RPL SoC changes prior to getting the mainboard changes in place Once the RPL SoC code has merged, I will update the skolas baseboard and skolas4es variant to use RPL instead of ADL. BUG=b:229134437 TEST=util/abuild/abuild -p none -t google/brya -x -a -c max Change-Id: Iec100306dca2320eaf2432797f3acc31db2543d3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* cpu/x86/mp_init.c: Prolong delay on synchronous APIArthur Heymans2022-06-022-3/+3
| | | | | | | | | | | When each AP needs to do a lot of printing 1 sec is not enough. Change-Id: I00f0a49bf60f3915547924c34a62dd0044b0c918 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64828 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
* mb/google/brya/variants/osiris: Remove KB_MT from overridetreeDavid Wu2022-06-021-4/+0
| | | | | | | | | | | | | | All Osiris SKUs use the new RGB gaming keyboard, so don't need the fw_config to decide keyboard matrix. BUG=b:220800586 TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I19211c345de0b315d65ec64efc70826e81315810 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
* soc/intel/alderlake: add power limits for Alder Lake-N SKUsVidya Gopalakrishnan2022-06-022-0/+26
| | | | | | | | | | | | | | | | This patch adds support for the ADL-N SKUs based on the PCH ID. Document reference: 645548 (ADL-N EDS Volume 1). BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Change-Id: I24c18a27a4a2c68c78bc3dc728c45ba04f57205d Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64472 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/intel/adlrvp: Enable DPTF for ADL-N RVPVidya Gopalakrishnan2022-06-021-0/+101
| | | | | | | | | | | | | | | BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Verified fan control successfully when participant reaches temp threshold as per Active Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Icafacfca6a026ec3b42906790831f11fd2f1b085 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/intel/adlrvp: Set power limits dynamically for ADL-N SKUsVidya Gopalakrishnan2022-06-021-0/+4
| | | | | | | | | | | | | | | | This patch adds support for the ADL-N SKUs based on the PCH ID. Document reference: 645548 (ADL-N EDS Volume 1). BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Ie49398b8a7de8d8cff3536eae6a5e893980f9c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* soc/intel/common/cpu: Use SoC overrides to set CPU privilege levelSubrata Banik2022-06-0212-0/+101
| | | | | | | | | | | | | | | | This patch implements a SoC overrides to set CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* cpu/intel/model_fxx: Select SSE2Arthur Heymans2022-06-023-0/+3
| | | | | | | | | | | | | Starting from Intel Pentium 4, cpus featured SSE2. This will be used in the follow-up patches to determine whether to use mfence as this instruction was introduced with the SSE2 feature set. Change-Id: I8ce37d855cf84a9fb9fe9e18d77b0c19be261407 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* cpu/x86/smm_module_loader: Drop superfluous checksArthur Heymans2022-06-021-47/+5
| | | | | | | | | | | Checking if the stack encroaches on the entry points is done in other parts of the code. Change-Id: I275d5dda9c69cc89608450ae27dd5dbd581e3595 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mb/google/nissa/var/craask: Disable PCIe WLAN pinsTyler Wang2022-06-021-0/+4
| | | | | | | | | | | | | | Craask uses CNVi WLAN, so disable the PCIe-related GPIOs. BUG=b:229040345 Test=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I7bcf041503dcee448758dac46b1c9711d0b02ba3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* nb/intel/i440bx: Use PARALLEL_MPArthur Heymans2022-06-022-6/+15
| | | | | | | | | | | | The ramstage size is decreased by roughly 5K, but the compressed size increased by ~1K. Change-Id: Ic8d2582b353069eecea8561cfe01b2dd8221779b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59693 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/mp.h: Implement a pre-SSE2 mfenceArthur Heymans2022-06-021-1/+5
| | | | | | | | | | | | Taken from the Linux Kernel. Tested: Qemu using '-cpu pentium3' now boots. Change-Id: I376f86f4d7992344dd68374ba67ad3580070f4d8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mb/lenovo/w541/Kconfig: sort alphabeticallyPeter Lemenkov2022-06-011-1/+1
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I9cefa29738b42dd08cb00489ad6e8644e3fc405e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/t440p/Kconfig: remove duplicates and sort alphabeticallyPeter Lemenkov2022-06-011-3/+1
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I47fded50377ab624e4bceb320a5e069a7f36c2fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/t440p/hda_verb: WhitespacePeter Lemenkov2022-06-011-1/+1
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I92c167bf95e605e098324b9e80cfaab8f589dcab Reviewed-on: https://review.coreboot.org/c/coreboot/+/63995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/w541/hda_verb: WhitespacePeter Lemenkov2022-06-011-1/+1
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I284a5e39ca4b0032ed0c8e3a92c095db319d1691 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/w541/dsdt.asl: Remove redundant commentFelix Singer2022-06-011-1/+0
| | | | | | | | | Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: Ide938a40ed1f6869ee248ed46f6bf29f95649490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/t440p/cmos: Remove unused optionsPeter Lemenkov2022-06-011-4/+0
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I9bf95ed74468e283bab79a5f25aee758d37d926a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verificationJulius Werner2022-06-012-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Intel Firmware Interface Table (FIT) is a bit of an annoying outlier among CBFS files because it gets manipulated by a separate utility (ifittool) after cbfstool has already added it to the image. This will break file hashes created for CBFS verification. This is not actually a problem when booting, since coreboot never actually loads the FIT from CBFS -- instead, it's only in the image for use by platform-specific mechanisms that run before coreboot's bootblock. But having an invalid file hash in the CBFS image is confusing when you want to verify that the image is correctly built for verification. This patch adds a new CBFS file type "intel_fit" which is only used for the intel_fit (and intel_fit_ts, if applicable) file containing the FIT. cbfstool will avoid generating and verifying file hashes for this type, like it already does for the "bootblock" and "cbfs header" types. (Note that this means that any attempt to use the CBFS API to actually access this file from coreboot will result in a verification error when CBFS verification is enabled.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1c1bb6dab0c9ccc6e78529758a42ad3194cd130c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cbfs: Rename TYPE_FIT to TYPE_FIT_PAYLOADJulius Werner2022-06-015-5/+5
| | | | | | | | | | | | | | There are too many "FIT" in firmware land. In order to reduce possible confusion of CBFS_TYPE_FIT with the Intel Firmware Interface Table, this patch renames it to CBFS_TYPE_FIT_PAYLOAD (including the cbfstool argument, so calling scripts will now need to replace `-t fit` with `-t fit_payload`). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I826cefce54ade06c6612c8a7bb53e02092e7b11a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* sc7180: Trogdor to support 2 dcbSudheer Kumar Amrabadi2022-06-012-0/+35
| | | | | | | | | | | BUG=b:227946776 TEST=Validated on sc7180 Lazor board Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Change-Id: Ie4d7f7f0b24aee06ffb272b21b74fea4160fe87c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brya/var/agah: Enable EC keyboard backlightTony Huang2022-06-011-0/+3
| | | | | | | | | | | BUG=b:210970640 TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I90d9f2e298e54832bc077eae1c8be0e39c151d90 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/mediatek/mt8186/pll.c: Fix typo in log messageElyes Haouas2022-06-011-1/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ied8eb0fb51d0521eedd8ff77b1083813d3843570 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/brya/var/kinox: Set memory SMBus addresses based on board revDtrain Hsu2022-06-011-2/+10
| | | | | | | | | | | | | | | Starting with id 2, boards switched the memory SMBus slave address, and use 0x50, 0x52. BUG=b:233975373 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I5e683ffdbc0727259ee796610cd97a6e378bf335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* driver/intel/fsp2_0: Disable NULL deref code when calling FSPArthur Heymans2022-06-015-9/+31
| | | | | | | | | | | | | FSP needs interrupts disable so also disable generating exceptions around debug registers. Change-Id: Ia49dde68d45b71e231aaf32a0e6fd847f0e06146 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64426 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/corsola: Add new board 'steelix'Zanxi Chen2022-06-012-0/+5
| | | | | | | | | | | | | | Add a new kingler follower 'steelix'. BUG=b:232195941 TEST=make # select steelix Change-Id: Idd2ed1404cde72ecdb6cc3a262e793a6272aa871 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEGArthur Heymans2022-06-015-5/+18
| | | | | | | | | | | Tested with SMI_DEBUG: SMM prints things on the console. Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Revert "cpu/x86/mtrr: Make useful MTRR functions available for all boot stages"Arthur Heymans2022-06-013-71/+60
| | | | | | | | | | | | | | This code is only meant to be used in early stages so move it back to earlymtrr.c. This reverts commit 3ad00d0c89c9e7a8e9ef13b6dc65bb338a191ec8. Change-Id: I9bc1ac4b863eb43d3e398e6462ee139a7751bf62 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64804 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/fast_spi: Use smarter mtrr code in ramstageArthur Heymans2022-06-011-0/+5
| | | | | | | | | | | | | | mtrr_use_temp_range is a lot smarter than the plain set_var_mtrr. It will compute a new optimal solution with the temp ranges included while also taking care of the cleanup before loading the payload/s3 resume. Change-Id: I283ba07fc12c410be39dfdc828657598237247c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63550 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "cpu/x86: Add function to set `put_back_original_solution` variable"Arthur Heymans2022-06-012-7/+1
| | | | | | | | | | | | | | Now that mtrr_use_temp_range() can deal with multiple ranges there is no need to expose this to restore the MTRR solution. This reverts commit 00aaffaf470adfbaa0fbfa0ec3cc67311763810b. Change-Id: Ib77a0f52228cd2f19f3227824f704ac690be4aba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64803 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/mtrr: Allow for multiple TEMP MTRR rangesArthur Heymans2022-06-011-1/+28
| | | | | | | | | | | | | | | | | | | Temporary MTRR setup usually covers the memory mapped flash. On recent Intel hardware the mapping is not coherent. It uses an external window for parts of the BIOS region that exceed 16M. This now allows up to 10 temporary memory ranges. TESTED: Qemu with multiple MTRR temporary MTRR ranges sets up a valid and optimized temporary MTRR solution. Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/craask: Add ACPI _PLD custom valuesWon Chung2022-06-011-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia288937ef3a4229088b60d87d31ea88057377a71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya/var/nivviks: Add ACPI _PLD custom valuesWon Chung2022-06-011-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: If2a77c0239646759e0192b72ba1991d334dd15aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/64730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya/var/nereid: Add ACPI _PLD custom valuesWon Chung2022-06-011-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I47b069377046652ba4d278733a15bbca98bdb739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya/var/kinox: Add delay time for BH799BB rtd3Dtrain Hsu2022-06-011-0/+2
| | | | | | | | | | | | | | | | | | This CL adds the delay time into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. We checked power on sequence requires enable pin prior to reset pin delay of 50ms and add delay of 20ms to meet the sequence on various eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:232327947 TEST=Build and suspend_stress_test -c 2500 pass Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I42cde5336f73a446cf5157e78f955fef8d70ae7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/dedede/beadrix: Add fw_config probe for ALC5682-VD & VSTeddy Shih2022-06-011-1/+25
| | | | | | | | | | | | | | | | | | | | | | ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BRANCH=dedede BUG=b:226910787,b:232057623 TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I059b750743ab3b29d17c50d0d4301fbae4873acc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-09 09:34:07 +0000