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* soc/amd/common: move block/pi out of the block folderFelix Held2021-09-2413-9/+7
| | | | | | | | | | | | | | | Since the binaryPI glue code is specific to a binary interface, but not for a hardware block, move it out of the common blocks directory. This also brings the binaryPI support in line with the FSP support which is used on the newer generations. This also drops the SOC_AMD_COMMON_BLOCK_PI Kconfig option and makes use of the already existing SOC_AMD_PI Kconfig option instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I014e538f2772938031950475e456cc40dd05d74c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block: move binaryPI S3 block into PI blockFelix Held2021-09-246-15/+6
| | | | | | | | | | | | | | | | | The code in soc/amd/common/block/s3 is specific to the AMD binaryPI coreboot integration, so move the code to soc/amd/common/block/pi. This drops the SOC_AMD_COMMON_BLOCK_S3 Kconfig option and integrates the dependencies and selections into the SOC_AMD_COMMON_BLOCK_PI Kconfig option. Since only selecting SOC_AMD_COMMON_BLOCK_PI but not SOC_AMD_COMMON_BLOCK_S3 resulted in missing functions in the linking process, we don't lose support for any working configuration by only having one Kconfig option for both parts. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib2bd99a88d8b05216688bc45d9c4f23a007ce870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/intel/alderlake: add MaxDramSpeed configCasper Chang2021-09-242-0/+4
| | | | | | | | | | This change add MaxDramSpeed for variants usage to config dram speed. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Iba0fae0ab4ff0121dc63af792458492eeb21ec2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/dedede/var/magolor: Add ssfc codec DA7219 supportTyler Wang2021-09-242-1/+29
| | | | | | | | | | | | | | | Add DA7219 codec support in maglet. BUG=b:198239769, b:196193562 TEST:emerge coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I52d980ed611b3fbe4892cd3e65e3b35931feaba5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/common/blocks/include: rename gpio_banks.h to gpio.hFelix Held2021-09-2328-27/+27
| | | | | | | | | | | This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/blocks: rename gpio_banks folder to gpioFelix Held2021-09-233-0/+0
| | | | | | | | | | | This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3dfcca2f126eb49c962b5cc32cbcf72e04f3f170 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/intel/adlrvp_m: Enable HECI1 communicationzhixingma2021-09-231-0/+3
| | | | | | | | | | | | | | The patch enables HECI1 interface to allow OS applications to communicate with CSE. TEST=Verify PCI device 0:16.0 exposed in the lspci output Signed-off-by: zhixingma <zhixing.ma@intel.com> Change-Id: Ifd338345caa183f03097f1003080992da70296ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/57813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* soc/amd: rename program_gpios to gpio_configure_padsFelix Held2021-09-2333-44/+44
| | | | | | | | | | | | | | | | | Use the same function name as in soc/intel for this functionality. This also brings the function name more in line with the extended version of this function gpio_configure_pads_with_override which additionally supports passing a GPIO override configuration. This might cause some pain for out-of-tree boards, but at some point this should be made more consistent, so I don't see a too strong reason not to do this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd,intel/common/include/gpio: improve documentation of overridesFelix Held2021-09-232-2/+4
| | | | | | | | | | | | | Explicitly point out that gpio_configure_pads_with_override will ignore GPIOs that are only in the override configuration, but not in the base configuration. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1bdfcac89b81fef773938133a2699897c6ee9415 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/brya/variants/gimble: Update DPTF sensorsMark Hsieh2021-09-231-3/+4
| | | | | | | | | | | | | | | Add two thermal sensors for fan and charger for DPTF based thermal control. BUG=b:199180746 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I1529dd5dff3445dd499ed665386a9b06d67c7028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57833 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/gimble: Update audio settingMark Hsieh2021-09-231-0/+6
| | | | | | | | | | | | | Add vmon-slot-no,imon-slot-no and dsm_param_file_name in overridetree.cb BUG=b:197701952 TEST=build and check SSDT Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie646360c4ebbf25762b374c5bc3ef2017989fb2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57832 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google: Update comments in mem_parts_used.txt to match new templatesReka Norman2021-09-2320-40/+40
| | | | | | | | | | | BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iafcbb3ce33cd2299ff98b54b9200f3e70929fb1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google: Bulk rename mem_list_variant.txt to mem_parts_used.txtReka Norman2021-09-2390-60/+60
| | | | | | | | | | | | | | | | | | | | | | | | The variant creation script creates a placeholder file called mem_parts_used.txt, with the intent that variant owners will populate this file with memory parts as needed. But instead, some partners have been adding the parts in a new file called mem_list_variant.txt and removing the placeholder file. E.g. https://review.coreboot.org/55735. There's nothing wrong with this, but it's confusing to have two different file names which serve the same purpose. Bulk rename all the mem_list_variant.txt files to mem_parts_used.txt. The only time these file names are used is as an argument to the spd_tools part_id_gen script, so no other changes are necessary. BUG=None TEST=Re-run part_id_gen for all variants of brya/volteer/dedede/guybrush/zork. Check that the only change is to the "Generated by" comment in Makefile.inc and dram_id.generated.txt. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Icdeee78ae5c01e97f66c759c127175b4962d5635 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/volteer: Remove unused mem_parts_used.txt from copano/collisReka Norman2021-09-232-22/+0
| | | | | | | | | | | | | | | The copano and collis variants have both a mem_parts_used.txt and a mem_list_variant.txt. The mem_parts_used.txt files are empty, so delete them. BUG=None TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ia98aad7238b0173b8d5c048d89637bc297d02283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/zork: Migrate zork to use SPD files under spd/Reka Norman2021-09-2343-460/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all zork variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for dalboz: util/spd_tools/bin/part_id_gen \ PCO \ ddr4 \ src/mainboard/google/zork/variants/dalboz/spd \ src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/zork -a -x --timeless Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I305a24f9345bab28ff35e317b6e7fd7efba22413 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57772 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/xeon_sp/cpx: Use FSP repoArthur Heymans2021-09-239-1133/+145
| | | | | | | | | | | Some headers in vendorcode are still needed but the UPD definitions can be taken from the FSP repo. Change-Id: I7bb96649ecba9d313cfce50af202aabcf610680f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/xeon_sp/cpx: Rename FSP UPDs using CPPArthur Heymans2021-09-233-8/+13
| | | | | | | | | | | | coreboot expects different names for FSP UPDs so use some CPP to make it happy. Change-Id: I4b2c2dd6ba40cb58bc2089eb9204fd4f70b037aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/xeon_sp: correct wrong gpio register base offsetsMichael Niewöhner2021-09-231-4/+4
| | | | | | | | | | | | Reference: Intel doc# 633935-005 and 547817 rev1.5. Change-Id: I38c20288a9839f8c3cf895f7b49941387bdca5e2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Lance Zhao Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* soc/intel/tgl: correct wrong gpio GPI enable register base offsetMichael Niewöhner2021-09-231-1/+1
| | | | | | | | | | | Reference: Intel doc# 631120-001. Change-Id: Iaf3a1b7bc38a1b30f8cc901bd6496e77f2d92cfd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/icelake: correct wrong gpio SMI register base offsetsMichael Niewöhner2021-09-231-2/+2
| | | | | | | | | | | Reference: Intel doc# 341081-002. Change-Id: If6e0503cc042c26c4077b8b32bb447d4e3a9bb6a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registersMichael Niewöhner2021-09-2312-0/+62
| | | | | | | | | | | | | | | | | | | Add NMI_EN and NMI_STS registers, so NMI interrupts can be used. References: - XEON-SP: Intel doc# 633935-005 and 547817 rev1.5 - ICL-LP: Intel doc# 341081-002 - TGL-LP: Intel doc# 631120-001 - TGL-H: Intel doc# 636174-002 - JSL: Intel doc# 634545-001 - EHL: Intel doc# 636722-002 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I2621f4495dfd4f95f9774d9081e44c604de830a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
* soc/intel/icl: add missing gpio group to fix the group indexesMichael Niewöhner2021-09-232-41/+50
| | | | | | | | | | | | | There is another gpio group, namely HVCMOS, between GPP_C and GPP_E. Add it, so the group index calculation for GPI/SMI/NMI results in the correct value. Reference: Linux linux/drivers/pinctrl/intel/pinctrl-icelake.c Change-Id: I7725191173ddc0d43bbe940cdf3b0dc2aa3e5f8d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/hatch/moonbuggy: copy PCIe configuration from genesisJeff Chase2021-09-232-13/+98
| | | | | | | | | | | | | | The moonbuggy pcie topology is the same as genesis so copy from its device tree and gpios in order to enable these devices. BUG=b:199746414 TEST=lspci Change-Id: I4e916a95047b9f955734f164d7578c520478f5af Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/brya/var/anahera: Update gpio and devicetreeWisley Chen2021-09-235-4/+559
| | | | | | | | | | | | | Based on latest shcematic to update the device tree and gpio. BUG=b:197850509 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: I0a999de479c7b2e4776a57e1e56b1568450ec31a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* elog: calculate year correctly in timestampRicardo Quesada2021-09-232-2/+2
| | | | | | | | | | | | | | | | | | | This CL uses a 16-bit value (instead of an 8-bit value) for the year. This is needed because the function internally does a "year % 100", so the year should not be truncated to 8-bit before applying the modulo. This fixes a regression introduced in commit e929a75. BUG=b:200538760 TEST=deployed coreboot. Manually verified that year is correct using "elogtool list" TEST=test_that -b $BOARD $DUT firmware_EventLog Change-Id: I17578ff99af5b31b216ac53c22e53b1b70df5084 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/guybrush: Migrate guybrush to use SPD files under spd/Reka Norman2021-09-2318-391/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all guybrush variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for guybrush: util/spd_tools/bin/part_id_gen \ CZN \ lp4x \ src/mainboard/google/guybrush/variants/guybrush/memory \ src/mainboard/google/guybrush/variants/guybrush/memory/mem_list_variant.txt For dewatt, the Makefile.inc was manually modified to use the new placeholder value. BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/guybrush -a -x --timeless Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I48ca430b80b892d68dad582b1d9937a9edafa5d4 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/dedede: Migrate dedede to use SPD files under spd/Reka Norman2021-09-2362-466/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all dedede variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for cret: util/spd_tools/bin/part_id_gen \ JSL \ lp4x \ src/mainboard/google/dedede/variants/cret/memory \ src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt For cappy, the Makefile.inc was manually modified to use the new placeholder value. BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/dedede -a -x --timeless Change-Id: I2871ff45d6202520d4466b68a4d5bb283faf2b63 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/dedede: Remove unnecessary fixed IDs from galtic mem_parts_used.txtReka Norman2021-09-232-17/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, trying to regenerate the galtic Makefile.inc and dram_id.generated.txt using part_id_gen fails due to duplicate fixed IDs in the mem_parts_used.txt file. Remove the fixed IDs since they aren't needed. The part IDs assigned are the same either way. Also delete the comments from mem_parts_used.txt, since lp4x/gen_part_id currently doesn't support comments. BUG=b:191776301 Regenerate the Makefile.inc and dram_id.generated.txt using gen_part_id, and check that the part IDs don't changed. Command used: util/spd_tools/lp4x/gen_part_id \ src/soc/intel/jasperlake/spd \ src/mainboard/google/dedede/variants/galtic/memory \ src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ida83814b2f19b4a56eb9fde5939fa6c7874803c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/volteer: Migrate volteer to use SPD files under spd/Reka Norman2021-09-2357-648/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all volteer variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for voema: util/spd_tools/bin/part_id_gen \ TGL \ lp4x \ src/mainboard/google/volteer/variants/voema/memory \ src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/volteer -a -x --timeless Change-Id: Ibd4f42fd421bfa58354b532fe7a67ee59dac5e1d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Migrate brya to use SPD files under spd/Reka Norman2021-09-2326-332/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all brya variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for anahera: util/spd_tools/bin/part_id_gen \ ADL \ lp4x \ src/mainboard/google/brya/variants/anahera/memory \ src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/brya -a -x --timeless Change-Id: I08efe1d75438c81161d9b496af2fa30ce6f59ade Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* lib/Makefile.inc: Generate placeholder spd.bin in lib/Makefile.incReka Norman2021-09-231-8/+12
| | | | | | | | | | | | | | | | | | | | | When a new variant is created, it needs to have a path to its SPD binary defined. Currently, this is done by setting SPD_SOURCES to a placeholder SPD file, which just contains zero bytes. To remove the need for a placeholder file, automatically generate a single-byte spd.bin in lib/Makefile.inc when SPD_SOURCES is set to the marker value 'placeholder'. BUG=b:191776301 TEST=Change cappy/memory/Makefile to `SPD_SOURCES = placeholder`. Build and check that spd.bin contains a single zero byte. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I11f8f9b7ea3bc32aa5c7a617558572a5c1c74c72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/qualcomm/common: Move UART SC7180 driver to common sectionRajesh Patil2021-09-232-5/+5
| | | | | | | | | | | | | | | Move existing UART driver from sc7180 to common folder. This implements UART driver for QCOM SoC's BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I7bc2d3765f956e04bae3e45c3a9b9e2ad424c7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* mb/google/brya/var/taeko: Correct IOM port configurationJoey Peng2021-09-231-0/+3
| | | | | | | | | | | | | Enable programming of Type-C AUX DC bias GPIOs. BUG=b:199833078 TEST=Verify that a Type-C monitor works when connected in both orientations. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I4f6d80a9f2fc8cdc93226d6c234b54e5db830d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/amd/common/block/gpio_banks: Rework GPIO pad configurationFelix Held2021-09-221-39/+23
| | | | | | | | | | | | | | | | | | | | | | Before this patch, gpio_configure_pads_with_override called program_gpios once for each GPIO that needed to be configured which resulted in base_num_pads - 1 unneeded master_switch_set/ master_switch_clr sequences for the gpio_configure_pads_with_override call. Instead implement gpio_configure_pads_with_override as the more generic function and program_gpios as a special case of that which passes an empty override configuration and override pad number to gpio_configure_pads_with_override. TEST=GPIO configuration and multiplexer register values are the same for all GPIOs on google/guybrush right before jumping to the payload before and after the patch. Change-Id: Ia8e47b2a278a1887db5406c1f863ddafa6a68675 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/system76/addw1: Add Adder WS 2 as a variantTim Crawford2021-09-229-1/+2661
| | | | | | | | | Change-Id: I3965a90151bd9250a87dabc715d68a39699ff9e1 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/system76/addw1: Add System76 Adder Workstation 1Tim Crawford2021-09-2222-0/+2266
| | | | | | | | | Change-Id: I5dd3bc320ca640728e1d86180c6bfa0dc7295760 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ec/google/chromeec: Update ec_commands.hRob Barnes2021-09-221-2/+25
| | | | | | | | | | | | | | | This change copies ec_commands.h directly from Chromium OS EC repo at sha 8c2c6bd5b1d44b367929af498d4d4b0df126a4ef. BUG=b:188073399 TEST=Build coreboot BRANCH=None Change-Id: I674cb860adb6b8497a8aecf47952ed8f85ddaa70 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* soc/intel/alderlake: Drop unused HECI_DISABLE_USING_SMM KconfigSubrata Banik2021-09-221-1/+0
| | | | | | | | | | | | | | | | | | | | Earlier generation platform used `HeciEnabled` chip config (set to 0) and HECI_DISABLE_USING_SMM Kconfig to make the CSE function disable at the end of the post. `HeciEnabled` chip config remains enabled in all latest generation platforms hence drop HECI_DISABLE_USING_SMM Kconfig selection from SoC Kconfig as CSE remains default enabled. BUG=b:200644229 TEST=No functional impact during boot as CSE (B:0, D:0x16, F:0) device is listed with `lspci`. Change-Id: I5278e5c2e015b91bb3df3a3c73a6c659a56794b5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* mb/google/brya/var/redrix: Update audio settingWisley Chen2021-09-222-8/+29
| | | | | | | | | | | | | | | Update codec/amp setting. 1. Update hid for ALC5682VS 2. Add maxim properties. BUG=b:197076844 TEST=build and check SSDT Change-Id: I8bedd4d0737caf46769ad27bce1768c225ce8a82 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/redrix: Correct SSD power sequenceWisley Chen2021-09-221-0/+8
| | | | | | | | | | | | | | | | | | | | The current power sequencing for the SSD does not work in a non-serial enabled BIOS image. It appears that the FSP scans the PCIe RPs before the SSD has time to prepare itself for PCIe, so the FSP disables the RP and so depthcharge cannot find a boot disk. Changing the power sequence timing to enable power in bootblock and deassert reset in ramstage follows the SSD's power sequence and allows it to be discovered by the FSP so the RP does not get disabled. BUG=b:199714453 TEST=build, boot into SSD, and run reboot stress test. Change-Id: I5e7943a6cc88bc02bcbd97a1086b2d8044d7b1c3 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/amd/common/block/gpio_banks: add missing types.h includeFelix Held2021-09-211-0/+1
| | | | | | | | | | | | In this file bool, uint8_t and uint32_t are used, so include types.h directly to have those types defined instead of relying to have those included indirectly via amdblocks/gpio_banks.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6f4626a50219fab818e8bc5087961a731b44e71b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/qualcomm/common/spi: Configure SPI QUP driverRavi Kumar Bokka2021-09-211-0/+13
| | | | | | | | | | | | | This implements the SPI driver for the QUP core. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I7e5d3ad07f68255727958d53e6919944d3038260 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56399 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sc7280: Enable SPI driverRajesh Patil2021-09-211-1/+2
| | | | | | | | | | | BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I34a45422e38ea3a47f29e9856fc5679e8aebbcdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* soc/qualcomm/common/spi: Add support for SPI common driverRavi Kumar Bokka2021-09-214-6/+4
| | | | | | | | | | | | | | This implements qup spi driver for qualcomm chipsets Rename header file names for trogdor to prevent breakage. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I2f2b25b6661fcd518f70383da0c7788c5269c97b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55953 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sc7280: Enable I2C driverRajesh Patil2021-09-211-0/+1
| | | | | | | | | | | BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I58c2b79ea2feeab0ad4c2b7cdaa041984160a7ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/55961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* soc/qualcomm/common/i2c: Add support for I2C common driverRajesh Patil2021-09-214-4/+5
| | | | | | | | | | | | | | | copy existing I2C driver from /soc/qualcomm/sc7180 to common folder. This implements i2c driver for qualcomm chipsets BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I16e6fc2c1c24b9814d1803bffd5cfbb657201cfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* src/mainboard/herobrine: Load GSI FW in ramstageRavi Kumar Bokka2021-09-211-0/+3
| | | | | | | | | | | | | Load GSI FW in ramstage and make it part of RW BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I3d9caa0921fcf9ad67f1071cdf769a99fb6d1a30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* src/mainboard/herobrine: Load respective QUP FW for I2C and SPIRajesh Patil2021-09-211-0/+23
| | | | | | | | | | | | | | | | | Loading QUP FW as per herobrine and piglin configuration for I2C, SPI and UART. As part of the code clean up, update the header files of the QUP drivers with the correct path. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: Ic218c6a91ffc4484830446d707d1f3403e2dc46b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* sc7280: Refactor QUP driverRajesh Patil2021-09-215-0/+185
| | | | | | | | | | | | | Enable common qup driver in sc7280 BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I0e9049557ff63898037210e72333e1739ab62413 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* lib/Makefile.inc: Fail build if SPD file doesn't existReka Norman2021-09-211-4/+8
| | | | | | | | | | | | | | | | Currently, if LIB_SPD_DEPS contains an SPD file which doesn't exist, the file is silently skipped when creating spd.bin. Instead, fail the build. BUG=b:191776301 TEST=Build test on brya. Build fails if a non-existent file is included in LIB_SPD_DEPS. Change-Id: I1bdadb72e087c2ee7a88fbab2f3607bd400fa2e4 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-04 01:21:21 +0000