summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* mb/purism/librem_14: Enable both lanes of left side USB 3.0 portJonathon Hall2022-12-021-0/+1
| | | | | | | | | | | | | | | | Fixes using USB-C devices in either orientation on left-side USB-C port. Test: Plug USB-C device in both orientations on left-side USB-C port, check speed with lsusb -t. Change-Id: I9fbc53bb51a5225e92b0b6bb9ced87a0ab90c9ce Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69702 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: skip external buses for D-states listEran Mitrani2022-12-021-0/+3
| | | | | | | | | | | | | | | | | | | The devices in the list that was introduced in commit c66ea985776 ("soc/intel/alderlake: provide a list of D-states to enter LPM") are all internal. This CL skips the external buses (which caused the addition of packages to non-existant paths such as "_SB.PCI0.RP1.MCHC", and warnings from the kernel) BUG=b:231582182 TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/zydron: Add WiFi SAR tableDavid Wu2022-12-022-0/+7
| | | | | | | | | | | | | Add WiFi SAR table for zydron. BUG=b:260770999 TEST=build FW and checked SAR table can load by WiFi driver. Change-Id: I8d5f966c7af3ac6d9923d4f6c851bfb340f31fab Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/prodrive/atlas: Enable GPP_B14 buzzer supportLean Sheng Tan2022-12-022-0/+12
| | | | | | | | | | | | | | | | | | Per Intel doc 621483, 26.1.1 - NMI_STS_CNT, 8254 timer is required for Speaker Data output (buzzer) at GPP_B14 NF1, as it is using 8254 timer counter 2 output. However when 8254 timer is used, S0ix will not work as 8254 has to be gated instead. For further info on s0ix requirements, refer to Intel doc 610002 (Modern Standby Unified Checklist). This CL also disables s0ix because it is not required by the platform. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ib5e7787a47509ed09818d8515d21a80196fb1ec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67553 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/prodrive/atlas: Add DP++ supportLean Sheng Tan2022-12-021-0/+0
| | | | | | | | | | | | Update VBT configurations for DP++ and DP dongles support. Tested working on customer's side. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I7aa34297a10bf16b9043140bff91fd3a8c4009d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70154 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` functionKapil Porwal2022-12-022-40/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch refactors the `pmc_lockdown_cfg()` to remove the helper functions and uses the `setbits32` function to enforce bit locking as applicable. This patch also locks PMC features like: 1. Debug mode configuration and host read access to PMC XRAM. 2. PMC soft strap message interface. 3. PMC static function. and then calls into the PMC IPC function that informs about PCI enumeration. Port of - 1. commit 2eec87a553ec ("soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function") 2. commit bae4a0b5a1e4 ("soc/intel/alderlake: Implement PMC feature lock") 3. commit c2570dc99800 ("soc/intel/alderlake: Implement PMC soft strap interface lock") 4. commit f021952c4067 ("soc/intel/alderlake: Implement PMC static function lock") 5. commit 457891415380 ("soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done") BUG=none TEST=Boot to OS on google/rex. Register values in OS - # busybox devmem 0xfe0018d4 32 #bit31 0x80000000 # busybox devmem 0xfe001024 32 #bit21,18,17,4 0x00362610 # busybox devmem 0xfe001818 32 #bit27,22 0x2B4F0004 # busybox devmem 0xfe00104c 32 #bit0 0x00000001 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3622748d8fecef69c60bb3fe9bfe68fc126764b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70132 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/i945: Use boolean for gpu_lvds_use_spread_spectrum_clockElyes Haouas2022-12-024-4/+5
| | | | | | | | Change-Id: I5f11bde99dfcde81c9dc62c1102330c0a6c16e04 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/pineview: Remove unused 'gpu_lvds_use_spread_spectrum_clock'Elyes Haouas2022-12-021-1/+0
| | | | | | | | | | 'gpu_lvds_use_spread_spectrum_clock'is only used on i945. Change-Id: I0f63f18d3f57ef8774f22ca9eb8c20dd39c56cdc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70147 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}Elyes Haouas2022-12-0221-32/+32
| | | | | | | | | Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/pineview: Use {true,false} instead of {0,1}Elyes Haouas2022-12-023-5/+5
| | | | | | | | | | "use_crt" and "use_lvds" are boolean, so use "true/false". Change-Id: I5b5b42c27351331ad40fbe92fb87390cb1284aa9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70148 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/system76/adl-p: Disable SATA DevSlpTim Crawford2022-12-021-1/+2
| | | | | | | | | | | | | After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0# in system76/ec@cc3effb6a451 ("board/system76/common: use SLP_S0# pin for modern standby detection"), DevSlp blocks suspend entry. Disable it until it is fixed. Change-Id: I586245ebf9f9d5ad08f6745a450411f194a661da Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
* mb/system76/adl-p: Add Galago Pro 6 as a variantTim Crawford2022-12-029-1/+484
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Galago Pro 6 (galp6) is an Alder Lake-P board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - M.2 NVMe SSD (with MZVL2500HCJQ) - All USB ports - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Windows 10 and Linux 6.1 - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.0.6 - Internal flashing with flashrom v1.2-1087-gde016a17 Not working: - Detection of devices in TBT slot on boot Change-Id: I8940fb3777d7f18393ef50baec32f9445b375648 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
* mb/system76/cml-u: Convert lemp9 to a variantTim Crawford2022-12-0231-552/+483
| | | | | | | | Change-Id: I13777cf6f663ca8c52a059a60cfcdfe6ecc5b9ae Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
* mb/google/herobrine: Update FMD file for multiple ROM sizesMartin Roth2022-12-021-0/+5
| | | | | | | | | | | | | | | The Piglin & Hoglin boards were built with a couple of different sizes of ROM chips. Despite this, the desire was to use just a single FMD file. The different sizes are already accounted for in Kconfig, so add the Kconfig size here to be used. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ia75725b0c4d61e832c94160fa4cd455e89c60274 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel/meteorlake: Allow sending late EOP cmd to CSESubrata Banik2022-12-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch selects SOC_INTEL_CSE_SEND_EOP_LATE config to let IA common code to skip sending CSE EOP cmd during finalize operation rather uses boot state machine (either payload load or payload boot) to delay in sending EOP cmd to CSE. BUG=b:260041679 TEST=Able to boot to Google/Rex with this patch and observed ~150ms savings in boot time Without this patch: 942:before sending EOP to ME 1,795,702 (354) 943:after sending EOP to ME 1,950,526 (154,824) With this patch: 942:before sending EOP to ME 2,051,406 (35,484) 943:after sending EOP to ME 2,057,583 (6,177) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7d44d5eff890ac78e3075d49cc249f740686dd0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69999 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/cse: Allow to perform essential CSE operations post EOPSubrata Banik2022-12-021-4/+6
| | | | | | | | | | | | | | | | | | | This patch allows to send late EOP cmd to CSE (after CSE .final) using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD) if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config. Rename `set_cse_end_of_post()` to `send_cse_eop_with_late_finalize()` to make the function name more meaningful with its operation. BUG=b:260041679 TEST=Able to boot Google/Rex after sending CSE EOP late. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel/cmn/cse: API to perform essential CSE operations post EOPSubrata Banik2022-12-022-0/+22
| | | | | | | | | | | | | | | | | | | | This patch creates an API that can perform essential CSE operation after sending the late EOP command to the CSE and prior booting to OS. Lists of operation are - Perform global reset lock - Put HECI1 to D0i3 and disable the HECI1 if the user selects - Set D0I3 for all HECI devices. BUG=b:260041679 TEST=Able to boot Google/Rex after sending CSE EOP late. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/cse: Send EOP cmd from .final aka `cse_final()`Subrata Banik2022-12-021-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch refactors common code to allow cse_final() function to send EOP cmd if the SoC user selects `SOC_INTEL_CSE_SET_EOP` kconfig. This patch helps cse_final_ready_to_boot() and cse_final_end_of_firmware() function for being meaningful with its operation and let cse_final() being that outer layer to perform three operations based on the selected kconfig. 1. send cse eop command 2. perform cse_final_ready_to_boot() operations 3. perform cse_final_end_of_firmware() operations Additionally, ensures the platform that choose to send EOP late (like JSL and TGL) is not being impacted due to this code refactoring hence, skip calling into CSE.final if SoC selects `SOC_INTEL_CSE_SEND_EOP_LATE` config. BUG=b:260041679 TEST=Able to send EOP command successfully for Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I412291c9378011509d3825f9b01e81bfced53303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69975 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/cse: Create another config for sending CSE EOP cmd lateSubrata Banik2022-12-023-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Presently, coreboot supports two instances of sending EOP cmd to the Intel CSE. 1. Sending EOP cmd to CSE during `.final` operation from cse pci driver. 2. Starting with Alder Lake, the recommendation was to send EOP to CSE earlier than CSE `.final` operation. Since then it's referred to as `Sending EOP Early`. This method helped to save the CSE EOP response time significantly. During Meteor Lake platform, CSE EOP response time has become non-deterministic and we have figured that sending EOP command later than CSE .final operation is actually helping to optimize the boot time significantly (around ~150ms savings compared to sending from `.final` ops and ~5sec compared to sending CSE early). Hence, this patch intended to create yet another kconfig for sending CSE late (specifically after `.final` operation). The idea for this newer config is to use the boot state machine for sending CSE EOP cmd. The patch train in this series would add the specific changes to allow sending EOP late and perform other essential operations required prior booting to OS as coreboot decided to skip calling into FSP Notify phase. Starting with Jasper Lake, coreboot sends EOP before loading payload hence, this config is applicable for those platforms. The current plan is that Intel Jasper Lake, Tiger Lake and Meteor Lake platform will select this newer config from SoC code. BUG=b:260041679 TEST=Able to send EOP command successfully for Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69976 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/anahera: Adjust I2C5 timing for touchpadWisley Chen2022-12-021-1/+6
| | | | | | | | | | | | | | | | | | | | | | Adjust scl_lcnt, scl_hcnt, sda_hold value for I2C5 to meet touchpad SPEC. BUG=b:260540852 BRANCH=firmware-brya-14505.B TEST=build, checked TP function work normally, and measure the timing meet SPEC tLOW ~1.72 us tHIGH ~0.63 us tHD ~0.69 us fscl 383 kHz Change-Id: I9036a604a90558911c4f8a492db9f1f0f28bf404 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/nissa/var/xivu: Fine-tune eMMC DLLLawrence Chang2022-12-021-0/+45
| | | | | | | | | | | | | | | Fine-tune eMMC DLL based on Xivu EVT system. BUG=b:256538132 TEST=executed 3000 cycles of cold boot successfully Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69892 Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim/var/frostflow: Enable DPTC supportJohn Su2022-12-021-0/+1
| | | | | | | | | | | | | | | Enable DPTC support for frostflow. BUG=b:257187831 TEST=emerge-skyrim coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Iac7b8789a5189827fe98cb06328d666300841a5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69931 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vboot: Allow for comparison of hash without zero-paddingJakub Czapiga2022-12-012-3/+3
| | | | | | | | | | | | | Adjust asserts to allow to store and compare (at S3 resume) hashes without padding to maximum hash length / slot size. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vboot/vboot_common: Fix vboot_save_data() code exclusion guardJakub Czapiga2022-12-011-10/+17
| | | | | | | | | | | | | | | Compilers are not optimizing-out code correctly. This patch fixes incorrect behavior by splitting if statement and extracting code to another function, this allowing for better code size optimization and reduction of undefined references. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69761 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brya/var/gaelin: Configure audio in devicetreeRaymond Chung2022-12-011-0/+30
| | | | | | | | | | | | | | | Refer to brask board to add audio settings for gaelin. BUG=b:253177160 BRANCH=firmware-brya-14505.B TEST=Able to verify audio playback on gaelin with kernel v5.10. Change-Id: Ibc8cacce6cb4b3e55fc7332bb9eb9ac20848fc5b Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/gaelin: Add camera module settingsRaymond Chung2022-12-012-2/+11
| | | | | | | | | | | | | | | Modify USB2.0 port[4] settings to support camera. BUG=b:238252678 BRANCH=firmware-brya-14505.B TEST=with brask overlay changes, camera in camera app works Change-Id: I42325b75e129429ee451ded6a2086fd3808e581a Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/alderlake: Drop duplicate macro `PCH_PWRM_BASE_SIZE`Subrata Banik2022-12-011-1/+0
| | | | | | | | | | | | | | | | | | | This patch ensures dropping of the duplicate macro introduced with 'commit 9e4488ab06fd9c4 ("soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS")' `PCH_PWRM_BASE_SIZE` macro represents the size of the PMC MMIO range which can be used as is even in ufs.asl file. BUG=b:252975357 TEST=Build and boot nirwen and see no issues in PLT runs. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic967c609e1330eca1b9e1143e7efd78db011f317 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70180 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* ec/google/chromec: Add DPTC support for host event 1/2/9EricKY Cheng2022-12-011-0/+16
| | | | | | | | | | | | | | | DTTS is Dynamic Thermal Table Switching Proposal. Add DPTC support for host event lid-open/lid-close/Thermal Threshold. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67793 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/siemens/mc_ehl2: Disable GSPI2 controllerMario Scheithauer2022-12-011-2/+0
| | | | | | | | | | | | | GSPI2 interface is not used on this mainboard and can be disabled. It will in addition remove the warning of a leftover static device in the log. Change-Id: I6e7462312953d50385ca7bb2f2e0abb8fc3a5886 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/amd/chausie: change AMD_FWM_POSITION_INDEX for non-chromeos caseFelix Held2022-12-011-0/+1
| | | | | | | | | | | | | | | | | | | Commit 2c102232e8f7 ("mb/amd/chausie,google/skyrim: increase RW_MRC_CACHE size to 120 kByte") increased the MRC cache size, but with the change the default AMD_FWM_POSITION_INDEX which is 5 for the 16MByte flash size, the amdfw part won't be placed on the expected position, since the cbfs header is in that exact location and cbfstool places the amdfw part right after that. Change the AMD_FWM_POSITION_INDEX to 4 for the non-chromeos builds to work around this. TEST=Non-chromeos chausie build now boots and doesn't fail any more before releasing the x86 cores from reset Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I89fe1d0672139e04070f05c6c8fa8955edcfc7ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/70133 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/pujjo: Add new audio sku configureLeo Chou2022-12-011-0/+3
| | | | | | | | | | | | | | | | Add new audio sku configure for Pujjo board. BUG=b:260538412 TEST=Boot to OS on pujjo and check that audio are configured based on fw_config. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ia9ddc683945002a0b19efd67006e1983b2eb9f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans2022-12-0119-48/+74
| | | | | | | | Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans2022-12-0111-12/+22
| | | | | | | | Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans2022-12-014-13/+8
| | | | | | | | | Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69293 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/model_206ax: Remove fake lapic deviceArthur Heymans2022-12-0112-92/+42
| | | | | | | | | | | | | | Instead of using a fake lapic device hook up the cpu cluster to chip cpu/intel/model_206ax. The lapic device is also not needed as the mp init will allocate it for the BSP at runtime. Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* cpu/intel/sandybridge: Use enum for ACPI C statesArthur Heymans2022-12-017-16/+27
| | | | | | | | | | Also remove the now unnecessary comments from the devicetree. Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* soc/intel/meteorlake: Log CSE RO write protection info for MTLKapil Porwal2022-12-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | The patch logs CSE RO's write protection information for Meteor Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. Port of commit abe0d810f009 ("soc/intel/alderlake: Log CSE RO write protection info for ADL"). BUG=none TEST=Verify the write protection details on google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* mb/google/herobrine: Mask out upper bits from sku_id()Shelley Chen2022-11-301-1/+6
| | | | | | | | | | | | | | | | | | When retrieving the SKU id value through the sku_id() function in mainboard_needs_pcie_init(), we only want the values in the lower 5 bits as we can only represent SKU id up to 27. Everything in the higher bits should be masked out because they are not needed. BUG=b:254281839 BRANCH=None TEST=Make sure that NVMe is not initialized Tested on a herobrine board with SKU id 0 Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70164 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/herobrine: Only retrieve sku_id from EC onceShelley Chen2022-11-301-14/+12
| | | | | | | | | | | | | | | | | | | | | Currently, we are getting the sku id from the EC every time we call the sku_id() function. However, this will never change so we only need to retrieve it once. Inserting exit condition if sku id is already set, then don't get it from the EC again. Also, removing the ram_code function, which does nothing right now. There is already a weak stub_function for this in src/lib/coreboot_table.c that already does the same thing. BUG=b:260740438,b:182963902 BRANCH=None TEST=make sure image still boots to login on herobrine device Change-Id: Ia787968100baf58a41ccce0cf95ed3ec9ce1758a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Doug Anderson <dianders@chromium.org>
* mb/amd/birman/gpio: Configure birman GPIOsFred Reitberger2022-11-302-5/+234
| | | | | | | | | | Configure birman GPIOs per schematic 105-D67000-00B v0.7 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I5459efb38431e568e25405c440b5b9cf1354f02f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parametersEricKY Cheng2022-11-302-6/+144
| | | | | | | | | | | | | | | Expand DPTC_INPUT macro to supoort 13 DPTC thermal table parameters for dynamic table switching support. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/system76: Rename gaze16 to tgl-hTim Crawford2022-11-3031-3/+5
| | | | | | | | Change-Id: Icbf9348447b9e7acc0caa8082cf5dd00853da37a Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
* arch/x86: Buildtest clang targets with VBOOT_STARTS_BEFORE_BOOTBLOCKArthur Heymans2022-11-301-1/+1
| | | | | | | | | | TESTED: google/vilboz boots with clang build. Change-Id: Ie115c27b4cb0b8f83d7647bdd27ffcbac9376399 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69746 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/arm/armv7: Disable generating neon FPU codeArthur Heymans2022-11-301-0/+1
| | | | | | | | | | | By default clang generates code with neon instructions. These are not supported on all arm targets so default to fpu=none. Change-Id: I48fc505107d131466be39f466151df62b2d2bd0b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69745 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyXArthur Heymans2022-11-301-0/+23
| | | | | | | | | | Clang generated code uses this for zero initialized variables. Change-Id: I460a0096918141c1cf8826bdf1853a3aa3aecff8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* arm/armv7/Makefile.inc: Fix processing ld files with clangArthur Heymans2022-11-301-0/+6
| | | | | | | | | | | When processing linker scripts clang needs to be set for the proper target or it gets confused by other options. Change-Id: I040aa14a06c728269ca1026e0002392e5ac8fef8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69744 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Add packed attribute to structs in unionArthur Heymans2022-11-301-2/+2
| | | | | | | | | | | | | | | | Clang warns about structs inside a union also needing the packed attribute. This files is copied from the chromeec project, so it adds comment next to the coreboot specific changes as a reference. TEST: google/vilboz remains the same with BUILD_TIMELESS=1 and gcc. Change-Id: I8b5233618081db86caedcb2d14870974e109ed9b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/google/brya: Enable Fast VMode for brya0, skolas and skolas4esJeremy Compostella2022-11-303-0/+12
| | | | | | | | | | | | | | | | | | | | | Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. FSP silicon discards the request if the Voltage Regulator or SoC does not support the feature. BUG:b:259057787 TEST:Verify that the feature is enabled by reading from pcode No PnP regression observed BRANCH=firmware-brya-14505.B Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I7e318534f1429af8ec06048430966344ddd346a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69579 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Jeremy Compostella <jeremy.compostella@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetreeArthur Heymans2022-11-302-13/+4
| | | | | | | | | Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69291 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/sandybridge: Add a chipset devicetreeArthur Heymans2022-11-3043-367/+25
| | | | | | | | | | | This only moves CPU configuration to a common place. Other PCI devices can be done in follow-ups. Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-30 23:43:25 +0000