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* soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-144-12/+4
| | | | | | | | | | | | | | | | List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-1411-34/+6
| | | | | | | | | | | | | | | | List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/brya/var/agah: update overridetreeTony Huang2022-01-142-1/+288
| | | | | | | | | | | | | Init basic override devicetree based on initial schematics BUG=b:210970640 TEST=emerge-brya coreboot Change-Id: I7b7badacce27dd7da4f138c6f2465af518715e7f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60837 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: factor out eSPI SPI2 pads configuration functionsFelix Held2022-01-144-21/+41
| | | | | | | | | | | | | | verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses some of the registers directly. BUG=b:183149183 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner2022-01-1414-0/+28
| | | | | | | | | | | | | Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/tgl: deduplicate the PCIe root port mapMichael Niewöhner2022-01-141-17/+2
| | | | | | | | | | | | Make use of the helper introduced in the parent change to deduplicate the PCIe root port table. Change-Id: I2dae4e4caf0a7ba3662889f3b31da0c3c299bc92 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/tgl/pcie_rp: add TGL-H supportMichael Niewöhner2022-01-142-1/+21
| | | | | | | | | | | Add TGL-H support for the recently introduced code for differentiating CPU and PCH root ports by adding the missing TGL-H port map. Change-Id: Id2911cddeb97d6c164662e2bef4fdeece10332a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* src/{drivers,lib}: Remove unused <console/console.h>Elyes HAOUAS2022-01-142-2/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ifad13ef418db204cf132fe00f75c6e66cd2bc51b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/brya: Adjust CSE RO and Data partition in the CSE regionSridhar Siricilla2022-01-131-2/+2
| | | | | | | | | | | | | | | | | | The patch adjusts CSE region's internal partitions' (CSE RO and Data partition) sizes to match with sizes of MFIT generated CSE Region's internal partitions. BUG=b:213993778 TEST=Generate coreboot for Brya and verify with MFIT generated coreboot. Cq-Depend: chrome-internal:4452789 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I5418c02f83134814e3f9959ee8c8da32ce8c7bec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60951 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Variants with ESx SoC use NEM for CARSubrata Banik2022-01-131-2/+2
| | | | | | | | | | | | | | | | | This patch ensures all brya variants with Alder Lake ESx SoC are using NEM by default for CAR set up. Default CAR configuration for QS SoC is eNEM. BUG=b:168820083 TEST=Able to build and boot brya0 variant using eNEM mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib04bec188bdfde67c408fcd6b0603a5c2fb0fc97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* soc/amd/*/chip.h: add missing gpio.h includeFelix Held2022-01-133-0/+3
| | | | | | | | | | | | | | Since we need the GPIO defines in the devicetree settings, include gpio.h in each SoC's chip.h file which will indirectly include the soc-specific soc/gpio.h header instead of having it indirectly included via soc/i2c.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id26721a6b8ae94784d4a90d7ccac28fef2be36dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04Nick Vaccaro2022-01-134-104/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2511_04 Previous FSP version was v2471_02 Changes include: - UPDs description update in FspsUpd.h and FspmUpd.h - Adjust UPD Offset in FspmUpd.h - Name change of UPDs in FspmUpd.h and FspsUpd.h - Copyright year is updated in FspmUpd.h and FspsUpd.h - Updated spd_upds and dq_upds structure variables in meminit.c - Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask in fsp_params.c BUG=b:213959910 BRANCH=None TEST=Build and boot brya Cq-Depend: chrome-internal:4448696, chrome-internal:4445910 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> Change-Id: I39646c6812afbf622171361b8206daeacdaafac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/felwinter: Update ELAN touch HIDEric Lai2022-01-131-1/+1
| | | | | | | | | | | | | Per customer spec, change ELAN touch HID from ELAN9050 to ELAN9008. BUG=b:214010928 TEST=touch screen is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia95fdb378aaf241e38c0beb8ec392d57d77dc4db Reviewed-on: https://review.coreboot.org/c/coreboot/+/61027 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Fix include guard naming for emi.hYu-Ping Wu2022-01-131-3/+3
| | | | | | | | | | | | | | | | | Fix the name of the include guard for soc/mediatek/common/include/soc/emi.h. BUG=none TEST=emerge-corsola coreboot BRANCH=none Change-Id: Iddac3467959545b7db141545aaa2a135536f44f1 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Xi Chen <xixi.chen@mediatek.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
* console/cbmem_console: Rename cbmem_dump_consoleRaul E Rangel2022-01-133-3/+3
| | | | | | | | | | | | | | This function actually dumps cbmem to the UART. This change renames the function to make that clear. BUG=b:213828947 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icc314c530125e5303a06b92aab48c1e1122fd18c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brya/var/taeko: Modify power sequence for SSD deviceKevin Chang2022-01-122-10/+32
| | | | | | | | | | | | | | | | In order to avoid having the FSP fail to detect the SSD device downstream of the RP, its PERST# must be deasserted earlier in the boot flow, therefore move PERST# deassertion to a romstage GPIO table. BUG=b:213828931 TEST=Build FW and run stress exceed 1000 cycles. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I4e5eed7db16e1420ccbc22a5c30b00bedd190a2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common/gpio: Fix cosmetic issue with `gpio_lock_pads`Subrata Banik2022-01-121-3/+4
| | | | | | | | | | | | | | | | This patch replaces hardcoded `4` (next offset Tx state) with `sizeof(uint32_t)` for calculating 'Tx state offset'. Also, add checks to detect the specific GPIO lock action between `LOCK_CONFIG` or 'LOCK_TX'. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iff712b16808e0bc99c575bb2426a4f84b89fdb73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* sc7180: Update video mode active horizontal/vertical/total calculationsVinod Polimera2022-01-121-13/+6
| | | | | | | | | | | Remove vbp & hbp as the names are misleading and use edid variables to simplify the video mode active and total calculations. Change-Id: I9ccafabe226fa53c6f82e32413d4c00a0b4531be Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/glados/variants/sentry: Increase CPU critical temp threshold to 105CSumeet Pawnikar2022-01-121-1/+1
| | | | | | | | | | | | | | | | | | | | | During certain kind of test scenario, observed that CPU temperature spikes till 98C and based on current thermal critical policy temperature threshold of CPU set to 98C, it initiates the system wide abrupt shutdown. To avoid this kind of abrupt system shutdown, update cpu critical temperature threshold from 98C to 105C. BUG=b:213476881 BRANCH=glados TEST=Built and booted on glados Change-Id: I56df9285b3c247866a5bfa6dc59d1856544de41c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* device/pci_device.c: Make sure the PCI bus has a deviceArthur Heymans2022-01-121-0/+3
| | | | | | | | | | | | | | Some SOC add PCI root busses structs at runtime without adding a device struct to the bus because pci_scan_bus does it. An example would be xeon_sp which has multiple root busses. TEST: ocp/deltalake boots again. Change-Id: I81d9c94652e34dbf9e8cec64fc34ef0042563037 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* mb/prodrive/atlas: Add new mainboard based on adlrvpLean Sheng Tan2022-01-1212-0/+254
| | | | | | | | | | | | | | | | | | This is a initial mainboard code cloned from adlrvp aimed to serve as base for further mainboard check-ins. This commit copies the mainboard directory and adjusts the naming to match the new board's name. Besides, This commit also trims down major parts of adlrvp code except some of ADL-P DDR5 RVP as Atlas is using it as main reference. Follow-up commits will introduce the needed changes for the new mainboard. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia3129f68c73969604edcd290c3e50ad219cf88d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60899 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/beadrix: Configure GPIO settingsTeddy Shih2022-01-122-0/+69
| | | | | | | | | | | | | | Override GPIO pad configurations based on the beadrix's schematic. BUG=b:204882915 BRANCH=None TEST=Built test coreboot image Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I53fc8088ff8ebb2790ac8cd68186cf9de908b414 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/beadrix: Correct memory settingsTeddy Shih2022-01-122-0/+51
| | | | | | | | | | | | | | Based on the beadrix's schematic, generate memory settings. BUG=b:204882915, b:210123929 BRANCH=None TEST=Built test coreboot image Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I935581fbf21be4820b03a608ea5bd60b1c000baa Reviewed-on: https://review.coreboot.org/c/coreboot/+/60244 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/drivers: Remove unused <delay.h>Elyes HAOUAS2022-01-122-2/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<" Change-Id: Ifda7b3a798c8b1736e125b2527f95e697951d7bd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src: Remove redundant <rules.h> and <commonlib/bsd/compiler.h>Elyes HAOUAS2022-01-124-4/+0
| | | | | | | | | | | <rules.h> and <commonlib/bsd/compiler.h> are always automatically included in all compilation units by the build system Change-Id: I9528c47f4b7cd22c5a56d6a59b3bfe53197cc4d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/tigerlake: Implement function to map physical port to EC portjzhao802022-01-122-0/+33
| | | | | | | | | | | | | | | | | | Currently coreboot and EC had different logic to interpret TCSS port number which would break retimer update functionality since coreboot would pass wrong port information to EC. This change clones the implementation on Alder Lake which converts the phyiscal port mapping to EC's abstract port mapping. BUG=b:207057940 BRANCH=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: If4451598dbb83528ae6d88dbc1b65c206f24fe1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/tgl/pcie_rp: correct root port mapMichael Niewöhner2022-01-121-2/+1
| | | | | | | | | | | | TGL-LP only has 12 root ports, not 20. Correct the port map. Change-Id: I3f5c69a2e7e3a2b8292c81beeac4ea6c7279d4b4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/brya: Move gpio_pm settings for brya variants to baseboardsTim Wawrzynczak2022-01-1215-134/+20
| | | | | | | | | | | | | | | The factory versions (minor version 22) of cr50 FW have an issue with producing short interrupt pulses, which can be missed by the ADL PCH if autonomous GPIO power management is enabled, therefore instead of continually adding the setting to all the variants, move it to the baseboard instead. Change-Id: I337f1e9e8f958c02bb73e6701a06c0b88a4757d7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/guybrush/var/dewatt: Update unused GPIO pinsKenneth Chan2022-01-123-1/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to H/W schematics, fingerprint, SD controller, WWAN/LTE and PEN modules are not stuffed and hence the following GPIOs are marked as not connected: GPIO_3 : TP247 GPIO_4 : TP218 GPIO_5 : TP220 GPIO_8 : TP245 GPIO_11: TP244 GPIO_17: TP194 GPIO_18: TP195 GPIO_21: TP243 GPIO_24: TP196 GPIO_31: TP50 GPIO_42: TP219 GPIO_69: TP217 GPIO_115: TP235 GPIO_116: TP205 GPIO_140: TP226 GPIO_142: TP225 GPIO_144: TP227 BUG=b:204155627 TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I552fd6af1cd827e4e41be1a954bf95c3afbb6a86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/guybrush/var/dewatt: Support ALC5682I-VS codecKenneth Chan2022-01-121-1/+1
| | | | | | | | | | | | | | | ALC5682I-VS codec will be used in EVT, replacing ALC5682I-VD. BUG=b:211835769 TEST=emerge-guybrush coreboot chromeos-bootimage; HW reworked a proto MB with ALC5682I-VS, build and check "i2cdetect -r -y 2", dmesg. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ib1a82285b60c6d5d474ead8643a826e36f56f5b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/common/block: add new PCI IDs to common codeFelix Held2022-01-123-0/+4
| | | | | | | | | | | | The existing common AMD SoC code supports some of AMD Family 17h Model A0h SoC's PCI devices that however have different PCI IDs. Add the new PCI ID defines to the PCI ID lists of the common PCI drivers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I50960e502c63a2ffcfed35178c5e7c9729ef061e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* include/device/pci_ids.h: add PCI IDs for AMD Family 17h Model A0h SoCFelix Held2022-01-121-0/+16
| | | | | | | | | | | | The PCI IDs of the ACP (audio co-processor), the non-GPU HDA audio, the SMBus and the LPC devices haven't changed from the previous generations of Zen-based APUs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I41e0a57671b9ef2938b7798d5826de43bea8fe12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* chromeos: Add an elog for Chrome OS diagnostic bootHsuan Ting Chen2022-01-111-1/+8
| | | | | | | | | | | | | | | | | Add an elog type 0xb6 for Chrome OS diagnostics related events and log the message while booting the diagnostic tool: __func__: Logged diagnostic boot BRANCH=none BUG=b:185551931, b:177196147 TEST=emerge-volteer coreboot vboot_reference Change-Id: Icb675fc431d4c45e4f432b2d12cac6dcfb2d5e3a Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/amd/cezanne/include/i2c: add missing types.h includeFelix Held2022-01-111-0/+1
| | | | | | | | | | | | uintptr_t is defined in stdint.h which gets included by types.h. I use types.h instead of stdint.h, since that's also what the Picasso code does. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3d0811d831b5acc9343398f4d28c73467c0a429 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/cezanne/include/i2c: move include inside header guardFelix Held2022-01-111-2/+2
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a8c21c462258c8a419ccc3f2db50f74a154e465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* mb/google/brya/var/volmar: Generate SPD ID for supported partsDavid Wu2022-01-113-13/+22
| | | | | | | | | | | | | | | | | | | | | | Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B (Micron) MT53E1G32D2NP-046 WT:B (Micron) H54G46CYRBX267 (Hynix) H54G56CYRBX247 (Hynix) K4U6E3S4AB-MGCL (Samsung) K4UBE3D4AB-MGCL (Samsung) BUG=none TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic5b45ec83d0d7e0e1d16cb1afae501f06ee1f36a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/apl: Use Kconfig to disable HECI1Subrata Banik2022-01-112-1/+5
| | | | | | | | | | | This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Apollo Lake and ensures disable_heci1() is guarded against this config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7ac0cad97fcd42b2c6386693319d863352356864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/alderlake: Factor out A0 stepping workaroundAngel Pons2022-01-119-173/+106
| | | | | | | | | | | | | | Move the `configure_pmc_descriptor()` function to SoC scope instead of having two identical copies in mainboard scope. Add a Kconfig option to allow mainboards to decide whether to implement this workaround. Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Check if descriptor is writableAngel Pons2022-01-111-0/+30
| | | | | | | | | | | | | Copy the `is_descriptor_writeable()` function from the `intel/adlrvp` mainboard and use it in the `configure_pmc_descriptor()` function. With this change, this function is now identical for both mainboards. Change-Id: I2ff39682ed98c6b8bc60cc2218f36f4934b9903c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
* mb/google/brya/bootblock.c: Sync cosmetics with adlrvpAngel Pons2022-01-111-16/+14
| | | | | | | | | | | | | | | Adjust the cosmetics of the `configure_pmc_descriptor()` function to match the code for the `intel/adlrvp` mainboard. The only difference is that adlrvp checks if the descriptor is writable. Tested with BUILD_TIMELESS=1, Google Brya0 remains identical. Change-Id: I9c524d5c422c765db200a15f484c2b8827ebd40b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
* mb/google/brya: Restructure PMC descriptor updateAngel Pons2022-01-111-3/+6
| | | | | | | | | | | | | | Restructure the code in the `configure_pmc_descriptor()` so that it matches the code for the `intel/adlrvp` mainboard. This change does not reindent the contents of the original if-block intentionally as this will be taken care of in a reproducible follow-up. Change-Id: I8c9d9087cb2d0668f6a4afbb566d830bb9febd89 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
* mb/google/brya/(brya0,taeko): Use eNEM for CAR by defaultSubrata Banik2022-01-111-1/+1
| | | | | | | | | | | | | | | | More Brya variants like Brya0 and Taeko have migrated to use Alder Lake QS SoC which enables eNEM feature by default. Hence, select eNEM for CAR by default for these variants. BUG=b:168820083 TEST=Able to build and boot brya0 variant using eNEM mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I63be166c8e428f052999fe29c8ebe1238e1a12ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* soc/intel/apl: Rework on CPU privilege level implementationSubrata Banik2022-01-116-23/+16
| | | | | | | | | | | | | | | | | | This patch migrates common code API into SoC specific implementation to drop CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK, it's MSR 0x120 and CNL onwards it's MSR 0x151. Also, include `soc/msr.h` in cpu.h to fix the compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0b6f39509cc5457089cc15f28956833c36b567ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/60898 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/mainboard/emulation/qemu-i440fx: Fix struct packingPatrick Rudolph2022-01-101-5/+5
| | | | | | | | | | | | | On x86_64 the struct isn't packed, causing the fw_cfg parser to return invalid memory entries (possible others as well) through fw_cfg. Fix that by packing all structs. Change-Id: Id1bab99f06be99674efe219dda443fb7d44be560 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src/mainboard/google: Remove unused <acpi/acpi.h>Elyes HAOUAS2022-01-1037-37/+0
| | | | | | | | Change-Id: I67fc65c5e01bb134e2e3068dc6da03de1183f785 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* src/drivers/i2c/gpiomux: Remove unused <stdlib.h>Elyes HAOUAS2022-01-102-2/+2
| | | | | | | | | | | Found using: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l 'memalign(\|malloc(\|calloc(\|free(' -- src/) Change-Id: Id3bd3d8a2d3609a13ecbc4eab14ba745e6365cab Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src/lib: Remove unused <timer.h>Elyes HAOUAS2022-01-101-1/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <timer.h>' -- src/) <(git grep -l 'NSECS_PER_SEC\|USECS_PER_SEC\|MSECS_PER_SEC\|USECS_PER_MSEC\|mono_time\|microseconds\|timeout_callback\|expiration\|timer_monotonic_get\|timers_run\|timer_sched_callback\|mono_time_set_usecs\|mono_time_set_msecs\|mono_time_add_usecs\|mono_time_add_msecs\|mono_time_cmp\|mono_time_after\|mono_time_before\|mono_time_diff_microseconds\|stopwatch\|stopwatch_init\|stopwatch_init_usecs_expire\|stopwatch_init_msecs_expire\|stopwatch_tick\|stopwatch_expired\|stopwatch_wait_until_expired\|stopwatch_duration_usecs\|stopwatch_duration_msecs\|wait_us\|wait_ms' -- src/) Change-Id: I9cc14b4b90989bd9ab1018e5863eece120f861c0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src/soc/qualcomm: Remove unused <delay.h>Elyes HAOUAS2022-01-105-5/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<" Change-Id: Id1e0f4cb9f6181dc2fc45e7b6cb149646111bb3e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src/soc: Remove unused <stdlib.h>Elyes HAOUAS2022-01-104-4/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l 'memalign(\|malloc(\|calloc(\|free(' -- src/) Change-Id: I08e1a680de9bfcc7d74e88a15abe9eef327b4961 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* src/lib: Remove unused <delay.h>Elyes HAOUAS2022-01-101-1/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<" Change-Id: I6fb603a17534e3a1593cb421c618f8119933292a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-20 06:54:29 +0000