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* treewide: Move list.h to commonlibMaximilian Brune2024-02-242-153/+0
| | | | | | | | | | | It is needed in order to move device_tree.c into commonlib in a subsequent commit. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I16eb7b743fb1d36301f0eda563a62364e7a9cfec Reviewed-on: https://review.coreboot.org/c/coreboot/+/77968 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests/lib/ux_locales-test: Simplify macrosYu-Ping Wu2024-02-221-41/+15
| | | | | | | | | | | | | | | The cmocka problem of sanitizing XML strings has been fixed in CB:80382. Therefore the helper macros UX_LOCALES_GET_TEXT_FOUND_TEST() and UX_LOCALES_GET_TEXT_NOT_FOUND_TEST() can be merged into one. TEST=make unit-tests JUNIT_OUTPUT=y -j Change-Id: Ic3199e2a061550282fb08122943994c835845543 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
* lib: Move IP checksum to commonlibJulius Werner2024-02-022-104/+1
| | | | | | | | | | | | | | | | | | | | | | This patch moves the IP checksum algorithm into commonlib to prepare for it being shared with libpayload. The current implementation is ancient and pretty hard to read (and does some unnecessary questionable things like the type-punning stuff which leads to suboptimal code generation), so this reimplements it from scratch (that also helps with the licensing). This algorithm is prepared to take in a pre-calculated "wide" checksum in a machine-register-sized data type which is then narrowed down to 16 bits (see RFC 1071 for why that's valid). This isn't used yet (and the code will get optimized out), but will be used later in this patch series for architecture-specific optimization. Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80251 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
* malloc/memalign: Return NULL if the request is too largePatrick Georgi2024-01-291-10/+4
| | | | | | | | | | | | | | | | | | | | | It's what this function family is defined to do, we currently don't usually run into the case (see: not too many die() instances going around), it's more useful to try to recover, and the JPEG parser can run into it if the work buffer size exceeds the remaining heap, whereas its sole user (the bootsplash code) knows what to do when seeing a NULL. Use xmalloc() if you want an allocation that either works or dies. tl;dr: That code path isn't usually taken. Right now it crashes. With this patch it _might_ survive. There is a use-case for doing it like that now. Change-Id: I262fbad7daae0ca3aab583fda00665a2592deaa8 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
* tests: Rename Makefiles from .inc to .mkMartin Roth2024-01-261-0/+0
| | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id09eafd293a54198aab87281f529749325df8b07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* tests/lib: Enforce ux_locales-test with CONFIG_VBOOTSubrata Banik2023-11-161-0/+1
| | | | | | | | | | | | | | The ux_locales-test relies on the ability to determine supported locales for the platform. However, this information is unavailable without VBOOT config being enabled. Therefore, enforce this test for platforms with VBOOT config alone to avoid unnecessary failures. Change-Id: I2828eb062e2b601e073e7dab9aef7316fc6ba2cd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hsuan-ting Chen <roccochen@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* Allow to build romstage sources inside the bootblockArthur Heymans2023-11-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* tests/lib: Add unit tests for ux_locales_get_text()Hsuan Ting Chen2023-08-302-0/+270
| | | | | | | | | | | | | | | | Add unit tests for ux_locales_get_text() in lib/ux_locales.c. BUG=b:264666392, b:289995591 BRANCH=brya TEST=make tests/lib/ux_locales-test TEST=Make sure ux_locales.c has 100% test coverage Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I4d73419c02478870942828d324c258ef0eaa983c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* tree: Drop repeated wordsAlexander Goncharov2023-02-071-1/+1
| | | | | | | | | | | | | Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spd.h: Move enum ddr3_module_type to ddr3.hElyes Haouas2023-01-041-4/+7
| | | | | | | | | | Move specific enum ddr3_module_type to <device/dram/ddr3.h>. Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spd.h: Move enum ddr2_module_type to ddr2.hElyes Haouas2023-01-041-4/+7
| | | | | | | | | | | Move specific enum ddr2_module_type to <device/dram/ddr2.h>. Change-Id: I748658f9b349bff9b1ebe2c0a6acf71bf2a221ce Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71546 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* coreboot_tables: Make existing alignment conventions more explicitJulius Werner2022-12-221-6/+7
| | | | | | | | | | | | | | | | | | There seem to be some recurring vague concerns about the alignment of coreboot table entries. While the existing implementation has been producing tables with a well-defined alignment (4 bytes) for a long time, the code doesn't always make it very clear. This patch adds an explicit constant to codify that alignment, assertions to check it after each entry, and adds explicit padding to the few entry structures that were relying on compiler padding to return a correct sizeof() value. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaeef29ef255047a855066469e03b5481812e5975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70158 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
* cbmem_top_chipset: Change the return value to uintptr_tElyes Haouas2022-11-182-4/+4
| | | | | | | | | | Get rid of a lot of casts. Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* lib/coreboot_table: Simplify API to set up lb_serialArthur Heymans2022-11-041-30/+8
| | | | | | | | | | | | | | | | | Instead of having callbacks into serial console code to set up the coreboot table have the coreboot table code call IP specific code to get serial information. This makes it easier to reuse the information as the return value can be used in a different context (e.g. when filling in a FDT). This also removes boilerplate code to set up lb_console entries by setting entry based on the type in struct lb_uart. Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* test/lib: Add non-existent DIMMs test case in spd_cache-testEric Lai2022-11-031-0/+21
| | | | | | | | | | | | | | | Add non-existent DIMMs test case in spd_cache-test. BUG=b:213964936 TEST=make unit-tests PASSED Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I3c8aa92ee0cfd5908399f4bbd305f8f306571d40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* coreboot_tables: Drop uart PCI addrArthur Heymans2022-10-261-3/+0
| | | | | | | | | | | | | | | Only edk2 used this to fill in a different struct but even there the entries go unused, so removing this struct element from coreboot has no side effects. Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* tests/lib/coreboot_table-test.c: Use ALIGN_UP macroElyes Haouas2022-09-121-2/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie0d4788c0a4ffee2f16bcf05e3454dbaeaa1606b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* allocator_v4: Introduce RESOURCE_ALLOCATION_TOP_DOWNNico Huber2022-09-041-15/+33
| | | | | | | | | | | | | | | | | | Add option to resource allocator v4 that restores the top-down allocation approach at the domain level. This makes it easier to handle 64-bit resources natively. With the top-down approach, resources that can be placed either above or below 4G would be placed above, to save precious space below the 4G boundary. Change-Id: Iaf463d3e6b37d52e46761d8e210034fded58a8a4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* cbfs/vboot: Adapt to new vb2_digest APIJulius Werner2022-09-021-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | CL:3825558 changes all vb2_digest and vb2_hash functions to take a new hwcrypto_allowed argument, to potentially let them try to call the vb2ex_hwcrypto API for hash calculation. This change will open hardware crypto acceleration up to all hash calculations in coreboot (most notably CBFS verification). As part of this change, the vb2_digest_buffer() function has been removed, so replace existing instances in coreboot with the newer vb2_hash_calculate() API. Due to the circular dependency of these changes with vboot, this patch also needs to update the vboot submodule: Updating from commit id 18cb85b5: 2load_kernel.c: Expose load kernel as vb2_api to commit id b827ddb9: tests: Ensure auxfw sync runs after EC sync This brings in 15 new commits. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* tests/memrange-test: Correct final end test in test_memrange_steal()Nico Huber2022-08-261-1/+1
| | | | | | | | | | | | If an inserted region's base wasn't aligned, the resulting range should still cover the original end (original region's base + size) and not the aligned-down base + size. Change-Id: I8f1c9456d6dbab4fa868de5c93fa3656397e54c1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66607 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests/memrange-test: Correct commentary on test_memrange_steal()Nico Huber2022-08-261-4/+4
| | | | | | | | | | | | | | Currently, memranges_steal() steals at the lowest possible address. This is actually reflected by the test code that checks if the *base* of the READONLY_TAG range changes. Furthermore, the test ends with the memranges restored, so revise the comment on the final state. Change-Id: Idef71ce464280c6805145f229de9e8913ba850bc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66606 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jan Dabros <jsd@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests/lib: Do not pick up unassigned resourcesShuo Liu2022-08-131-4/+21
| | | | | | | | | | | | Unassigned tag is defined to emulate an unmapped PCI BAR resource. This resource is not mapped into host physical address and hence should not be picked up by memranges_add_resources(). Change-Id: If7a5c437d486b80d798496b985efd80526f13c63 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Dabros <jsd@semihalf.com>
* tests/lib: Set IORESOURCE_ASSIGNED for bootmem-test and memrange-testShuo Liu2022-08-132-12/+21
| | | | | | | | | | | | | | | | | | | IORESOURCE_ASSIGNED is used to indicate the resource is actually mapped host physical address space. E.g. PCI BAR resources not mapped are not regarded as assigned. In src/include/device/device.h, standard macros, e.g. ram_resource, mmio_resource, io_resource, et al, are all following the usage above. This patch updates the bootmem-test and memrange-test to follow the usage as well. Change-Id: Ifc19302482038267cef01321a46a72d90ca76d35 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66450 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Jan Dabros <jsd@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib: Check for non-existent DIMMs in check_if_dimm_changedEric Lai2022-04-201-5/+10
| | | | | | | | | | | | | | | | | | | | Treat dimm addr_map 0 non-existent. addr_map default is 0, we don't set it if Hw is not present. Also change the test case default to avoid 0. SODIMM SMbus address 0x50 to 0x53 is commonly used. BUG=b:213964936 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The MRC training does not be performed again after rebooting. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac Reviewed-on: https://review.coreboot.org/c/coreboot/+/63628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* tests: update CMocka to stable-1.1Jakub Czapiga2022-04-191-1/+1
| | | | | | | | | | | | CMocka stable-1.1 has some convenience bugfixes like vprint buffer increase or leftover values log fix (funtion names display correctly now. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I20ebd15324a21c17cccd2976ae9c3f86b040426d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_tJianjun Wang2022-04-142-12/+12
| | | | | | | | | | | | | | | Replace 'struct lb_uint64' with 'typedef __aligned(4) uint64_t lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no longer needed. Also replace 'struct cbuint64' with 'cb_uint64_t' and remove 'cb_unpack64' in libpayload for compatible with lb_uint64_t. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* tests/lib: Add space before single line comment terminationPaul Menzel2022-03-272-2/+2
| | | | | | | | Change-Id: I9321391cc06afddff94fbba79f93851b553c74b1 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* coreboot_tables.c: Expose the ACPI RSDPArthur Heymans2022-03-091-0/+12
| | | | | | | | | | | | | | | | | | | | | The ACPI RSDP can only be found in: - legacy BIOS region - via UEFI service On some systems like ARM that legacy BIOS region is not an option, so to avoid needing UEFI it makes sense to expose the RSDP via a coreboot table entry. This also adds the respective unit test. Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62573 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/bsd: Remove cb_err_tJulius Werner2022-03-092-20/+20
| | | | | | | | | | | | | | | | | cb_err_t was meant to be used in place of `enum cb_err` in all situations, but the choice to use a typedef here seems to be controversial. We should not be arbitrarily using two different identifiers for the same thing across the codebase, so since there are no use cases for serializing enum cb_err at the moment (which would be the primary reason to typedef a fixed-width integer instead), remove cb_err_t again for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* timestamps: Rename timestamps to make names more consistentJakub Czapiga2022-03-081-2/+2
| | | | | | | | | | | | | | | | | | This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* tests: Fix tests code and comments styleJakub Czapiga2022-01-1424-1055/+1068
| | | | | | | | | | | | | | This patch applies clang-format settings to most of tests files. Some files were fixed "by-hand" to exclude some lines, which whould be less readable after automatic style fixing. Moreover, some comments (mostly in tests/lib/edid-test.c) were adjusted to match coreboot coding style guidelines. Change-Id: I69f25a7b6d8265800c731754e2fbb2255f482134 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* tests: Move EDID test header to include/tests/libJakub Czapiga2022-01-121-1/+1
| | | | | | | | | | | Move header to path with all other test headers to make include paths unambigous. Change-Id: Ie2dbb055df658272424df95f58d84caaeba3fc8f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* tests/lib/lzma-test: Fix uninitialized array errorJakub Czapiga2021-12-151-1/+1
| | | | | | | | | Change-Id: I5b10eef3dd82068f97d4d875f3da813a5aca07a7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reported-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60112 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib: Add __fls() (Find Last Set)Jianjun Wang2021-12-131-0/+10
| | | | | | | | | | | | Implement __fls() as an alias for log2(), and remove the duplicate definitions in commonlib/storage/sdhci.c. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* lib: Fix log2_ceil() for 0xffffffffYu-Ping Wu2021-12-082-0/+63
| | | | | | | | | | | | | | | | | | Current log2_ceil(x) is defined as log2(x * 2 - 1). When x is larger than (1 << 31), (x * 2 - 1) won't fit in u32, leading to incorrect result. Therefore, correct it as (log2(x - 1) + 1). Also add unit tests for inline functions in lib.h. BUG=none TEST=make tests/lib/lib-test BRANCH=none Change-Id: If868f793b909a6ad7fc48a7affac15e2c714fa2e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* cbfs: Remove deprecated APIsJulius Werner2021-12-062-0/+2
| | | | | | | | | | | | | | This patch removes all remaining pieces of the old CBFS API, now that the last straggling use cases of it have been ported to the new one (meaning cbfs_map()/cbfs_load()/etc... see CB:39304 and CB:38421). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* commonlib: Move commonlib/cbmem_id.h to commonlib/bsd/Jakub Czapiga2021-11-301-1/+1
| | | | | | | | | | | | | Libpayload requires cbmem_id.h file to support extracting values from CBMEM IMD entries of coreboot tables. Libpayload use BSD-3-Clause license, and all of its files used to compile a static library have to use it too. Change-Id: I97c080e34ebdbcdf14fe3a3c9515b1dea8ede179 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
* arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik2021-11-112-16/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* lib/list: Add list_appendRaul E Rangel2021-11-031-0/+20
| | | | | | | | | | | | | This method will add a node to the end of the list. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1792e40f789e3ef16ceca65ce4cae946e08583d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()Subrata Banik2021-11-021-16/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* tests: Add lib/lzma-test test caseJakub Czapiga2021-10-142-0/+196
| | | | | | | | | | | | | | | | | Files used by this test are in: tests/data/lib/lzma-test/ file.bin - files with uncompressed data file.lzma.bin - files with LZMA-compressed data from file.bin How to prepare compressed file: util/cbfs-compression-tool compress file.bin /tmp/file.lzma.bin lzma dd if=/tmp/file.lzma.bin of=file.lzma.bin skip=8 ibs=1 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Id75e0b41991382d4c391b031862106de58eacdf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* tests: Add lib/cbfs-lookup-test test caseJakub Czapiga2021-09-142-0/+1085
| | | | | | | | Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I2ebebba1468c19661741de8a8456605b1c5f56b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* tests: Add lib/cbfs-verification-test test caseJakub Czapiga2021-09-022-0/+228
| | | | | | | | | | | This commit adds test case for lib/cbfs verification mechanisms. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I1d8cbb1c2d0a9db3236de065428b70a9c2a66330 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56601 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests: Improve test output readabilityJakub Czapiga2021-09-0129-39/+32
| | | | | | | | | | | | | | | | | | | | | | When running multiple tests, e.g. by using unit-tests target, it is hard to differentiate, which output comes from which file and/or configuration. This patch makes the output easier to analyze and understand by using new wrapper macro cb_run_group_tests(). This macro uses __TEST_NAME__ value (containing test path and Makefile test name) as a group name when calling cmocka group runner. Example: Test path: tests/lib/ Makefile test name: cbmem_stage_cache-test Test group array name: tests Result: tests/lib/cbmem_stage_cache-test(tests) Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I4fd936d00d77cbe2637b857ba03b4a208428ea0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* tests/Makefile.inc: Add missing include paths to TEST_CFLAGSJakub Czapiga2021-08-131-4/+0
| | | | | | | | | | | Add missing paths to common tests cflags and remove these paths from individual tests configuration. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I13cb336195bfb06b861d7f403822f06bec8a40aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* tests: Add lib/libgcc-test test caseJakub Czapiga2021-07-262-0/+135
| | | | | | | | | | | | Add tests for src/lib/libgcc.c __clzsi2() implementation. Unlike GCC implementation, coreboot one can handle zero input. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I3f46071d0921e8c5edc5df3c296d11c77de01c88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* tests: Rework mocking facilityPatrick Georgi2021-06-103-5/+5
| | | | | | | | | | | | | | | | | | | | Using the linker's --wrap feature has the downside that it only covers references across object files: If foo.c defines a() and b(), with b calling a, --wrap=a does nothing to that call. Instead, use objcopy to mark a weak and global so it can be overridden by another implementation, but only for files originating in src/. That way mocks - implemented in tests/ - become the source of truth. TEST=Had such an issue with get_log_level() in a follow-up commit, and the mock now takes over. Also, all existing unit tests still pass. Change-Id: I99c6d6e44ecfc73366bf464d9c51c7da3f8db388 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* tests: Add lib/cbmem_stage_cache-test test caseJakub Czapiga2021-06-012-0/+204
| | | | | | | | Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie6851b9473b225beb5ba51e26f44e21ea5919a64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* tests/lib/memset-test: Add missing malloc check and free on errorJakub Czapiga2021-05-261-2/+2
| | | | | | | | | | | | Coverity found resource leak in test setup function in error block. Add malloc result check and free in error handling to silence Coverity. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Found-by: Coverity CID 1446760 Change-Id: Icf746df27167047fa3cf8f5df09fced20863f76d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* tests/lib/spd_cache-test: Initialize spd_block.addr_mapJakub Czapiga2021-05-181-5/+5
| | | | | | | | | | | | | | Coverity reported unitialized array spd_block.addr_map which values are not used. Add initialization to silence Coverity and avoid errors in the future. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Found-by: Coverity CID 1453145 1453146 1453147 1453148 1453149 Change-Id: If301f9e5d9e06ad26769bd0717f1f906e620d82d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-27 18:36:46 +0000