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* util/ifdtool.c: Fix long_options for platformVojtech Vesely2024-02-151-1/+1
| | | | | | | | | | | Platform has argument, but has_arg was mistakenly set to 0. Change-Id: I7d5c31c2b1da544cb73d9e213d463332fcdba7df Signed-off-by: Vojtech Vesely <vojtech.vesely@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80432 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
* util/ifdtool: Add a new switch -E to protect GPR0Subrata Banik2024-02-022-22/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the new command-line option `-E` to the ifdtool, which enables users (primarily factory users) to protect GPR0. Additionally, this patch refactors some code while adding support for enabling GPR0 protection. For more information on the scope of GPR0 (General Protection Range 0), please refer to the Intel Meteor Lake-U Type 4 Client Platform SPI Programming Guide, Document Number 768150. BUG=b:270275115 TEST=Able to test GPR0 protection on google/rex and google/yahiko. > ifdtool -p mtl -E image.bin -O image.bin_lock ... Value at GPRD offset (64) is 0x83220004 --------- GPR0 Protected Range -------------- Start address = 0x00004000 End address = 0x00322fff ... GPR0 protection is now enabled Change-Id: I27c533ae4109c79299f4e7ff75e750d7cc64280f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* util/ifdtool: Refactor GPR0 Unlock ImplemetationSubrata Banik2024-01-271-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch refactors GPR0 unlock function to add few important logic as below 1. Perform GPR0 unlock if GPR0 is locked. 2. While unlocking dump the GPRD PCH strap details 3. Additionally, print the GPR start and end range if GPR0 protection is enabled. TEST=Able to test GPR0 protection on google/rex and google/yahiko. Exp 1: Trying to unlock GPR0 protection for a locked image > ifdtool -p mtl -g image.bin -O image.bin_unlock File image.bin is 33554432 bytes Value at GPRD offset (64) is 0x83220004 --------- GPR0 Protected Range -------------- Start address = 0x00004000 End address = 0x00322fff Writing new image to image.bin_unlock Exp 2: Trying to unlock GPR0 protection for a unlocked image > ifdtool -p mtl -g image.bin_unlock -O image.bin_unlock File image.bin_unlock is 33554432 bytes GPR0 protection is already disabled Change-Id: Id35ebdefe83182ad7a3e735bdd2998baa0ec3ed7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80216 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* util: Rename Makefiles from .inc to .mkMartin Roth2024-01-262-1/+1
| | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I434940ebb46853980596f7ad55d27a62c90280fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/80123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/ifdtool: Enable Read Access for SPI device expansion 2 regionSubrata Banik2024-01-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per Intel Meteor Lake SPI programming doc, the BIOS region should have a read access enabled for device expansion 2 region (aka region 9). This patch ensures that BIOS region is able to read the device expansion 2 region for Intel Meteor Lake platform as known as SPI padding region. BUG=b:274356894 BRANCH=firmware-rex-15709.B TEST=Able to flash screebo AP FW image using flashrom on DUT. Without this patch: > flashrom -p internal -r /tmp/bios.rom flashrom 1.4.0-devel on Linux 6.1.67-09255-ge8ae3115f8b0 (x86_64) ... ... Found Winbond flash chip "W25Q256JW_DTR" (32768 kB, Programmer-specific) on internal. Reading flash... Transaction error between offset 0x0072f000 and 0x0072f03f (= 0x0072f000 + 63)! read_flash: failed to read (0x72f000..0x7fffff). Read operation failed! FAILED. FAILED With this patch: > flashrom -p internal -r /tmp/bios.rom flashrom 1.4.0-devel on Linux 6.1.68-09294-g001fdda5287d (x86_64) ... ... Found Winbond flash chip "W25Q256JW_DTR" (32768 kB, Programmer-specific) on internal. Reading flash... done. SUCCESS Change-Id: I18c44aa9a0f890f01a889247da118b69a58936e8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <ericllai@google.com>
* util/ifdtool: Add support for extended region read/write accessReka Norman2024-01-081-10/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Platforms from CNL onwards support up to 16 flash regions, not 12. The permissions for regions [15:12] are stored in extended region read/write access fields in the FLMSTR registers. Currently ifdtool treats these fields as reserved, so they're not modified when locking or unlocking. Add support for extended regions so that they are locked/unlocked by the --lock/--unlock options. This will make the locked/unlocked descriptors generated by ifdtool match those generated by mFIT. BUG=b:270275115 TEST=Without this change: `ifdtool -lr -p adl` on unlocked image: Before: 00000080 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00 00000090 ff ff ff ff After: 00000080 ff 07 20 00 ff 05 40 00 ff 00 00 00 00 00 00 00 00000090 ff 00 00 00 `ifdtool -u -p adl` on locked image: Before: 00000080 00 07 20 00 00 05 40 00 00 00 00 00 00 00 00 00 00000090 00 00 00 00 After: 00000080 00 ff ff ff 00 ff ff ff 00 ff ff ff 00 00 00 00 00000090 00 ff ff ff With this change: `ifdtool -lr -p adl` on unlocked image: Before: 00000080 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00 00000090 ff ff ff ff After: 00000080 00 07 20 00 00 05 40 00 00 00 00 00 00 00 00 00 00000090 00 00 00 00 `ifdtool -u -p adl` on locked image: Before: 00000080 00 07 20 00 00 05 40 00 00 00 00 00 00 00 00 00 00000090 00 00 00 00 After: 00000080 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00 00000090 ff ff ff ff Change-Id: Iaa43524d91c399a996ade56f2f613b4110a44aad Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* util/ifdtool: Add support for disabling GPR0Reka Norman2024-01-051-3/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | On ChromeOS devices with updateable CSE firmware, the GPR0 (Global Protected Range) register is used to ensure the CSE RO is write protected even when the FLMSTR-based protection is temporarily disabled by coreboot to allow updating the CSE RW. For more details see Documentation/soc/intel/cse_fw_update/cse_fw_update.md Therefore to allow modifying the CSE firmware from the CPU, the descriptor must have both the FLMSTR-based protection disabled (which can be done using ifdtool --unlock), and GPR0 disabled. Add an ifdtool option for disabling GPR0. For now I've added support for all platforms for which I have the SPI programming guide. Support for more platforms can be added in the future if needed. BUG=b:270275115 TEST=Run `ifdtool -p adl -g image.bin -O image-unlocked.bin` on a locked craask image, check the GPR0 field is set to 0. Change-Id: Iee13ce0b702b3c7a443501cb4fc282580869d03a Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79788 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool/ifdtool.c: Add NULL check for fmapnameMaximilian Brune2023-11-161-0/+8
| | | | | | | | | | | | | | | | | | Some boards (e.g. prodrive/hermes) that do not provide their own FMAP and therefore have been generated by the build system (+ ifdtool) experience a failure when trying to build with an IFD that contains regions which do not have equivalent fmap names (set to NULL). Therefore add a NULL check for the fmapname and ignore the region if we do not have an fmapname. Test: compile prodrive/hermes Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ib4589b7fdbd11d644214ca5601536e9aeb26882f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* util/ifdtool: Add support for Intel 800 series chipsetSubrata Banik2023-05-272-5/+45
| | | | | | | | | | | | | | | | | | | | | | This commit adds support for Intel 800 series chipset. The new chipset can be uniquely identified by its SPI speed, eSPI speed, and chipset name. This commit message is clear and concise, and it accurately describes the changes that were made to the code. It also includes the following information: - Specify the correct chipset name. "PCH Revision: 800 series Meteor Lake" - Show the valid eSPI/EC frequency. "Read eSPI/EC Bus Frequency: 20MHz" Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I70619d9e3ed2bcad86f84a0527e3a0ad13acd706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* util/ifdtool/ifdtool.c: Fix default FMAP generationMaximilian Brune2023-04-271-4/+10
| | | | | | | | | | | According to SPI programming guide, a region limit of 0 as well as region base of 7FFFh indicates an unused/reserved region. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I790d7f5631ecef3043b2c17c41430dc4fd854f72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* util/ifdtool: Add option to create FMAP templateMaximilian Brune2023-03-282-5/+105
| | | | | | | | | | | | | | | | | | | | | | On systems that do not provide their own *.fmd (Flashmap) file, we fall back to a default flashmap file. That file however does not contain the blobs (ME, GBE ...), that are usually placed below the BIOS Flashmap. It can therefore easily happen that the placement of the blobs collides with the placement of the BIOS region (e.g. if CBFS_SIZE is big enough). The fmaptool can't catch that, since it does not know of the blobs placement. This patch basically maps the regions described in the IFD (Intel Firmware Descriptor) to the default Flashmap. Test: Build and see that build/fmap.fmd contains all blobs now (on intel systems that are supported by the ifdtool) Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I82cb252fff456773af69943e188480a4998736fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* util/ifdtool/ifdtool.c: Clean upMaximilian Brune2023-03-092-206/+159
| | | | | | | | | | | | | | | | | | | | - Remove functions that are only called in one place. - Add warning if user doesn't supply a platform, since that can lead to dumps/layouts that do not include all IFD regions without the user even reliazing it. - Inform the User if IFD or Flashmap is not found. - Inform the User if there is not a single match between FMAP and IFD region - Avoid printing usage if not specifically asked by the user. It tends to obfuscate the original error message. - Keep indentation consistent throughout the file. - Remove typedefs (coreboot coding style) Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I7bbce63ecb2e920530394766f58b5ea6f72852e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* ifdtool: Introduce region_name_fmapPatrick Rudolph2023-02-021-2/+12
| | | | | | | | | | | | Instead of directly accessing the region_name array use a helper function. This allows to move the region name array to a separate file. Change-Id: Ifc810da1628cebd2728d0185502c462ff9428597 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* ifdtool: Add missing chipset_namePatrick Rudolph2023-02-021-0/+1
| | | | | | | | | | Add denverton soc chipset name. Change-Id: I0fd8494123490d6ccc21af2ed30c30d50ddb4e8e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68693 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ifdtool: Drop chipset without IFDPatrick Rudolph2023-02-022-14/+0
| | | | | | | | | | | Drop unused chipsets that do not use an IFD. Change-Id: I999e5e5d2063b8d33819fb22296ed486e1194cbb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* ifdtool: Cleanup IFDv1 detectionPatrick Rudolph2023-02-021-3/+0
| | | | | | | | | | | | | | | | Change https://review.coreboot.org/c/coreboot/+/54305 "util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset" made the '-p' argument mandatory for IFDv2 platforms. Drop the IFDv2 platform CHIPSET_C620_SERIES_LEWISBURG from IFDv1 detection. Change-Id: If29f8718b7aa696cdc07deef4c98be9a68c66f10 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68680 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool: Add Wellsburg supportPatrick Rudolph2023-02-022-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wellsburg is IFDv2 compatible in most fields, but not in all. It only has 8 regions and the flash master bits match the defines for IFDv1 and thus has an "IFDv1.5" descriptor. Add a new enum for IFDv1.5 descriptor and use them to properly operate on this IFD. The 'SPI programming guide' is inconsistent and mentions 6 regions in one place, but 7 regions in another chapter. Tests showed that it actually supports 7 regions. Add support using the -p argument to specify Wellsburg platform. The previous patch made sure that only 8 regions are used and that no corruption can happen when operating in IFDv2/IFDv1.5 mode. Tested on Intel Grangeville. Documents used: Intel Document Id: 516552 Intel Document Id: 565117 Change-Id: I651730b05deb512478d059174cf8615547d2fde4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Co-developed-by: Julian Elischer <jrelis@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* ifdtool: Determine max regions from IFDPatrick Rudolph2023-01-101-2/+49
| | | | | | | | | | | | | | | | | | | | | | | | | IFDv1 always has 8 regions, while IFDv2 always has 16 regions. It's platform specific which regions are used or are reserved. The 'SPI programming guide' as the name says is a guide only, not a specification what the hardware actually does. The best to do is not to rely on the guide, but detect how many regions are present in the IFD and expose them all. Very early IFDv2 chipsets, sometimes unofficially referred to as IFDv1.5 platforms, only have 8 regions. To not corrupt the IFD when operating on an IFDv1.5 detect how much space is actually present in the IFD. Fixes IFD corruption on Wellsburg/Lynxpoint when writing a new flash layout. Change-Id: I0e3f23ec580b8b8402eb1bf165e3995c8db633f1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* util/ifdtool/Makefile.inc: Respect LDFLAGS from environmentReka Norman2022-12-121-1/+1
| | | | | | | | | | | | | | | | | | | | | The ChromeOS build system performs ASAN builds by appending -fsanitize=address to CFLAGS and LDFLAGS. Currently, the ASAN build of ifdtool fails with linker errors because the Makefile does not respect LDFLAGS. Modify the Makefile to respect LDFLAGS from the environment. This is consistent with the Makefiles of most other coreboot utils. BUG=b:255462682 TEST=`USE=asan emerge-nissa coreboot-utils` now succeeds with CL:4018976 Change-Id: I1a497562d4d979829edb47c4c4b3f2c64266324e Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70054 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool/Makefile: improve cross-compilation supportMaciej Pijanowski2022-12-091-4/+4
| | | | | | | | | | | | | | | | | | | | | INSTALL and PREFIX variables will not be overwritten. Also, mkdir was replaced by a tool from the INSTALL variable to be compatible with other cross-compilation buildsystems (like Yocto). Overwriting variables generates problems when we use different buildsystem like Yocto where tool names are stored in environment variables. This change may make building the utility easier - the user of different buildsystem will not have to remember to pass correct tool names when issuing the make command. Also, this change does not affect the rest of users - if the variable was not set before, then it will be configured as before. Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Change-Id: Ia8dd67d18392e1e11d9160b187ef1a874d69ff5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70105 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool: Fix printing or setting PCH strapsArthur Heymans2022-06-231-7/+7
| | | | | | | | | | | When printing or setting the PCH straps use the PSL directly instead of multiplying it by 4. Change-Id: Ia91697fdf0c6d80502e8611b259c444f39c6cd57 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/ifdtool: Add Meteor Lake platform support under IFDv2Subrata Banik2022-03-152-0/+6
| | | | | | | | | | | | BUG=b:224325352 TEST=Able to build ifdtool. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3564efa27d0271286435284e745458aada987008 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/ifdtool: Add support for Denverton SoCJeff Daly2022-03-082-11/+73
| | | | | | | | | | | | | | | | Denverton is a special version of IFD2 flash layout. It defines 10GbE firmware regions (11/12) and the IE (10) region which other IFD2 platforms do not have. Denverton does not include the legacy GbE region (3) or the EC region (8) which other IFD2 platforms do have. TEST='ifdtool -p dnv coreboot.rom' and verify correct output Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/ifdtool: add generic `PLATFORM_IFD2` for early SoC developmentWonkyu Kim2022-02-092-0/+7
| | | | | | | | | | | | | | | | | | `PLATFORM_IFD2` macro is more generic tag that can be associated with early next SoC platform development which using IFDv2. The current assumption is that newer SoC platform still uses the same SPI/eSPI frequency definition being used for latest platform(TGL, ADL) and if the frequency definition is updated later, `PLATFORM_IFD2' will use latest frequency definition for early next SoC development. And once upstream is allowed for new platform, platform name will be added in tool later. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I14a71a58c7d51b9c8b92e013b5637c6b35005f22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* util/ifdtool: Add additional regions for platforms that support themJeff Daly2022-02-042-9/+34
| | | | | | | | | | | | Some Intel SoCs such as Denverton support additional SPI regions for things like Innovation Engine firmware or 10GbE LAN firmwares Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Ia5a450e5002e9f8edee76ca7c2eede9906df36c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* util/ifdtool/Makefile: Derive from Makefile.incPatrick Georgi2021-11-261-25/+8
| | | | | | | | | | | | Instead of maintaining two complete Makefiles, reuse the coreboot build system rules in the stand-alone Makefile. Change-Id: I5d894a1f079799478bce0bd200ac735097f3806b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59669 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool/Makefile: Fix building as standalone toolAngel Pons2021-11-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Commit f1e401c6cb70 (util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE) makes use of endianness conversion macros in cbfstool's FMAP code, which is also used by ifdtool. At least on Linux, the <endian.h> header provides these helpers, but only when `__USE_MISC` is defined, which is defined in the <ctypes.h> header when `_DEFAULT_SOURCE` is defined. This was accounted for in `Makefile.inc`, but not in `Makefile`. As a result, trying to build ifdtool as a standalone tool (i.e. not as part of building a coreboot image) results in build errors because the endianness conversion macros are not defined. Define `_DEFAULT_SOURCE` in `Makefile` to fix the build errors. Change-Id: I8c2bbc07ddd87d885e2d6f5c7f2bd501e5c4e3b0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59663 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BEMarek Kasiewicz2021-11-221-0/+1
| | | | | | | | | | | | | This patch makes all accesses to the FMAP fields explicitly little endian. It fixes issue where build on BE host produced different binary image than on LE. Signed-off-by: Marek Kasiewicz <marek.kasiewicz@3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: Ia88c0625cefa1e594ac1849271a71c3aacc8ce78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* util/ifdtool: Add APL to IFDv2 platformsSubrata Banik2021-07-151-2/+3
| | | | | | | | | | | | | | | | | Initially APL was considered as IFDv2 platform irrespective being added into ifd_2_platforms[], hence commit hash 621ed4c had migrated APL into IFDv1 which break its FLMSTR1/FLMSTR2/FLMSTR3 Read/Write access. This change adds APL into the list of IFDv2 platforms to fix booting issue on the LeafHill board. Change-Id: Ied59ddb2fe05b421266a6b119fd6eab17b8beedc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56300 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rick Lee <rick.lee@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool: Add sklkbl to IFDv2 platformsJan Tatje2021-07-071-2/+4
| | | | | | | | | | | | | | Currently ifdtool breaks the descriptor because it treats it as IFDv1. This change adds it to the list of IFDv2 platforms. Fixes boot for X11SSH-LN4F. Fixes: 8c082e5fef ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset") Change-Id: I3f92b090e929336b5c18b442d1504ee1000f5594 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56070 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool: Add Xeon SP Lewisburg PCH platform support under IFDv2Johnny Lin2021-06-262-0/+7
| | | | | | | | | | | | | | | After commit 8c082e5fe (util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset) w/o this xeon_sp/cpx would be detected as IFDv1 and see build error. Fixes: 8c082e5fe ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset") Change-Id: I444e7d35a85d9d42fc25d654e57386f38cf1ec85 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/ifdtool: Use ICH Strap Length (ISL) to identify APL chipsetSubrata Banik2021-06-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Use offset FLMAP1 bit 24:31, called ISL (ICH Strap Lenth) to uniquely identify the chipsets without any additional logic. +---------+-----------+ | Chipset | PSL Value | +---------+-----------+ | APL | 0x13 | +---------+-----------+ BUG=b:153888802 TEST=Able to dump FD contains correctly without specifying platform quirks on APL (IFDv1) Platform. > ifdtool -d coreboot.rom PCH Revision: Apollo Lake: N3xxx, J3xxx Change-Id: I02bcc6b1ca61c4ee59582f1b310ed0fba0ef1d9a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/ifdtool: Use -p platform name to detect IFDv2 platform and chipsetSubrata Banik2021-06-202-71/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ifdtool uses `chipset` information to determine how certain straps are decoded. This has been used for IFDv1 platforms as well as IFDv2 platforms (CHIPSET_500_600_SERIES_TIGER_ALDER_POINT). IFDv2 platforms are all expected to pass in `-p` argument to identify the platform. This platform information can be used to identify the appropriate chipset information. For IFDv1 since `-p` argument is not provided, ifdtool needs to use certain fields in the descriptor (e.g. strap length) for unique identification of IFDv1 chipset. This change updates `check_ifd_version()` function to: 1. Determine if IFD version is v1 or v2 based on `-p` argument. If `-p` is not provided, it assumes that the platform is using IFDv1. 2. Based on IFD version, it calls either `ifd2_platform_to_chipset()` or `ifd1_guess_chipset()` to determine chipset information. This fixes the issue reported with CB:44815, where ifdtool is unable to identify Alder Lake chipsets. BUG=b:153888802 TEST=Able to dump FD contains correctly with platform quirks on Brya Platform. > ifdtool -d coreboot.rom -p adl PCH Revision: 500 series Tiger Point/ 600 series Alder Point Change-Id: I25f69ce775454409974056d8326c02e29038ec8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54305 Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool: Add Elkhart Lake platform support under IFDv2Lean Sheng Tan2021-06-182-1/+7
| | | | | | | | | | | | | Add EHL under same family tree as TGL & JSL, also fix a spacing inconsistency line. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ice09861c104c4e339fc83631c75089fa069b3931 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55357 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool: Add coreboot build system supportPatrick Georgi2021-01-121-0/+18
| | | | | | | | | | | | | When building as part of the coreboot build system, use the same mechanism as other tools (cbfstool, amdfwtool, ...) so that abuild builds ifdtool once into sharedutils instead of once per board (while avoiding other race conditions, too). Change-Id: I42c7b43cc0859916174d59cba6b62630e70287fd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* util/ifdtool: Enable CPU read of the ME regionUsha P2020-11-021-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | We are implementing a mechanism in coreboot to update CSME firmware, this requires coreboot to be able to read CSME region. Exposing the CSME data is not an issue since the data stored by CSE is all encrypted. This patch provides a command line option "-r" which will enable read access to CSME region when locking. Without this change, locking SPI regions using ifdtool will block BIOS access to read/access CSME. This will cause failure since BIOS can't read basic information such as CSME version. TEST=Flashrom returns success while erasing the SI_ME region. After rebooting the DUT, DUT boots into OS without any issues on Drawlat EVT. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Reviewed-on: https://review.coreboot.org/c/coreboot/+/46441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* .gitignore: Ignore .test/.dependencies globallyPatrick Georgi2020-10-311-2/+0
| | | | | | | | | | | These were originally ignored only inside util/ but these files shouldn't be tracked anywhere. Change-Id: Ie0846bd8bdd6e52f420f9dd2e72a8a922102ff90 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* .gitignore: Split into subdirectory filesPatrick Georgi2020-10-301-0/+3
| | | | | | | | | | | | | | There's no need for the global list of files to ignore, so use git's ability to work with more local configuration. Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ifdtool: add "reserved" regionsStefan Reinauer2020-10-281-1/+7
| | | | | | | | | | This will let you at least dump / add these regions. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I195ba5e93823603e712cd16cecbb48141302bed6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* util/ifdtool: Include ADL dynamic check as per Gen12 SPI flash guideSubrata Banik2020-10-022-8/+9
| | | | | | | | | | | | | | | | | | BUG=b:153888802 TEST=Able to list correct PCH revision, SPI/eSPI frequency as per ADL SPI flash guide. Without this CL : PCH Revision: 500 series Tiger Point With this CL : PCH Revision: 500 series Tiger Point/ 600 series Alder Point Change-Id: I0faf0f0fdb625ff82eb0033b5b77e6470971bc23 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/ifdtool: Add NULL check for pointer fpsbaSubrata Banik2020-09-081-1/+1
| | | | | | | | | | | | | This patch adds NULL check inside get_ifd_version_from_fcba() function to fix Klocwork issue. BUG=b:153888802 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I525054376b36c658b93760b185ef6dd170f5aea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* util/ifdtool: Fix eSPI frequency as per Gen 11 SPI flash guideSubrata Banik2020-09-022-4/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:153888802 TEST=Able to list correct eSPI frequency as per TGL SPI flash guide Without this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read Clock Frequency: 20MHz With this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read eSPI/EC Bus Frequency: 60MHz Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I20840e6f931d7c1fabea0b6892e3bd19ead81168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/ifdtool: Fix SPI frequency as per Gen11 SPI flash guideSubrata Banik2020-09-022-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:153888802 TEST=Able to list correct SPI frequency as per TGL SPI flash guide Without this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: supported Read Clock Frequency: 20MHz With this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read Clock Frequency: 20MHz Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Id0a0a0cbd948ef8334cf522c09e881b464e87f0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool: Add FLMAP3 dump for Gen11 onwards PCHSubrata Banik2020-09-022-0/+7
| | | | | | | | | | | | | | | | BUG=b:153888802 TEST=Able to dump FLMAP3 for Volteer platform with TGP > ifdtool -d coreboot.rom FLMAP3: 0x00000000 Minor Revision ID: 0x0000 Major Revision ID: 0x0000 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I681abd6ae7b87f6638d4f6dc59168cf22b93c787 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44818 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCHSubrata Banik2020-09-021-8/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch performs below operations: 1. Remove reserved NR field from Gen 5 onwards SPI programming guide 2. Convert ISL to PSL as applicable for Gen 5 onwards PCH 3. Skip FLMAP2 register dump due to nonuniformity since Gen 5 onwards PCH 4. Dump FLILL1 register as applicable for Gen 5 onwards PCH 5. Remove FLPB register as not applicable since Gen 5 PCH BUG=b:153888802 TEST=Dump FD for Hatch platform as below > ifdtool -d coreboot.rom PCH Revision: 300 series Cannon Point/ 400 series Ice Point FLMAP0: 0x00040003 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x45100208 PSL: 0x45 FPSBA: 0x100 NM: 2 FMBA: 0x80 FLILL1 0xc7c4b9b7 Invalid Instruction 7: 0xc7 Invalid Instruction 6: 0xc4 Invalid Instruction 5: 0xb9 Invalid Instruction 4: 0xb7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5141ae5dd174659fde5401fac313a701ae4f8f44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/ifdtool: Identify between ICH and PCH RevisionSubrata Banik2020-09-021-1/+9
| | | | | | | | | | | | | | | | | | | | Consider IBEX_PEAK onwards all chipsets are belong to PCH family. BUG=b:153888802 TEST=Able to print correct PCH revision on Hatch Platform. > ifdtool -d coreboot.rom Without this CL : ICH Revision: 300 series Cannon Point/ 400 series Ice Point With this CL : PCH Revision: 300 series Cannon Point/ 400 series Ice Point Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ifd40dddc9179f347c0ea75149ec08089a829fdb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/ifdtool: Identify chipset without platform nameSubrata Banik2020-08-312-7/+42
| | | | | | | | | | | | | | | | | | | | | | | Able to uniquely identify the chipset without specifying the platform specific quirks (adl/cnl/icl/jsl/tgl etc.). BUG=b:153888802 TEST=Able to dump FD contains correctly without specifying platform quirks on Hatch Platform. > ifdtool -d coreboot.rom Without this CL : ICH Revision: 100 series Sunrise Point With this CL : ICH Revision: 300 series Cannon Point/ 400 series Ice Point Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I83763adb721e069343b19a10e503975ffa6abb24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44815 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool: Skip unused and reserved Flash RegionSubrata Banik2020-08-311-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch ensures all unused and reserved flash region sections are not getting listed while using -d option to dump FD. BUG=b:153888802 TEST=List only used flash region section with below command > ifdtool -p tgl -d coreboot.rom Without this CL : Found Region Section FLREG0: 0x00000000 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff FLREG1: 0x1fff0400 Flash Region 1 (BIOS): 00400000 - 01ffffff FLREG2: 0x03ff0001 Flash Region 2 (Intel ME): 00001000 - 003fffff FLREG3: 0x00007fff Flash Region 3 (GbE): 07fff000 - 00000fff (unused) FLREG4: 0x00007fff Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused) FLREG5: 0x00007fff Flash Region 5 (Reserved): 07fff000 - 00000fff (unused) FLREG6: 0x00007fff Flash Region 6 (Reserved): 07fff000 - 00000fff (unused) FLREG7: 0x00007fff Flash Region 7 (Reserved): 07fff000 - 00000fff (unused) FLREG8: 0x00007fff Flash Region 8 (EC): 07fff000 - 00000fff (unused) With this CL : Found Region Section FLREG0: 0x00000000 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff FLREG1: 0x1fff0400 Flash Region 1 (BIOS): 00400000 - 01ffffff FLREG2: 0x03ff0001 Flash Region 2 (Intel ME): 00001000 - 003fffff FLREG3: 0x00007fff Flash Region 3 (GbE): 07fff000 - 00000fff (unused) FLREG4: 0x00007fff Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused) FLREG8: 0x00007fff Flash Region 8 (EC): 07fff000 - 00000fff (unused) Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I900a29d8968bd61d66c04012e60e1ba4baff786d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/ifdtool: Add platform specific quirks for ADL/ICL/JSL/TGLSubrata Banik2020-08-311-4/+8
| | | | | | | | | | | | BUG=b:153888802 TEST=Able to dump FD contain using below command > ifdtool -p tgl -d coreboot.rom Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I0c9106051f4daf592d2467ebf79f9ddb037011dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/44809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/ifdtool: Add Alderlake platform support under IFDv2Subrata Banik2020-08-012-0/+5
| | | | | | | | Change-Id: Ief8ab6ad280d8a2625404c19d57cd2a24f23cf13 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39533 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-10 21:44:06 +0000