summaryrefslogtreecommitdiffstats
path: root/src/soc/intel/cannonlake/include/soc/romstage.h
blob: 46ab5496f8b25b43a0b921bd6db55c38eb48d7bb (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef _SOC_ROMSTAGE_H_
#define _SOC_ROMSTAGE_H_

#include <fsp/api.h>

void mainboard_memory_init_params(FSPM_UPD *mupd);

/* Provide a callback to allow mainboard to override the DRAM part number. */
void mainboard_get_dram_part_num(const char **part_num, size_t *len);
void systemagent_early_init(void);
void romstage_pch_init(void);

/* Board type */
enum board_type {
	BOARD_TYPE_MOBILE  = 0,
	BOARD_TYPE_DESKTOP = 1,
	BOARD_TYPE_ULT_ULX = 5,
	BOARD_TYPE_SERVER  = 7
};

#endif /* _SOC_ROMSTAGE_H_ */