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| author | Neo Hsueh <Hong-Chih.Hsueh@amd.com> | 2024-05-01 14:13:39 -0500 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-06-05 12:22:53 +0000 |
| commit | 10cd8b45ce36152996bcb1520ba36107a8cdc63f (patch) | |
| tree | 7f7753739ee78813fb55b0b2b556b08429b08e1d | |
| parent | e2e09d8512898709a3d076fdd36c8abee2734027 (diff) | |
| download | edk2-10cd8b45ce36152996bcb1520ba36107a8cdc63f.tar.gz edk2-10cd8b45ce36152996bcb1520ba36107a8cdc63f.tar.bz2 edk2-10cd8b45ce36152996bcb1520ba36107a8cdc63f.zip | |
MdePkg: Remove non-ASCII characters from header file
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4775
Signed-off-by: Neo Hsueh <Hong-Chih.Hsueh@amd.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Jiangang He <jiangang.he@amd.com>
| -rw-r--r-- | MdePkg/Include/Register/Amd/Cpuid.h | 4 | ||||
| -rw-r--r-- | MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 8 |
2 files changed, 6 insertions, 6 deletions
diff --git a/MdePkg/Include/Register/Amd/Cpuid.h b/MdePkg/Include/Register/Amd/Cpuid.h index add43c40aa..51fa9f235c 100644 --- a/MdePkg/Include/Register/Amd/Cpuid.h +++ b/MdePkg/Include/Register/Amd/Cpuid.h @@ -46,9 +46,9 @@ CPUID Signature Information CPUID Extended Topology Enumeration
@note
- Reference: AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions,
+ Reference: AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions,
Revision 3.35 Appendix E,
- E.4.24 Function 8000_0026—Extended CPU Topology:
+ E.4.24 Function 8000_0026-Extended CPU Topology:
CPUID Fn8000_0026 reports extended topology information for logical processors, including
asymmetric and heterogenous topology descriptions. Individual logical processors may report
different values in systems with asynchronous and heterogeneous topologies.
diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h index 756e7c86ec..4715c59dc4 100644 --- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h +++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h @@ -5733,9 +5733,9 @@ typedef union { /// [Bit 7:4] TME Policy/Encryption Algorithm: Only algorithms enumerated in
/// IA32_TME_CAPABILITY are allowed.
/// For example:
- /// 0000 – AES-XTS-128.
- /// 0001 – AES-XTS-128 with integrity.
- /// 0010 – AES-XTS-256.
+ /// 0000 - AES-XTS-128.
+ /// 0001 - AES-XTS-128 with integrity.
+ /// 0010 - AES-XTS-256.
/// Other values are invalid.
///
UINT32 TmePolicy : 4;
@@ -5756,7 +5756,7 @@ typedef union { /// Similar to enumeration, this is an encoded value.
/// Writing a value greater than MK_TME_MAX_KEYID_BITS will result in #GP.
/// Writing a non-zero value to this field will #GP if bit 1 of EAX (Hardware
- /// Encryption Enable) is not also set to ‘1, as encryption hardware must be
+ /// Encryption Enable) is not also set to 1, as encryption hardware must be
/// enabled to use MKTME.
/// Example: To support 255 keys, this field would be set to a value of 8.
///
|