IntelFsp2Pkg: Apply uncrustify changes

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the IntelFsp2Pkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

33 files changed, 894 insertions, 899 deletions

diff --git a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c
index 4803008012..88f5540fef 100644
--- a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c
+++ b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c
@@ -21,28 +21,28 @@
 EFI_STATUS

 EFIAPI

 WaitForNotify (

-  IN CONST EFI_DXE_IPL_PPI *This,

-  IN EFI_PEI_SERVICES      **PeiServices,

-  IN EFI_PEI_HOB_POINTERS  HobList

+  IN CONST EFI_DXE_IPL_PPI  *This,

+  IN EFI_PEI_SERVICES       **PeiServices,

+  IN EFI_PEI_HOB_POINTERS   HobList

   );

 

-CONST EFI_DXE_IPL_PPI mDxeIplPpi = {

+CONST EFI_DXE_IPL_PPI  mDxeIplPpi = {

   WaitForNotify

 };

 

-CONST EFI_PEI_PPI_DESCRIPTOR mInstallDxeIplPpi = {

+CONST EFI_PEI_PPI_DESCRIPTOR  mInstallDxeIplPpi = {

   EFI_PEI_PPI_DESCRIPTOR_PPI,

   &gEfiDxeIplPpiGuid,

-  (VOID *) &mDxeIplPpi

+  (VOID *)&mDxeIplPpi

 };

 

-CONST EFI_PEI_PPI_DESCRIPTOR gEndOfPeiSignalPpi = {

+CONST EFI_PEI_PPI_DESCRIPTOR  gEndOfPeiSignalPpi = {

   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),

   &gEfiEndOfPeiSignalPpiGuid,

   NULL

 };

 

-CONST EFI_PEI_PPI_DESCRIPTOR gFspReadyForNotifyPhasePpi = {

+CONST EFI_PEI_PPI_DESCRIPTOR  gFspReadyForNotifyPhasePpi = {

   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),

   &gFspReadyForNotifyPhasePpiGuid,

   NULL

@@ -62,12 +62,12 @@ CONST EFI_PEI_PPI_DESCRIPTOR gFspReadyForNotifyPhasePpi = {
 EFI_STATUS

 EFIAPI

 WaitForNotify (

-  IN CONST EFI_DXE_IPL_PPI *This,

-  IN EFI_PEI_SERVICES      **PeiServices,

-  IN EFI_PEI_HOB_POINTERS  HobList

+  IN CONST EFI_DXE_IPL_PPI  *This,

+  IN EFI_PEI_SERVICES       **PeiServices,

+  IN EFI_PEI_HOB_POINTERS   HobList

   )

 {

-  EFI_STATUS   Status;

+  EFI_STATUS  Status;

 

   DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP HOB is located at 0x%08X\n", HobList));

 

@@ -113,13 +113,13 @@ WaitForNotify (
 **/

 EFI_STATUS

 FspNotifyPhasePeimEntryPoint (

-  IN       EFI_PEI_FILE_HANDLE    FileHandle,

-  IN CONST EFI_PEI_SERVICES       **PeiServices

+  IN       EFI_PEI_FILE_HANDLE  FileHandle,

+  IN CONST EFI_PEI_SERVICES     **PeiServices

   )

 {

-  EFI_STATUS                      Status;

-  VOID                            *OldDxeIplPpi;

-  EFI_PEI_PPI_DESCRIPTOR          *OldDescriptor;

+  EFI_STATUS              Status;

+  VOID                    *OldDxeIplPpi;

+  EFI_PEI_PPI_DESCRIPTOR  *OldDescriptor;

 

   DEBUG ((DEBUG_INFO | DEBUG_INIT, "The entry of FspNotificationPeim\n"));

 

@@ -128,11 +128,11 @@ FspNotifyPhasePeimEntryPoint (
     // Locate old DXE IPL PPI

     //

     Status = PeiServicesLocatePpi (

-              &gEfiDxeIplPpiGuid,

-              0,

-              &OldDescriptor,

-              &OldDxeIplPpi

-              );

+               &gEfiDxeIplPpiGuid,

+               0,

+               &OldDescriptor,

+               &OldDxeIplPpi

+               );

     ASSERT_EFI_ERROR (Status);

 

     //

diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c
index 216f7bb6c5..ae03fa228e 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
@@ -17,20 +17,20 @@
 

 **/

 UINT64

-FspGetExceptionHandler(

+FspGetExceptionHandler (

   IN  UINT64  IdtEntryTemplate

   )

 {

   UINT32                    Entry;

   UINT64                    ExceptionHandler;

-  IA32_IDT_GATE_DESCRIPTOR *IdtGateDescriptor;

-  FSP_INFO_HEADER          *FspInfoHeader;

-

-  FspInfoHeader     = (FSP_INFO_HEADER *)AsmGetFspInfoHeader();

-  ExceptionHandler  = IdtEntryTemplate;

-  IdtGateDescriptor = (IA32_IDT_GATE_DESCRIPTOR *)&ExceptionHandler;

-  Entry = (IdtGateDescriptor->Bits.OffsetHigh << 16) | IdtGateDescriptor->Bits.OffsetLow;

-  Entry = FspInfoHeader->ImageBase + FspInfoHeader->ImageSize - (~Entry + 1);

+  IA32_IDT_GATE_DESCRIPTOR  *IdtGateDescriptor;

+  FSP_INFO_HEADER           *FspInfoHeader;

+

+  FspInfoHeader                      = (FSP_INFO_HEADER *)AsmGetFspInfoHeader ();

+  ExceptionHandler                   = IdtEntryTemplate;

+  IdtGateDescriptor                  = (IA32_IDT_GATE_DESCRIPTOR *)&ExceptionHandler;

+  Entry                              = (IdtGateDescriptor->Bits.OffsetHigh << 16) | IdtGateDescriptor->Bits.OffsetLow;

+  Entry                              = FspInfoHeader->ImageBase + FspInfoHeader->ImageSize - (~Entry + 1);

   IdtGateDescriptor->Bits.OffsetHigh = (UINT16)(Entry >> 16);

   IdtGateDescriptor->Bits.OffsetLow  = (UINT16)Entry;

 

@@ -46,13 +46,13 @@ FspGetExceptionHandler(
 VOID

 EFIAPI

 SecGetPlatformData (

-  IN OUT  FSP_GLOBAL_DATA    *FspData

+  IN OUT  FSP_GLOBAL_DATA  *FspData

   )

 {

-  FSP_PLAT_DATA    *FspPlatformData;

-  UINT32            TopOfCar;

-  UINT32           *StackPtr;

-  UINT32            DwordSize;

+  FSP_PLAT_DATA  *FspPlatformData;

+  UINT32         TopOfCar;

+  UINT32         *StackPtr;

+  UINT32         DwordSize;

 

   FspPlatformData = &FspData->PlatformData;

 

@@ -61,7 +61,7 @@ SecGetPlatformData (
   // reside in the bottom of stack, left untouched by normal stack operation.

   //

 

-  FspPlatformData->DataPtr   = NULL;

+  FspPlatformData->DataPtr             = NULL;

   FspPlatformData->MicrocodeRegionBase = 0;

   FspPlatformData->MicrocodeRegionSize = 0;

   FspPlatformData->CodeRegionBase      = 0;

@@ -70,7 +70,7 @@ SecGetPlatformData (
   //

   // Pointer to the size field

   //

-  TopOfCar = PcdGet32(PcdTemporaryRamBase) + PcdGet32(PcdTemporaryRamSize);

+  TopOfCar = PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamSize);

   StackPtr = (UINT32 *)(TopOfCar - sizeof (UINT32));

 

   if (*(StackPtr - 1) == FSP_MCUD_SIGNATURE) {

@@ -114,26 +114,26 @@ SecGetPlatformData (
 **/

 VOID

 FspGlobalDataInit (

-  IN OUT  FSP_GLOBAL_DATA    *PeiFspData,

-  IN UINT32                   BootLoaderStack,

-  IN UINT8                    ApiIdx

+  IN OUT  FSP_GLOBAL_DATA  *PeiFspData,

+  IN UINT32                BootLoaderStack,

+  IN UINT8                 ApiIdx

   )

 {

-  VOID              *FspmUpdDataPtr;

-  CHAR8              ImageId[9];

-  UINTN              Idx;

+  VOID   *FspmUpdDataPtr;

+  CHAR8  ImageId[9];

+  UINTN  Idx;

 

   //

   // Set FSP Global Data pointer

   //

-  SetFspGlobalDataPointer    (PeiFspData);

-  ZeroMem  ((VOID *)PeiFspData, sizeof(FSP_GLOBAL_DATA));

+  SetFspGlobalDataPointer (PeiFspData);

+  ZeroMem ((VOID *)PeiFspData, sizeof (FSP_GLOBAL_DATA));

 

-  PeiFspData->Signature            = FSP_GLOBAL_DATA_SIGNATURE;

-  PeiFspData->Version              = 0;

-  PeiFspData->CoreStack            = BootLoaderStack;

-  PeiFspData->PerfIdx              = 2;

-  PeiFspData->PerfSig              = FSP_PERFORMANCE_DATA_SIGNATURE;

+  PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE;

+  PeiFspData->Version   = 0;

+  PeiFspData->CoreStack = BootLoaderStack;

+  PeiFspData->PerfIdx   = 2;

+  PeiFspData->PerfSig   = FSP_PERFORMANCE_DATA_SIGNATURE;

 

   SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY);

 

@@ -141,7 +141,7 @@ FspGlobalDataInit (
   // Get FSP Header offset

   // It may have multiple FVs, so look into the last one for FSP header

   //

-  PeiFspData->FspInfoHeader      = (FSP_INFO_HEADER *)AsmGetFspInfoHeader();

+  PeiFspData->FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader ();

   SecGetPlatformData (PeiFspData);

 

   //

@@ -152,10 +152,11 @@ FspGlobalDataInit (
   //

   // Set UPD pointer

   //

-  FspmUpdDataPtr = (VOID *) GetFspApiParameter ();

+  FspmUpdDataPtr = (VOID *)GetFspApiParameter ();

   if (FspmUpdDataPtr == NULL) {

     FspmUpdDataPtr = (VOID *)(PeiFspData->FspInfoHeader->ImageBase + PeiFspData->FspInfoHeader->CfgRegionOffset);

   }

+

   SetFspUpdDataPointer (FspmUpdDataPtr);

   SetFspMemoryInitUpdDataPointer (FspmUpdDataPtr);

   SetFspSiliconInitUpdDataPointer (NULL);

@@ -186,17 +187,21 @@ FspGlobalDataInit (
   for (Idx = 0; Idx < 8; Idx++) {

     ImageId[Idx] = PeiFspData->FspInfoHeader->ImageId[Idx];

   }

+

   ImageId[Idx] = 0;

 

-  DEBUG ((DEBUG_INFO | DEBUG_INIT, "\n============= FSP Spec v%d.%d Header Revision v%x (%a v%x.%x.%x.%x) =============\n", \

-         (PeiFspData->FspInfoHeader->SpecVersion >> 4) & 0xF, \

-         PeiFspData->FspInfoHeader->SpecVersion & 0xF, \

-         PeiFspData->FspInfoHeader->HeaderRevision, \

-         ImageId, \

-         (PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xFF, \

-         (PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xFF, \

-         (PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xFF, \

-         PeiFspData->FspInfoHeader->ImageRevision & 0xFF));

+  DEBUG ((

+    DEBUG_INFO | DEBUG_INIT,

+    "\n============= FSP Spec v%d.%d Header Revision v%x (%a v%x.%x.%x.%x) =============\n", \

+    (PeiFspData->FspInfoHeader->SpecVersion >> 4) & 0xF, \

+    PeiFspData->FspInfoHeader->SpecVersion & 0xF, \

+    PeiFspData->FspInfoHeader->HeaderRevision, \

+    ImageId, \

+    (PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xFF, \

+    (PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xFF, \

+    (PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xFF, \

+    PeiFspData->FspInfoHeader->ImageRevision & 0xFF

+    ));

 }

 

 /**

@@ -208,11 +213,11 @@ FspGlobalDataInit (
 **/

 VOID

 FspDataPointerFixUp (

-  IN UINT32   OffsetGap

+  IN UINT32  OffsetGap

   )

 {

   FSP_GLOBAL_DATA  *NewFspData;

 

-  NewFspData = (FSP_GLOBAL_DATA *)((UINTN)GetFspGlobalDataPointer() + (UINTN)OffsetGap);

+  NewFspData = (FSP_GLOBAL_DATA *)((UINTN)GetFspGlobalDataPointer () + (UINTN)OffsetGap);

   SetFspGlobalDataPointer (NewFspData);

 }

diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.h b/IntelFsp2Pkg/FspSecCore/SecFsp.h
index 75f3ef463c..aacd32f7f7 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.h
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.h
@@ -31,7 +31,7 @@
 

 **/

 UINT64

-FspGetExceptionHandler(

+FspGetExceptionHandler (

   IN  UINT64  IdtEntryTemplate

   );

 

@@ -47,12 +47,11 @@ FspGetExceptionHandler(
 **/

 VOID

 FspGlobalDataInit (

-  IN OUT  FSP_GLOBAL_DATA    *PeiFspData,

-  IN UINT32                   BootLoaderStack,

-  IN UINT8                    ApiIdx

+  IN OUT  FSP_GLOBAL_DATA  *PeiFspData,

+  IN UINT32                BootLoaderStack,

+  IN UINT8                 ApiIdx

   );

 

-

 /**

 

   Adjust the FSP data pointers after the stack is migrated to memory.

@@ -62,10 +61,9 @@ FspGlobalDataInit (
 **/

 VOID

 FspDataPointerFixUp (

-  IN UINT32   OffsetGap

+  IN UINT32  OffsetGap

   );

 

-

 /**

   This interface returns the base address of FSP binary.

 

diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
index 1334959005..7d6ef11fe7 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
@@ -7,7 +7,6 @@
 

 #include "SecFsp.h"

 

-

 /**

   This function check the FSP API calling condition.

 

@@ -18,14 +17,14 @@
 EFI_STATUS

 EFIAPI

 FspApiCallingCheck (

-  IN UINT8     ApiIdx,

-  IN VOID     *ApiParam

+  IN UINT8  ApiIdx,

+  IN VOID   *ApiParam

   )

 {

-  EFI_STATUS                Status;

-  FSP_GLOBAL_DATA           *FspData;

+  EFI_STATUS       Status;

+  FSP_GLOBAL_DATA  *FspData;

 

-  Status = EFI_SUCCESS;

+  Status  = EFI_SUCCESS;

   FspData = GetFspGlobalDataPointer ();

 

   if (ApiIdx == NotifyPhaseApiIndex) {

diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c b/IntelFsp2Pkg/FspSecCore/SecMain.c
index 540571187a..d376fb8361 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -8,11 +8,11 @@
 #include "SecMain.h"

 #include "SecFsp.h"

 

-EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI gSecTemporaryRamSupportPpi = {

+EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI  gSecTemporaryRamSupportPpi = {

   SecTemporaryRamSupport

 };

 

-EFI_PEI_PPI_DESCRIPTOR            mPeiSecPlatformInformationPpi[] = {

+EFI_PEI_PPI_DESCRIPTOR  mPeiSecPlatformInformationPpi[] = {

   {

     EFI_PEI_PPI_DESCRIPTOR_PPI,

     &gFspInApiModePpiGuid,

@@ -50,21 +50,21 @@ UINT64  mIdtEntryTemplate = 0xffff8e000008ffe4ULL;
 VOID

 EFIAPI

 SecStartup (

-  IN UINT32                   SizeOfRam,

-  IN UINT32                   TempRamBase,

-  IN VOID                    *BootFirmwareVolume,

-  IN PEI_CORE_ENTRY           PeiCore,

-  IN UINT32                   BootLoaderStack,

-  IN UINT32                   ApiIdx

+  IN UINT32          SizeOfRam,

+  IN UINT32          TempRamBase,

+  IN VOID            *BootFirmwareVolume,

+  IN PEI_CORE_ENTRY  PeiCore,

+  IN UINT32          BootLoaderStack,

+  IN UINT32          ApiIdx

   )

 {

-  EFI_SEC_PEI_HAND_OFF        SecCoreData;

-  IA32_DESCRIPTOR             IdtDescriptor;

-  SEC_IDT_TABLE               IdtTableInStack;

-  UINT32                      Index;

-  FSP_GLOBAL_DATA             PeiFspData;

-  UINT64                      ExceptionHandler;

-  UINTN                       IdtSize;

+  EFI_SEC_PEI_HAND_OFF  SecCoreData;

+  IA32_DESCRIPTOR       IdtDescriptor;

+  SEC_IDT_TABLE         IdtTableInStack;

+  UINT32                Index;

+  FSP_GLOBAL_DATA       PeiFspData;

+  UINT64                ExceptionHandler;

+  UINTN                 IdtSize;

 

   //

   // Process all libraries constructor function linked to SecCore.

@@ -117,10 +117,11 @@ SecStartup (
   IdtTableInStack.PeiService = 0;

   AsmReadIdtr (&IdtDescriptor);

   if (IdtDescriptor.Base == 0) {

-    ExceptionHandler = FspGetExceptionHandler(mIdtEntryTemplate);

-    for (Index = 0; Index < FixedPcdGet8(PcdFspMaxInterruptSupported); Index ++) {

-      CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&ExceptionHandler, sizeof (UINT64));

+    ExceptionHandler = FspGetExceptionHandler (mIdtEntryTemplate);

+    for (Index = 0; Index < FixedPcdGet8 (PcdFspMaxInterruptSupported); Index++) {

+      CopyMem ((VOID *)&IdtTableInStack.IdtTable[Index], (VOID *)&ExceptionHandler, sizeof (UINT64));

     }

+

     IdtSize = sizeof (IdtTableInStack.IdtTable);

   } else {

     IdtSize = IdtDescriptor.Limit + 1;

@@ -128,12 +129,13 @@ SecStartup (
       //

       // ERROR: IDT table size from boot loader is larger than FSP can support, DeadLoop here!

       //

-      CpuDeadLoop();

+      CpuDeadLoop ();

     } else {

-      CopyMem ((VOID *) (UINTN) &IdtTableInStack.IdtTable, (VOID *) IdtDescriptor.Base, IdtSize);

+      CopyMem ((VOID *)(UINTN)&IdtTableInStack.IdtTable, (VOID *)IdtDescriptor.Base, IdtSize);

     }

   }

-  IdtDescriptor.Base  = (UINTN) &IdtTableInStack.IdtTable;

+

+  IdtDescriptor.Base  = (UINTN)&IdtTableInStack.IdtTable;

   IdtDescriptor.Limit = (UINT16)(IdtSize - 1);

 

   AsmWriteIdtr (&IdtDescriptor);

@@ -154,18 +156,18 @@ SecStartup (
   // Support FSP reserved temporary memory from the whole temporary memory provided by bootloader.

   // FSP reserved temporary memory will not be given to PeiCore.

   //

-  SecCoreData.TemporaryRamBase       = (UINT8 *)(UINTN) TempRamBase  + PcdGet32 (PcdFspPrivateTemporaryRamSize);

-  SecCoreData.TemporaryRamSize       = SizeOfRam - PcdGet32 (PcdFspPrivateTemporaryRamSize);

+  SecCoreData.TemporaryRamBase = (UINT8 *)(UINTN)TempRamBase  + PcdGet32 (PcdFspPrivateTemporaryRamSize);

+  SecCoreData.TemporaryRamSize = SizeOfRam - PcdGet32 (PcdFspPrivateTemporaryRamSize);

   if (PcdGet8 (PcdFspHeapSizePercentage) == 0) {

-    SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;

-    SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize;

-    SecCoreData.StackBase              = (VOID *)GetFspEntryStack(); // Share the same boot loader stack

-    SecCoreData.StackSize              = 0;

+    SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;

+    SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize;

+    SecCoreData.StackBase           = (VOID *)GetFspEntryStack ();   // Share the same boot loader stack

+    SecCoreData.StackSize           = 0;

   } else {

-    SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;

-    SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100;

-    SecCoreData.StackBase              = (VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);

-    SecCoreData.StackSize              = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;

+    SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;

+    SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100;

+    SecCoreData.StackBase           = (VOID *)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);

+    SecCoreData.StackSize           = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;

   }

 

   DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase));

@@ -207,22 +209,22 @@ SecStartup (
 EFI_STATUS

 EFIAPI

 SecTemporaryRamSupport (

-  IN CONST EFI_PEI_SERVICES   **PeiServices,

-  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,

-  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,

-  IN UINTN                    CopySize

+  IN CONST EFI_PEI_SERVICES  **PeiServices,

+  IN EFI_PHYSICAL_ADDRESS    TemporaryMemoryBase,

+  IN EFI_PHYSICAL_ADDRESS    PermanentMemoryBase,

+  IN UINTN                   CopySize

   )

 {

-  IA32_DESCRIPTOR   IdtDescriptor;

-  VOID*             OldHeap;

-  VOID*             NewHeap;

-  VOID*             OldStack;

-  VOID*             NewStack;

-  UINTN             HeapSize;

-  UINTN             StackSize;

+  IA32_DESCRIPTOR  IdtDescriptor;

+  VOID             *OldHeap;

+  VOID             *NewHeap;

+  VOID             *OldStack;

+  VOID             *NewStack;

+  UINTN            HeapSize;

+  UINTN            StackSize;

 

-  UINTN             CurrentStack;

-  UINTN             FspStackBase;

+  UINTN  CurrentStack;

+  UINTN  FspStackBase;

 

   //

   // Override OnSeparateStack to 1 because this function will switch stack to permanent memory

@@ -231,33 +233,31 @@ SecTemporaryRamSupport (
   GetFspGlobalDataPointer ()->OnSeparateStack = 1;

 

   if (PcdGet8 (PcdFspHeapSizePercentage) == 0) {

-

-    CurrentStack = AsmReadEsp();

-    FspStackBase = (UINTN)GetFspEntryStack();

+    CurrentStack = AsmReadEsp ();

+    FspStackBase = (UINTN)GetFspEntryStack ();

 

     StackSize = FspStackBase - CurrentStack;

     HeapSize  = CopySize;

 

-    OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;

-    NewHeap = (VOID*)((UINTN)PermanentMemoryBase);

+    OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;

+    NewHeap = (VOID *)((UINTN)PermanentMemoryBase);

 

-    OldStack = (VOID*)CurrentStack;

+    OldStack = (VOID *)CurrentStack;

     //

-    //The old stack is copied at the end of the stack region because stack grows down.

+    // The old stack is copied at the end of the stack region because stack grows down.

     //

-    NewStack = (VOID*)((UINTN)PermanentMemoryBase - StackSize);

-

+    NewStack = (VOID *)((UINTN)PermanentMemoryBase - StackSize);

   } else {

-    HeapSize   = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100 ;

-    StackSize  = CopySize - HeapSize;

+    HeapSize  = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100;

+    StackSize = CopySize - HeapSize;

 

-    OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;

-    NewHeap = (VOID*)((UINTN)PermanentMemoryBase + StackSize);

-

-    OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);

-    NewStack = (VOID*)(UINTN)PermanentMemoryBase;

+    OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;

+    NewHeap = (VOID *)((UINTN)PermanentMemoryBase + StackSize);

 

+    OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);

+    NewStack = (VOID *)(UINTN)PermanentMemoryBase;

   }

+

   //

   // Migrate Heap

   //

@@ -268,7 +268,6 @@ SecTemporaryRamSupport (
   //

   CopyMem (NewStack, OldStack, StackSize);

 

-

   //

   // We need *not* fix the return address because currently,

   // The PeiCore is executed in flash.

@@ -293,8 +292,8 @@ SecTemporaryRamSupport (
   // permanent memory.

   //

   SecSwitchStack (

-    (UINT32) (UINTN) OldStack,

-    (UINT32) (UINTN) NewStack

+    (UINT32)(UINTN)OldStack,

+    (UINT32)(UINTN)NewStack

     );

 

   return EFI_SUCCESS;

diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.h b/IntelFsp2Pkg/FspSecCore/SecMain.h
index f6333b0ffb..7794255af1 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.h
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.h
@@ -8,7 +8,6 @@
 #ifndef _SEC_CORE_H_

 #define _SEC_CORE_H_

 

-

 #include <PiPei.h>

 #include <Ppi/TemporaryRamSupport.h>

 

@@ -27,7 +26,7 @@
 typedef VOID (*PEI_CORE_ENTRY) ( \

   IN CONST  EFI_SEC_PEI_HAND_OFF    *SecCoreData, \

   IN CONST  EFI_PEI_PPI_DESCRIPTOR  *PpiList \

-);

+  );

 

 typedef struct _SEC_IDT_TABLE {

   //

@@ -36,8 +35,8 @@ typedef struct _SEC_IDT_TABLE {
   // Note: For IA32, only the 4 bytes immediately preceding IDT is used to store

   // EFI_PEI_SERVICES**

   //

-  UINT64            PeiService;

-  UINT64            IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)];

+  UINT64    PeiService;

+  UINT64    IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)];

 } SEC_IDT_TABLE;

 

 /**

@@ -52,8 +51,8 @@ typedef struct _SEC_IDT_TABLE {
 VOID

 EFIAPI

 SecSwitchStack (

-  IN UINT32   TemporaryMemoryBase,

-  IN UINT32   PermenentMemoryBase

+  IN UINT32  TemporaryMemoryBase,

+  IN UINT32  PermenentMemoryBase

   );

 

 /**

@@ -75,13 +74,12 @@ SecSwitchStack (
 EFI_STATUS

 EFIAPI

 SecTemporaryRamSupport (

-  IN CONST EFI_PEI_SERVICES   **PeiServices,

-  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,

-  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,

-  IN UINTN                    CopySize

+  IN CONST EFI_PEI_SERVICES  **PeiServices,

+  IN EFI_PHYSICAL_ADDRESS    TemporaryMemoryBase,

+  IN EFI_PHYSICAL_ADDRESS    PermanentMemoryBase,

+  IN UINTN                   CopySize

   );

 

-

 /**

 

   Entry point to the C language phase of SEC. After the SEC assembly

@@ -102,12 +100,12 @@ SecTemporaryRamSupport (
 VOID

 EFIAPI

 SecStartup (

-  IN UINT32                   SizeOfRam,

-  IN UINT32                   TempRamBase,

-  IN VOID                    *BootFirmwareVolume,

-  IN PEI_CORE_ENTRY           PeiCore,

-  IN UINT32                   BootLoaderStack,

-  IN UINT32                   ApiIdx

+  IN UINT32          SizeOfRam,

+  IN UINT32          TempRamBase,

+  IN VOID            *BootFirmwareVolume,

+  IN PEI_CORE_ENTRY  PeiCore,

+  IN UINT32          BootLoaderStack,

+  IN UINT32          ApiIdx

   );

 

 /**

diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/FspEas/FspApi.h
index 5e488c452a..794f94dc7a 100644
--- a/IntelFsp2Pkg/Include/FspEas/FspApi.h
+++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h
@@ -16,21 +16,21 @@
 /// FSP Reset Status code

 /// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code

 /// @{

-#define FSP_STATUS_RESET_REQUIRED_COLD         0x40000001

-#define FSP_STATUS_RESET_REQUIRED_WARM         0x40000002

-#define FSP_STATUS_RESET_REQUIRED_3            0x40000003

-#define FSP_STATUS_RESET_REQUIRED_4            0x40000004

-#define FSP_STATUS_RESET_REQUIRED_5            0x40000005

-#define FSP_STATUS_RESET_REQUIRED_6            0x40000006

-#define FSP_STATUS_RESET_REQUIRED_7            0x40000007

-#define FSP_STATUS_RESET_REQUIRED_8            0x40000008

+#define FSP_STATUS_RESET_REQUIRED_COLD  0x40000001

+#define FSP_STATUS_RESET_REQUIRED_WARM  0x40000002

+#define FSP_STATUS_RESET_REQUIRED_3     0x40000003

+#define FSP_STATUS_RESET_REQUIRED_4     0x40000004

+#define FSP_STATUS_RESET_REQUIRED_5     0x40000005

+#define FSP_STATUS_RESET_REQUIRED_6     0x40000006

+#define FSP_STATUS_RESET_REQUIRED_7     0x40000007

+#define FSP_STATUS_RESET_REQUIRED_8     0x40000008

 /// @}

 

 ///

 /// FSP Event related definition.

 ///

-#define FSP_EVENT_CODE   0xF5000000

-#define FSP_POST_CODE    (FSP_EVENT_CODE | 0x00F80000)

+#define FSP_EVENT_CODE  0xF5000000

+#define FSP_POST_CODE   (FSP_EVENT_CODE | 0x00F80000)

 

 /*

   FSP may optionally include the capability of generating events messages to aid in the debugging of firmware issues.

@@ -60,7 +60,7 @@
 */

 typedef

 EFI_STATUS

-(EFIAPI *FSP_EVENT_HANDLER) (

+(EFIAPI *FSP_EVENT_HANDLER)(

   IN          EFI_STATUS_CODE_TYPE   Type,

   IN          EFI_STATUS_CODE_VALUE  Value,

   IN          UINT32                 Instance,

@@ -80,8 +80,8 @@ EFI_STATUS
 */

 typedef

 UINT32

-(EFIAPI *FSP_DEBUG_HANDLER) (

-  IN CHAR8*                 DebugMessage,

+(EFIAPI *FSP_DEBUG_HANDLER)(

+  IN CHAR8 *DebugMessage,

   IN UINT32                 MessageLength

   );

 

@@ -97,14 +97,14 @@ typedef struct {
   /// "XXXXXX_S" for FSP-S

   /// Where XXXXXX is an unique signature

   ///

-  UINT64                      Signature;

+  UINT64    Signature;

   ///

   /// Revision of the Data structure.

   ///   For FSP spec 2.0/2.1 value is 1.

   ///   For FSP spec 2.2 value is 2.

   ///

-  UINT8                       Revision;

-  UINT8                       Reserved[23];

+  UINT8     Revision;

+  UINT8     Reserved[23];

 } FSP_UPD_HEADER;

 

 ///

@@ -114,18 +114,18 @@ typedef struct {
   ///

   /// Revision Revision of the structure is 1 for this version of the specification.

   ///

-  UINT8                       Revision;

-  UINT8                       Reserved[3];

+  UINT8                Revision;

+  UINT8                Reserved[3];

   ///

   /// Length Length of the structure in bytes. The current value for this field is 32.

   ///

-  UINT32                      Length;

+  UINT32               Length;

   ///

   /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages

   /// occurring during FSP execution.

   ///

-  FSP_DEBUG_HANDLER           FspDebugHandler;

-  UINT8                       Reserved1[20];

+  FSP_DEBUG_HANDLER    FspDebugHandler;

+  UINT8                Reserved1[20];

 } FSPT_ARCH_UPD;

 

 ///

@@ -135,55 +135,55 @@ typedef struct {
   ///

   /// Revision of the structure. For FSP v2.0 value is 1.

   ///

-  UINT8                       Revision;

-  UINT8                       Reserved[3];

+  UINT8                Revision;

+  UINT8                Reserved[3];

   ///

   /// Pointer to the non-volatile storage (NVS) data buffer.

   /// If it is NULL it indicates the NVS data is not available.

   ///

-  VOID                        *NvsBufferPtr;

+  VOID                 *NvsBufferPtr;

   ///

   /// Pointer to the temporary stack base address to be

   /// consumed inside FspMemoryInit() API.

   ///

-  VOID                        *StackBase;

+  VOID                 *StackBase;

   ///

   /// Temporary stack size to be consumed inside

   /// FspMemoryInit() API.

   ///

-  UINT32                      StackSize;

+  UINT32               StackSize;

   ///

   /// Size of memory to be reserved by FSP below "top

   /// of low usable memory" for bootloader usage.

   ///

-  UINT32                      BootLoaderTolumSize;

+  UINT32               BootLoaderTolumSize;

   ///

   /// Current boot mode.

   ///

-  UINT32                      BootMode;

+  UINT32               BootMode;

   ///

   /// Optional event handler for the bootloader to be informed of events occurring during FSP execution.

   /// This value is only valid if Revision is >= 2.

   ///

-  FSP_EVENT_HANDLER           *FspEventHandler;

-  UINT8                       Reserved1[4];

+  FSP_EVENT_HANDLER    *FspEventHandler;

+  UINT8                Reserved1[4];

 } FSPM_ARCH_UPD;

 

 typedef struct {

   ///

   /// Revision Revision of the structure is 1 for this version of the specification.

   ///

-  UINT8                      Revision;

-  UINT8                      Reserved[3];

+  UINT8                Revision;

+  UINT8                Reserved[3];

   ///

   /// Length Length of the structure in bytes. The current value for this field is 32.

   ///

-  UINT32                      Length;

+  UINT32               Length;

   ///

   /// FspEventHandler Optional event handler for the bootloader to be informed of events

   /// occurring during FSP execution.

   ///

-  FSP_EVENT_HANDLER           FspEventHandler;

+  FSP_EVENT_HANDLER    FspEventHandler;

   ///

   /// A FSP binary may optionally implement multi-phase silicon initialization,

   /// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER

@@ -191,8 +191,8 @@ typedef struct {
   /// To enable multi-phase silicon initialization, the bootloader must set

   /// EnableMultiPhaseSiliconInit to a non-zero value.

   ///

-  UINT8                       EnableMultiPhaseSiliconInit;

-  UINT8                       Reserved1[19];

+  UINT8                EnableMultiPhaseSiliconInit;

+  UINT8                Reserved1[19];

 } FSPS_ARCH_UPD;

 

 ///

@@ -202,7 +202,7 @@ typedef struct {
   ///

   /// FSP_UPD_HEADER Configuration.

   ///

-  FSP_UPD_HEADER              FspUpdHeader;

+  FSP_UPD_HEADER    FspUpdHeader;

 } FSPT_UPD_COMMON;

 

 ///

@@ -212,12 +212,12 @@ typedef struct {
   ///

   /// FSP_UPD_HEADER Configuration.

   ///

-  FSP_UPD_HEADER              FspUpdHeader;

+  FSP_UPD_HEADER    FspUpdHeader;

 

   ///

   /// FSPT_ARCH_UPD Configuration.

   ///

-  FSPT_ARCH_UPD               FsptArchUpd;

+  FSPT_ARCH_UPD     FsptArchUpd;

 } FSPT_UPD_COMMON_FSP22;

 

 ///

@@ -227,11 +227,11 @@ typedef struct {
   ///

   /// FSP_UPD_HEADER Configuration.

   ///

-  FSP_UPD_HEADER              FspUpdHeader;

+  FSP_UPD_HEADER    FspUpdHeader;

   ///

   /// FSPM_ARCH_UPD Configuration.

   ///

-  FSPM_ARCH_UPD               FspmArchUpd;

+  FSPM_ARCH_UPD     FspmArchUpd;

 } FSPM_UPD_COMMON;

 

 ///

@@ -241,7 +241,7 @@ typedef struct {
   ///

   /// FSP_UPD_HEADER Configuration.

   ///

-  FSP_UPD_HEADER              FspUpdHeader;

+  FSP_UPD_HEADER    FspUpdHeader;

 } FSPS_UPD_COMMON;

 

 ///

@@ -251,12 +251,12 @@ typedef struct {
   ///

   /// FSP_UPD_HEADER Configuration.

   ///

-  FSP_UPD_HEADER              FspUpdHeader;

+  FSP_UPD_HEADER    FspUpdHeader;

 

   ///

   /// FSPS_ARCH_UPD Configuration.

   ///

-  FSPS_ARCH_UPD               FspsArchUpd;

+  FSPS_ARCH_UPD     FspsArchUpd;

 } FSPS_UPD_COMMON_FSP22;

 

 ///

@@ -273,13 +273,13 @@ typedef enum {
   /// This stage is notified just before the bootloader hand-off

   /// to the OS loader.

   ///

-  EnumInitPhaseReadyToBoot         = 0x40,

+  EnumInitPhaseReadyToBoot = 0x40,

   ///

   /// This stage is notified just before the firmware/Preboot

   /// environment transfers management of all system resources

   /// to the OS or next level execution environment.

   ///

-  EnumInitPhaseEndOfFirmware       = 0xF0

+  EnumInitPhaseEndOfFirmware = 0xF0

 } FSP_INIT_PHASE;

 

 ///

@@ -289,15 +289,15 @@ typedef struct {
   ///

   /// Notification phase used for NotifyPhase API

   ///

-  FSP_INIT_PHASE     Phase;

+  FSP_INIT_PHASE    Phase;

 } NOTIFY_PHASE_PARAMS;

 

 ///

 /// Action definition for FspMultiPhaseSiInit API

 ///

 typedef enum {

-  EnumMultiPhaseGetNumberOfPhases  = 0x0,

-  EnumMultiPhaseExecutePhase       = 0x1

+  EnumMultiPhaseGetNumberOfPhases = 0x0,

+  EnumMultiPhaseExecutePhase      = 0x1

 } FSP_MULTI_PHASE_ACTION;

 

 ///

@@ -305,8 +305,8 @@ typedef enum {
 /// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases)

 ///

 typedef struct {

-  UINT32                         NumberOfPhases;

-  UINT32                         PhasesExecuted;

+  UINT32    NumberOfPhases;

+  UINT32    PhasesExecuted;

 } FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS;

 

 ///

@@ -321,9 +321,9 @@ typedef struct {
 ///   - MultiPhaseParamPtr shall be NULL.

 ///

 typedef struct {

-  IN     FSP_MULTI_PHASE_ACTION  MultiPhaseAction;

-  IN     UINT32                  PhaseIndex;

-  IN OUT VOID                    *MultiPhaseParamPtr;

+  IN     FSP_MULTI_PHASE_ACTION    MultiPhaseAction;

+  IN     UINT32                    PhaseIndex;

+  IN OUT VOID                      *MultiPhaseParamPtr;

 } FSP_MULTI_PHASE_PARAMS;

 

 #pragma pack()

@@ -359,7 +359,7 @@ typedef struct {
 **/

 typedef

 EFI_STATUS

-(EFIAPI *FSP_TEMP_RAM_INIT) (

+(EFIAPI *FSP_TEMP_RAM_INIT)(

   IN  VOID    *FsptUpdDataPtr

   );

 

@@ -379,7 +379,7 @@ EFI_STATUS
 **/

 typedef

 EFI_STATUS

-(EFIAPI *FSP_NOTIFY_PHASE) (

+(EFIAPI *FSP_NOTIFY_PHASE)(

   IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr

   );

 

@@ -407,12 +407,11 @@ EFI_STATUS
 **/

 typedef

 EFI_STATUS

-(EFIAPI *FSP_MEMORY_INIT) (

+(EFIAPI *FSP_MEMORY_INIT)(

   IN  VOID    *FspmUpdDataPtr,

   OUT VOID    **HobListPtr

   );

 

-

 /**

   This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary

   memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure

@@ -433,11 +432,10 @@ EFI_STATUS
 **/

 typedef

 EFI_STATUS

-(EFIAPI *FSP_TEMP_RAM_EXIT) (

+(EFIAPI *FSP_TEMP_RAM_EXIT)(

   IN  VOID    *TempRamExitParamPtr

   );

 

-

 /**

   This FSP API is called after TempRamExit API.

   FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the

@@ -454,7 +452,7 @@ EFI_STATUS
 **/

 typedef

 EFI_STATUS

-(EFIAPI *FSP_SILICON_INIT) (

+(EFIAPI *FSP_SILICON_INIT)(

   IN  VOID    *FspsUpdDataPtr

   );

 

@@ -478,8 +476,8 @@ EFI_STATUS
 **/

 typedef

 EFI_STATUS

-(EFIAPI *FSP_MULTI_PHASE_SI_INIT) (

+(EFIAPI *FSP_MULTI_PHASE_SI_INIT)(

   IN FSP_MULTI_PHASE_PARAMS     *MultiPhaseSiInitParamPtr

-);

+  );

 

 #endif

diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/FspGlobalData.h
index dba9b48e1a..71033121c4 100644
--- a/IntelFsp2Pkg/Include/FspGlobalData.h
+++ b/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -10,8 +10,8 @@
 

 #include <FspEas.h>

 

-#define FSP_IN_API_MODE      0

-#define FSP_IN_DISPATCH_MODE 1

+#define FSP_IN_API_MODE       0

+#define FSP_IN_DISPATCH_MODE  1

 

 #pragma pack(1)

 

@@ -27,50 +27,50 @@ typedef enum {
 } FSP_API_INDEX;

 

 typedef struct  {

-   VOID               *DataPtr;

-   UINT32             MicrocodeRegionBase;

-   UINT32             MicrocodeRegionSize;

-   UINT32             CodeRegionBase;

-   UINT32             CodeRegionSize;

+  VOID      *DataPtr;

+  UINT32    MicrocodeRegionBase;

+  UINT32    MicrocodeRegionSize;

+  UINT32    CodeRegionBase;

+  UINT32    CodeRegionSize;

 } FSP_PLAT_DATA;

 

-#define FSP_GLOBAL_DATA_SIGNATURE  SIGNATURE_32 ('F', 'S', 'P', 'D')

-#define FSP_PERFORMANCE_DATA_SIGNATURE  SIGNATURE_32 ('P', 'E', 'R', 'F')

-#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF

+#define FSP_GLOBAL_DATA_SIGNATURE        SIGNATURE_32 ('F', 'S', 'P', 'D')

+#define FSP_PERFORMANCE_DATA_SIGNATURE   SIGNATURE_32 ('P', 'E', 'R', 'F')

+#define FSP_PERFORMANCE_DATA_TIMER_MASK  0xFFFFFFFFFFFFFF

 

 typedef struct  {

-   UINT32             Signature;

-   UINT8              Version;

-   UINT8              Reserved1[3];

-   UINT32             CoreStack;

-   UINT32             StatusCode;

-   UINT32             Reserved2[8];

-   FSP_PLAT_DATA      PlatformData;

-   FSP_INFO_HEADER    *FspInfoHeader;

-   VOID               *UpdDataPtr;

-   VOID               *TempRamInitUpdPtr;

-   VOID               *MemoryInitUpdPtr;

-   VOID               *SiliconInitUpdPtr;

-   UINT8              ApiIdx;

-   ///

-   /// 0: FSP in API mode; 1: FSP in DISPATCH mode

-   ///

-   UINT8              FspMode;

-   UINT8              OnSeparateStack;

-   UINT8              Reserved3;

-   UINT32             NumberOfPhases;

-   UINT32             PhasesExecuted;

-   ///

-   /// To store function parameters pointer

-   /// so it can be retrieved after stack switched.

-   ///

-   VOID               *FunctionParameterPtr;

-   UINT8              Reserved4[16];

-   UINT32             PerfSig;

-   UINT16             PerfLen;

-   UINT16             Reserved5;

-   UINT32             PerfIdx;

-   UINT64             PerfData[32];

+  UINT32             Signature;

+  UINT8              Version;

+  UINT8              Reserved1[3];

+  UINT32             CoreStack;

+  UINT32             StatusCode;

+  UINT32             Reserved2[8];

+  FSP_PLAT_DATA      PlatformData;

+  FSP_INFO_HEADER    *FspInfoHeader;

+  VOID               *UpdDataPtr;

+  VOID               *TempRamInitUpdPtr;

+  VOID               *MemoryInitUpdPtr;

+  VOID               *SiliconInitUpdPtr;

+  UINT8              ApiIdx;

+  ///

+  /// 0: FSP in API mode; 1: FSP in DISPATCH mode

+  ///

+  UINT8              FspMode;

+  UINT8              OnSeparateStack;

+  UINT8              Reserved3;

+  UINT32             NumberOfPhases;

+  UINT32             PhasesExecuted;

+  ///

+  /// To store function parameters pointer

+  /// so it can be retrieved after stack switched.

+  ///

+  VOID               *FunctionParameterPtr;

+  UINT8              Reserved4[16];

+  UINT32             PerfSig;

+  UINT16             PerfLen;

+  UINT16             Reserved5;

+  UINT32             PerfIdx;

+  UINT64             PerfData[32];

 } FSP_GLOBAL_DATA;

 

 #pragma pack()

diff --git a/IntelFsp2Pkg/Include/FspMeasurePointId.h b/IntelFsp2Pkg/Include/FspMeasurePointId.h
index 3535210fc5..00dabca243 100644
--- a/IntelFsp2Pkg/Include/FspMeasurePointId.h
+++ b/IntelFsp2Pkg/Include/FspMeasurePointId.h
@@ -11,44 +11,44 @@
 //

 // 0xD0 - 0xEF are reserved for FSP common measure point

 //

-#define  FSP_PERF_ID_MRC_INIT_ENTRY               0xD0

-#define  FSP_PERF_ID_MRC_INIT_EXIT                (FSP_PERF_ID_MRC_INIT_ENTRY +  1)

+#define  FSP_PERF_ID_MRC_INIT_ENTRY  0xD0

+#define  FSP_PERF_ID_MRC_INIT_EXIT   (FSP_PERF_ID_MRC_INIT_ENTRY +  1)

 

-#define  FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY      0xD8

-#define  FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT       (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY +  1)

+#define  FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY  0xD8

+#define  FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT   (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY +  1)

 

-#define  FSP_PERF_ID_PCH_INIT_ENTRY               0xDA

-#define  FSP_PERF_ID_PCH_INIT_EXIT                (FSP_PERF_ID_PCH_INIT_ENTRY +  1)

+#define  FSP_PERF_ID_PCH_INIT_ENTRY  0xDA

+#define  FSP_PERF_ID_PCH_INIT_EXIT   (FSP_PERF_ID_PCH_INIT_ENTRY +  1)

 

-#define  FSP_PERF_ID_CPU_INIT_ENTRY               0xE0

-#define  FSP_PERF_ID_CPU_INIT_EXIT                (FSP_PERF_ID_CPU_INIT_ENTRY +  1)

+#define  FSP_PERF_ID_CPU_INIT_ENTRY  0xE0

+#define  FSP_PERF_ID_CPU_INIT_EXIT   (FSP_PERF_ID_CPU_INIT_ENTRY +  1)

 

-#define  FSP_PERF_ID_GFX_INIT_ENTRY               0xE8

-#define  FSP_PERF_ID_GFX_INIT_EXIT                (FSP_PERF_ID_GFX_INIT_ENTRY +  1)

+#define  FSP_PERF_ID_GFX_INIT_ENTRY  0xE8

+#define  FSP_PERF_ID_GFX_INIT_EXIT   (FSP_PERF_ID_GFX_INIT_ENTRY +  1)

 

-#define  FSP_PERF_ID_ME_INIT_ENTRY                0xEA

-#define  FSP_PERF_ID_ME_INIT_EXIT                 (FSP_PERF_ID_ME_INIT_ENTRY +  1)

+#define  FSP_PERF_ID_ME_INIT_ENTRY  0xEA

+#define  FSP_PERF_ID_ME_INIT_EXIT   (FSP_PERF_ID_ME_INIT_ENTRY +  1)

 

 //

 // 0xF0 - 0xFF are reserved for FSP API

 //

-#define  FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY           0xF0

-#define  FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT            (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1)

+#define  FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY  0xF0

+#define  FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT   (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1)

 

-#define  FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY         0xF2

-#define  FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT          (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1)

+#define  FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY  0xF2

+#define  FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT   (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1)

 

-#define  FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY           0xF4

-#define  FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT            (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1)

+#define  FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY  0xF4

+#define  FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT   (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1)

 

-#define  FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY        0xF6

-#define  FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT         (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1)

+#define  FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY  0xF6

+#define  FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT   (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1)

 

-#define  FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY         0xF8

-#define  FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT          (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1)

+#define  FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY  0xF8

+#define  FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT   (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1)

 

-#define  FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY    0xFA

-#define  FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT     (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1)

+#define  FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY  0xFA

+#define  FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT   (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1)

 

 #define  FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY  0xFC

 #define  FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_EXIT   (FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY + 1)

diff --git a/IntelFsp2Pkg/Include/FspStatusCode.h b/IntelFsp2Pkg/Include/FspStatusCode.h
index c891b67849..e294aa3435 100644
--- a/IntelFsp2Pkg/Include/FspStatusCode.h
+++ b/IntelFsp2Pkg/Include/FspStatusCode.h
@@ -12,29 +12,29 @@
 //

 // FSP API - 4 BITS

 //

-#define FSP_STATUS_CODE_TEMP_RAM_INIT                0xF000

-#define FSP_STATUS_CODE_MEMORY_INIT                  0xD000

-#define FSP_STATUS_CODE_TEMP_RAM_EXIT                0xB000

-#define FSP_STATUS_CODE_SILICON_INIT                 0x9000

-#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION  0x6000

-#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION   0x4000

-#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION 0x2000

+#define FSP_STATUS_CODE_TEMP_RAM_INIT                 0xF000

+#define FSP_STATUS_CODE_MEMORY_INIT                   0xD000

+#define FSP_STATUS_CODE_TEMP_RAM_EXIT                 0xB000

+#define FSP_STATUS_CODE_SILICON_INIT                  0x9000

+#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION   0x6000

+#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION    0x4000

+#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION  0x2000

 

 //

 // MODULE - 4 BITS

 //

-#define FSP_STATUS_CODE_GFX_PEIM                     0x0700

-#define FSP_STATUS_CODE_COMMON_CODE                  0x0800

-#define FSP_STATUS_CODE_SILICON_COMMON_CODE          0x0900

-#define FSP_STATUS_CODE_SYSTEM_AGENT                 0x0A00

-#define FSP_STATUS_CODE_PCH                          0x0B00

-#define FSP_STATUS_CODE_CPU                          0x0C00

-#define FSP_STATUS_CODE_MRC                          0x0D00

-#define FSP_STATUS_CODE_ME_BIOS                      0x0E00

+#define FSP_STATUS_CODE_GFX_PEIM             0x0700

+#define FSP_STATUS_CODE_COMMON_CODE          0x0800

+#define FSP_STATUS_CODE_SILICON_COMMON_CODE  0x0900

+#define FSP_STATUS_CODE_SYSTEM_AGENT         0x0A00

+#define FSP_STATUS_CODE_PCH                  0x0B00

+#define FSP_STATUS_CODE_CPU                  0x0C00

+#define FSP_STATUS_CODE_MRC                  0x0D00

+#define FSP_STATUS_CODE_ME_BIOS              0x0E00

 //

 // Individual Codes - 1 BYTE

 //

-#define FSP_STATUS_CODE_API_ENTRY                    0x0000

-#define FSP_STATUS_CODE_API_EXIT                     0x007F

+#define FSP_STATUS_CODE_API_ENTRY  0x0000

+#define FSP_STATUS_CODE_API_EXIT   0x007F

 

 #endif

diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
index 11e0ede65b..e5a9d7a2b4 100644
--- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
+++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
@@ -10,7 +10,7 @@
 #ifndef __FSP_HEADER_FILE_H__

 #define __FSP_HEADER_FILE_H__

 

-#define FSP_HEADER_REVISION_3   3

+#define FSP_HEADER_REVISION_3  3

 

 #define FSPE_HEADER_REVISION_1  1

 #define FSPP_HEADER_REVISION_1  1

@@ -18,7 +18,7 @@
 ///

 /// Fixed FSP header offset in the FSP image

 ///

-#define FSP_INFO_HEADER_OFF    0x94

+#define FSP_INFO_HEADER_OFF  0x94

 

 #define OFFSET_IN_FSP_INFO_HEADER(x)  (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x

 

@@ -33,25 +33,25 @@ typedef struct {
   ///

   /// Byte 0x00: Signature ('FSPH') for the FSP Information Header.

   ///

-  UINT32  Signature;

+  UINT32    Signature;

   ///

   /// Byte 0x04: Length of the FSP Information Header.

   ///

-  UINT32  HeaderLength;

+  UINT32    HeaderLength;

   ///

   /// Byte 0x08: Reserved.

   ///

-  UINT8   Reserved1[2];

+  UINT8     Reserved1[2];

   ///

   /// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.

   ///            For revision v2.3 the value will be 0x23.

   ///

-  UINT8   SpecVersion;

+  UINT8     SpecVersion;

   ///

   /// Byte 0x0B: Revision of the FSP Information Header.

   ///            The Current value for this field is 0x6.

   ///

-  UINT8   HeaderRevision;

+  UINT8     HeaderRevision;

   ///

   /// Byte 0x0C: Revision of the FSP binary.

   ///            Major.Minor.Revision.Build

@@ -67,69 +67,69 @@ typedef struct {
   ///              23 : 16 - Minor Version

   ///              31 : 24 - Major Version

   ///

-  UINT32  ImageRevision;

+  UINT32    ImageRevision;

   ///

   /// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration.

   ///

-  CHAR8   ImageId[8];

+  CHAR8     ImageId[8];

   ///

   /// Byte 0x18: Size of the entire FSP binary.

   ///

-  UINT32  ImageSize;

+  UINT32    ImageSize;

   ///

   /// Byte 0x1C: FSP binary preferred base address.

   ///

-  UINT32  ImageBase;

+  UINT32    ImageBase;

   ///

   /// Byte 0x20: Attribute for the FSP binary.

   ///

-  UINT16  ImageAttribute;

+  UINT16    ImageAttribute;

   ///

   /// Byte 0x22: Attributes of the FSP Component.

   ///

-  UINT16  ComponentAttribute;

+  UINT16    ComponentAttribute;

   ///

   /// Byte 0x24: Offset of the FSP configuration region.

   ///

-  UINT32  CfgRegionOffset;

+  UINT32    CfgRegionOffset;

   ///

   /// Byte 0x28: Size of the FSP configuration region.

   ///

-  UINT32  CfgRegionSize;

+  UINT32    CfgRegionSize;

   ///

   /// Byte 0x2C: Reserved2.

   ///

-  UINT32  Reserved2;

+  UINT32    Reserved2;

   ///

   /// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized.

   ///

-  UINT32  TempRamInitEntryOffset;

+  UINT32    TempRamInitEntryOffset;

   ///

   /// Byte 0x34: Reserved3.

   ///

-  UINT32  Reserved3;

+  UINT32    Reserved3;

   ///

   /// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process.

   ///

-  UINT32  NotifyPhaseEntryOffset;

+  UINT32    NotifyPhaseEntryOffset;

   ///

   /// Byte 0x3C: The offset for the API to initialize the memory.

   ///

-  UINT32  FspMemoryInitEntryOffset;

+  UINT32    FspMemoryInitEntryOffset;

   ///

   /// Byte 0x40: The offset for the API to tear down temporary RAM.

   ///

-  UINT32  TempRamExitEntryOffset;

+  UINT32    TempRamExitEntryOffset;

   ///

   /// Byte 0x44: The offset for the API to initialize the CPU and chipset.

   ///

-  UINT32  FspSiliconInitEntryOffset;

+  UINT32    FspSiliconInitEntryOffset;

   ///

   /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.

   ///            This value is only valid if FSP HeaderRevision is >= 5.

   ///            If the value is set to 0x00000000, then this API is not available in this component.

   ///

-  UINT32  FspMultiPhaseSiInitEntryOffset;

+  UINT32    FspMultiPhaseSiInitEntryOffset;

   ///

   /// Byte 0x4C: Extended revision of the FSP binary.

   ///            This value is only valid if FSP HeaderRevision is >= 6.

@@ -142,11 +142,11 @@ typedef struct {
   ///            Minor Version = ImageRevision[23:16]

   ///            Major Version = ImageRevision[31:24]

   ///

-  UINT16  ExtendedImageRevision;

+  UINT16    ExtendedImageRevision;

   ///

   /// Byte 0x4E: Reserved4.

   ///

-  UINT16  Reserved4;

+  UINT16    Reserved4;

 } FSP_INFO_HEADER;

 

 ///

@@ -161,31 +161,31 @@ typedef struct {
   ///

   /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header.

   ///

-  UINT32  Signature;

+  UINT32    Signature;

   ///

   /// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.

   ///

-  UINT32  Length;

+  UINT32    Length;

   ///

   /// Byte 0x08: FSP producer defined revision of the table.

   ///

-  UINT8   Revision;

+  UINT8     Revision;

   ///

   /// Byte 0x09: Reserved for future use.

   ///

-  UINT8   Reserved;

+  UINT8     Reserved;

   ///

   /// Byte 0x0A: FSP producer identification string

   ///

-  CHAR8   FspProducerId[6];

+  CHAR8     FspProducerId[6];

   ///

   /// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.

   ///

-  UINT32  FspProducerRevision;

+  UINT32    FspProducerRevision;

   ///

   /// Byte 0x14: Size of the FSP producer defined data (n) in bytes.

   ///

-  UINT32  FspProducerDataSize;

+  UINT32    FspProducerDataSize;

   ///

   /// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.

   ///

@@ -195,7 +195,7 @@ typedef struct {
 // A generic table search algorithm for additional tables can be implemented with a

 // signature search algorithm until a terminator signature 'FSPP' is found.

 //

-#define FSP_FSPP_SIGNATURE  SIGNATURE_32 ('F', 'S', 'P', 'P')

+#define FSP_FSPP_SIGNATURE         SIGNATURE_32 ('F', 'S', 'P', 'P')

 #define FSP_PATCH_TABLE_SIGNATURE  FSP_FSPP_SIGNATURE

 

 ///

@@ -205,31 +205,31 @@ typedef struct {
   ///

   /// Byte 0x00: FSP Patch Table Signature "FSPP".

   ///

-  UINT32  Signature;

+  UINT32    Signature;

   ///

   /// Byte 0x04: Size including the PatchData.

   ///

-  UINT16  HeaderLength;

+  UINT16    HeaderLength;

   ///

   /// Byte 0x06: Revision is set to 0x01.

   ///

-  UINT8   HeaderRevision;

+  UINT8     HeaderRevision;

   ///

   /// Byte 0x07: Reserved for future use.

   ///

-  UINT8   Reserved;

+  UINT8     Reserved;

   ///

   /// Byte 0x08: Number of entries to Patch.

   ///

-  UINT32  PatchEntryNum;

+  UINT32    PatchEntryNum;

   ///

   /// Byte 0x0C: Patch Data.

   ///

-//UINT32  PatchData[];

+  // UINT32  PatchData[];

 } FSP_PATCH_TABLE;

 

 #pragma pack()

 

-extern EFI_GUID gFspHeaderFileGuid;

+extern EFI_GUID  gFspHeaderFileGuid;

 

 #endif

diff --git a/IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h b/IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h
index 1246108b96..71748a13d4 100644
--- a/IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h
+++ b/IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h
@@ -14,11 +14,11 @@
 /// The Non-Volatile Storage (NVS) HOB version 2 provides > 64KB buffer support.

 ///

 typedef struct {

-  EFI_HOB_GUID_TYPE    GuidHob;

-  EFI_PHYSICAL_ADDRESS NvsDataPtr;

-  UINT64               NvsDataLength;

+  EFI_HOB_GUID_TYPE       GuidHob;

+  EFI_PHYSICAL_ADDRESS    NvsDataPtr;

+  UINT64                  NvsDataLength;

 } FSP_NON_VOLATILE_STORAGE_HOB2;

 

-extern EFI_GUID gFspNonVolatileStorageHob2Guid;

+extern EFI_GUID  gFspNonVolatileStorageHob2Guid;

 

 #endif

diff --git a/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h b/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h
index 28cd5ddca5..150d6b842a 100644
--- a/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h
+++ b/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h
@@ -10,8 +10,8 @@
 #ifndef __GUID_HOB_FSP_EAS_GUID__

 #define __GUID_HOB_FSP_EAS_GUID__

 

-extern EFI_GUID gFspBootLoaderTolumHobGuid;

-extern EFI_GUID gFspReservedMemoryResourceHobGuid;

-extern EFI_GUID gFspNonVolatileStorageHobGuid;

+extern EFI_GUID  gFspBootLoaderTolumHobGuid;

+extern EFI_GUID  gFspReservedMemoryResourceHobGuid;

+extern EFI_GUID  gFspNonVolatileStorageHobGuid;

 

 #endif

diff --git a/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h b/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h
index 4a517ba2b5..e9de86717d 100644
--- a/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h
+++ b/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h
@@ -17,8 +17,7 @@
 VOID

 EFIAPI

 DisableCacheAsRam (

-  IN BOOLEAN                   DisableCar

+  IN BOOLEAN  DisableCar

   );

 

 #endif

-

diff --git a/IntelFsp2Pkg/Include/Library/CacheLib.h b/IntelFsp2Pkg/Include/Library/CacheLib.h
index 4caf6401f4..82b6d5d323 100644
--- a/IntelFsp2Pkg/Include/Library/CacheLib.h
+++ b/IntelFsp2Pkg/Include/Library/CacheLib.h
@@ -13,11 +13,11 @@
 //

 typedef INT32 EFI_MEMORY_CACHE_TYPE;

 

-#define EFI_CACHE_UNCACHEABLE                 0

-#define EFI_CACHE_WRITECOMBINING              1

-#define EFI_CACHE_WRITETHROUGH                4

-#define EFI_CACHE_WRITEPROTECTED              5

-#define EFI_CACHE_WRITEBACK                   6

+#define EFI_CACHE_UNCACHEABLE     0

+#define EFI_CACHE_WRITECOMBINING  1

+#define EFI_CACHE_WRITETHROUGH    4

+#define EFI_CACHE_WRITEPROTECTED  5

+#define EFI_CACHE_WRITEBACK       6

 

 /**

  Reset all the MTRRs to a known state.

@@ -47,10 +47,9 @@ ResetCacheAttributes (
 EFI_STATUS

 EFIAPI

 SetCacheAttributes (

-  IN  EFI_PHYSICAL_ADDRESS      MemoryAddress,

-  IN  UINT64                    MemoryLength,

-  IN  EFI_MEMORY_CACHE_TYPE     MemoryCacheType

+  IN  EFI_PHYSICAL_ADDRESS   MemoryAddress,

+  IN  UINT64                 MemoryLength,

+  IN  EFI_MEMORY_CACHE_TYPE  MemoryCacheType

   );

 

 #endif

-

diff --git a/IntelFsp2Pkg/Include/Library/FspCommonLib.h b/IntelFsp2Pkg/Include/Library/FspCommonLib.h
index 197b10b42f..c70039d9e8 100644
--- a/IntelFsp2Pkg/Include/Library/FspCommonLib.h
+++ b/IntelFsp2Pkg/Include/Library/FspCommonLib.h
@@ -20,7 +20,7 @@
 VOID

 EFIAPI

 SetFspGlobalDataPointer (

-  IN FSP_GLOBAL_DATA   *FspData

+  IN FSP_GLOBAL_DATA  *FspData

   );

 

 /**

@@ -60,7 +60,7 @@ GetFspApiParameter2 (
 

   @retval FSP entry stack pointer.

 **/

-VOID*

+VOID *

 EFIAPI

 GetFspEntryStack (

   VOID

@@ -75,7 +75,7 @@ GetFspEntryStack (
 VOID

 EFIAPI

 SetFspApiParameter (

-  IN UINT32      Value

+  IN UINT32  Value

   );

 

 /**

@@ -99,7 +99,7 @@ SetFspApiReturnStatus (
 VOID

 EFIAPI

 SetFspCoreStackPointer (

-  IN VOID   *NewStackTop

+  IN VOID  *NewStackTop

   );

 

 /**

@@ -111,7 +111,7 @@ SetFspCoreStackPointer (
 VOID

 EFIAPI

 SetFspPlatformDataPointer (

-  IN VOID   *PlatformData

+  IN VOID  *PlatformData

   );

 

 /**

@@ -134,7 +134,7 @@ GetFspPlatformDataPointer (
 VOID

 EFIAPI

 SetFspUpdDataPointer (

-  IN VOID    *UpdDataPtr

+  IN VOID  *UpdDataPtr

   );

 

 /**

@@ -156,7 +156,7 @@ GetFspUpdDataPointer (
 VOID

 EFIAPI

 SetFspMemoryInitUpdDataPointer (

-  IN VOID    *MemoryInitUpdPtr

+  IN VOID  *MemoryInitUpdPtr

   );

 

 /**

@@ -178,7 +178,7 @@ GetFspMemoryInitUpdDataPointer (
 VOID

 EFIAPI

 SetFspSiliconInitUpdDataPointer (

-  IN VOID    *SiliconInitUpdPtr

+  IN VOID  *SiliconInitUpdPtr

   );

 

 /**

@@ -224,7 +224,7 @@ GetFspInfoHeader (
 VOID

 EFIAPI

 SetFspInfoHeader (

-  FSP_INFO_HEADER *FspInfoHeader

+  FSP_INFO_HEADER  *FspInfoHeader

   );

 

 /**

@@ -282,7 +282,6 @@ GetPhaseStatusCode (
   VOID

   );

 

-

 /**

   This function sets FSP Phase StatusCode.

 

@@ -303,6 +302,7 @@ SetPhaseStatusCode (
 VOID

 EFIAPI

 FspApiReturnStatusReset (

-  IN UINT32   FspResetType

+  IN UINT32  FspResetType

   );

+

 #endif

diff --git a/IntelFsp2Pkg/Include/Library/FspPlatformLib.h b/IntelFsp2Pkg/Include/Library/FspPlatformLib.h
index 8e7a9a8041..081add6529 100644
--- a/IntelFsp2Pkg/Include/Library/FspPlatformLib.h
+++ b/IntelFsp2Pkg/Include/Library/FspPlatformLib.h
@@ -16,7 +16,7 @@
 EFI_HOB_RESOURCE_DESCRIPTOR *

 EFIAPI

 FspGetResourceDescriptorByOwner (

-  IN EFI_GUID   *OwnerGuid

+  IN EFI_GUID  *OwnerGuid

   );

 

 /**

@@ -28,11 +28,10 @@ FspGetResourceDescriptorByOwner (
 VOID

 EFIAPI

 FspGetSystemMemorySize (

-  IN OUT UINT64              *LowMemoryLength,

-  IN OUT UINT64              *HighMemoryLength

+  IN OUT UINT64  *LowMemoryLength,

+  IN OUT UINT64  *HighMemoryLength

   );

 

-

 /**

   Set a new stack frame for the continuation function.

 

@@ -61,7 +60,7 @@ FspSiliconInitDone (
 VOID

 EFIAPI

 FspMemoryInitDone (

-  IN OUT VOID   **HobListPtr

+  IN OUT VOID  **HobListPtr

   );

 

 /**

@@ -95,7 +94,7 @@ FspWaitForNotify (
 VOID

 EFIAPI

 FspSiliconInitDone2 (

-  IN EFI_STATUS Status

+  IN EFI_STATUS  Status

   );

 

 /**

@@ -107,8 +106,8 @@ FspSiliconInitDone2 (
 VOID

 EFIAPI

 FspMemoryInitDone2 (

-  IN EFI_STATUS Status,

-  IN OUT VOID   **HobListPtr

+  IN EFI_STATUS  Status,

+  IN OUT VOID    **HobListPtr

   );

 

 /**

@@ -119,7 +118,7 @@ FspMemoryInitDone2 (
 VOID

 EFIAPI

 FspTempRamExitDone2 (

-  IN EFI_STATUS Status

+  IN EFI_STATUS  Status

   );

 

 #endif

diff --git a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h
index 51a0309aed..920115e90e 100644
--- a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h
+++ b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h
@@ -43,7 +43,7 @@ SecPlatformInit (
 UINT32

 EFIAPI

 LoadMicrocode (

-  IN  VOID    *FsptUpdDataPtr

+  IN  VOID  *FsptUpdDataPtr

   );

 

 /**

@@ -62,7 +62,7 @@ LoadMicrocode (
 UINT32

 EFIAPI

 SecCarInit (

-  IN  VOID    *FsptUpdDataPtr

+  IN  VOID  *FsptUpdDataPtr

   );

 

 /**

@@ -75,8 +75,8 @@ SecCarInit (
 EFI_STATUS

 EFIAPI

 FspUpdSignatureCheck (

-  IN UINT32   ApiIdx,

-  IN VOID     *ApiParam

+  IN UINT32  ApiIdx,

+  IN VOID    *ApiParam

   );

 

 /**

@@ -89,8 +89,8 @@ FspUpdSignatureCheck (
 EFI_STATUS

 EFIAPI

 FspMultiPhaseSiInitApiHandler (

-  IN UINT32   ApiIdx,

-  IN VOID     *ApiParam

+  IN UINT32  ApiIdx,

+  IN VOID    *ApiParam

   );

 

 #endif

diff --git a/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
index 7709096890..2559627c65 100644
--- a/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
+++ b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
@@ -10,7 +10,7 @@
 #ifndef _FSPM_ARCH_CONFIG_PPI_H_

 #define _FSPM_ARCH_CONFIG_PPI_H_

 

-#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1

+#define FSPM_ARCH_CONFIG_PPI_REVISION  0x1

 

 ///

 /// Global ID for the FSPM_ARCH_CONFIG_PPI.

@@ -27,21 +27,21 @@ typedef struct {
   ///

   /// Revision of the structure

   ///

-  UINT8         Revision;

-  UINT8         Reserved[3];

+  UINT8     Revision;

+  UINT8     Reserved[3];

   ///

   /// Pointer to the non-volatile storage (NVS) data buffer.

   /// If it is NULL it indicates the NVS data is not available.

   ///

-  VOID          *NvsBufferPtr;

+  VOID      *NvsBufferPtr;

   ///

   /// Size of memory to be reserved by FSP below "top

   /// of low usable memory" for bootloader usage.

   ///

-  UINT32        BootLoaderTolumSize;

-  UINT8         Reserved1[4];

+  UINT32    BootLoaderTolumSize;

+  UINT8     Reserved1[4];

 } FSPM_ARCH_CONFIG_PPI;

 

-extern EFI_GUID gFspmArchConfigPpiGuid;

+extern EFI_GUID  gFspmArchConfigPpiGuid;

 

 #endif // _FSPM_ARCH_CONFIG_PPI_H_

diff --git a/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h b/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
index 0db54dfa45..b497e33c5b 100644
--- a/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
+++ b/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
@@ -36,7 +36,7 @@ typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI;
 **/

 typedef

 EFI_STATUS

-(EFIAPI *FSP_TEMP_RAM_EXIT) (

+(EFIAPI *FSP_TEMP_RAM_EXIT)(

   IN  VOID    *TempRamExitParamPtr

   );

 

@@ -44,9 +44,9 @@ EFI_STATUS
 /// This PPI provides function to disable temporary memory.

 ///

 struct _FSP_TEMP_RAM_EXIT_PPI {

-  FSP_TEMP_RAM_EXIT   TempRamExit;

+  FSP_TEMP_RAM_EXIT    TempRamExit;

 };

 

-extern EFI_GUID gFspTempRamExitPpiGuid;

+extern EFI_GUID  gFspTempRamExitPpiGuid;

 

 #endif // _FSP_TEMP_RAM_EXIT_PPI_H_

diff --git a/IntelFsp2Pkg/Library/BaseCacheAsRamLibNull/DisableCacheAsRamNull.c b/IntelFsp2Pkg/Library/BaseCacheAsRamLibNull/DisableCacheAsRamNull.c
index 78abb6d5d0..bf1422c5d0 100644
--- a/IntelFsp2Pkg/Library/BaseCacheAsRamLibNull/DisableCacheAsRamNull.c
+++ b/IntelFsp2Pkg/Library/BaseCacheAsRamLibNull/DisableCacheAsRamNull.c
@@ -18,7 +18,7 @@
 VOID

 EFIAPI

 DisableCacheAsRam (

-  IN BOOLEAN                   DisableCar

+  IN BOOLEAN  DisableCar

   )

 {

   //

@@ -28,8 +28,8 @@ DisableCacheAsRam (
   if (DisableCar) {

     AsmInvd ();

   } else {

-    AsmWbinvd();

+    AsmWbinvd ();

   }

 

-  return ;

+  return;

 }

diff --git a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
index 2365f7514e..f879c268e7 100644
--- a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
+++ b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
@@ -26,11 +26,11 @@
 **/

 EFI_STATUS

 SearchForExactMtrr (

-  IN  EFI_PHYSICAL_ADDRESS      MemoryAddress,

-  IN  UINT64                    MemoryLength,

-  IN  UINT64                    ValidMtrrAddressMask,

-  OUT UINT32                    *UsedMsrNum,

-  OUT EFI_MEMORY_CACHE_TYPE     *MemoryCacheType

+  IN  EFI_PHYSICAL_ADDRESS   MemoryAddress,

+  IN  UINT64                 MemoryLength,

+  IN  UINT64                 ValidMtrrAddressMask,

+  OUT UINT32                 *UsedMsrNum,

+  OUT EFI_MEMORY_CACHE_TYPE  *MemoryCacheType

   );

 

 /**

@@ -43,7 +43,7 @@ SearchForExactMtrr (
 **/

 BOOLEAN

 IsDefaultType (

-  IN  EFI_MEMORY_CACHE_TYPE     MemoryCacheType

+  IN  EFI_MEMORY_CACHE_TYPE  MemoryCacheType

   );

 

 /**

@@ -58,8 +58,8 @@ IsDefaultType (
 **/

 UINT32

 CheckMtrrAlignment (

-  IN  UINT64                    BaseAddress,

-  IN  UINT64                    Size

+  IN  UINT64  BaseAddress,

+  IN  UINT64  Size

   );

 

 typedef struct {

@@ -68,18 +68,18 @@ typedef struct {
   UINT32    Length;

 } EFI_FIXED_MTRR;

 

-EFI_FIXED_MTRR mFixedMtrrTable[] = {

-  { EFI_MSR_IA32_MTRR_FIX64K_00000, 0,       0x10000},

-  { EFI_MSR_IA32_MTRR_FIX16K_80000, 0x80000, 0x4000},

-  { EFI_MSR_IA32_MTRR_FIX16K_A0000, 0xA0000, 0x4000},

-  { EFI_MSR_IA32_MTRR_FIX4K_C0000,  0xC0000, 0x1000},

-  { EFI_MSR_IA32_MTRR_FIX4K_C8000,  0xC8000, 0x1000},

-  { EFI_MSR_IA32_MTRR_FIX4K_D0000,  0xD0000, 0x1000},

-  { EFI_MSR_IA32_MTRR_FIX4K_D8000,  0xD8000, 0x1000},

-  { EFI_MSR_IA32_MTRR_FIX4K_E0000,  0xE0000, 0x1000},

-  { EFI_MSR_IA32_MTRR_FIX4K_E8000,  0xE8000, 0x1000},

-  { EFI_MSR_IA32_MTRR_FIX4K_F0000,  0xF0000, 0x1000},

-  { EFI_MSR_IA32_MTRR_FIX4K_F8000,  0xF8000, 0x1000}

+EFI_FIXED_MTRR  mFixedMtrrTable[] = {

+  { EFI_MSR_IA32_MTRR_FIX64K_00000, 0,       0x10000 },

+  { EFI_MSR_IA32_MTRR_FIX16K_80000, 0x80000, 0x4000  },

+  { EFI_MSR_IA32_MTRR_FIX16K_A0000, 0xA0000, 0x4000  },

+  { EFI_MSR_IA32_MTRR_FIX4K_C0000,  0xC0000, 0x1000  },

+  { EFI_MSR_IA32_MTRR_FIX4K_C8000,  0xC8000, 0x1000  },

+  { EFI_MSR_IA32_MTRR_FIX4K_D0000,  0xD0000, 0x1000  },

+  { EFI_MSR_IA32_MTRR_FIX4K_D8000,  0xD8000, 0x1000  },

+  { EFI_MSR_IA32_MTRR_FIX4K_E0000,  0xE0000, 0x1000  },

+  { EFI_MSR_IA32_MTRR_FIX4K_E8000,  0xE8000, 0x1000  },

+  { EFI_MSR_IA32_MTRR_FIX4K_F0000,  0xF0000, 0x1000  },

+  { EFI_MSR_IA32_MTRR_FIX4K_F8000,  0xF8000, 0x1000  }

 };

 

 /**

@@ -94,7 +94,7 @@ EFI_FIXED_MTRR mFixedMtrrTable[] = {
 **/

 INT8

 CheckDirection (

-  IN  UINT64                    Input

+  IN  UINT64  Input

   )

 {

   return 0;

@@ -108,7 +108,7 @@ CheckDirection (
 **/

 VOID

 EfiDisableCacheMtrr (

-  OUT UINT64                   *OldMtrr

+  OUT UINT64  *OldMtrr

   )

 {

   UINT64  TempQword;

@@ -116,9 +116,9 @@ EfiDisableCacheMtrr (
   //

   // Disable Cache MTRR

   //

-  *OldMtrr = AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);

+  *OldMtrr  = AsmReadMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);

   TempQword = (*OldMtrr) & ~B_EFI_MSR_GLOBAL_MTRR_ENABLE & ~B_EFI_MSR_FIXED_MTRR_ENABLE;

-  AsmWriteMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, TempQword);

+  AsmWriteMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, TempQword);

   AsmDisableCache ();

 }

 

@@ -131,8 +131,8 @@ EfiDisableCacheMtrr (
 **/

 VOID

 EfiRecoverCacheMtrr (

-  IN BOOLEAN                  EnableMtrr,

-  IN UINT64                   OldMtrr

+  IN BOOLEAN  EnableMtrr,

+  IN UINT64   OldMtrr

   )

 {

   UINT64  TempQword;

@@ -141,7 +141,7 @@ EfiRecoverCacheMtrr (
   // Enable Cache MTRR

   //

   if (EnableMtrr) {

-    TempQword = AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);

+    TempQword  = AsmReadMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);

     TempQword |= (UINT64)(B_EFI_MSR_GLOBAL_MTRR_ENABLE | B_EFI_MSR_FIXED_MTRR_ENABLE);

   } else {

     TempQword = OldMtrr;

@@ -164,15 +164,15 @@ EfiRecoverCacheMtrr (
 **/

 VOID

 EfiProgramMtrr (

-  IN  UINT32                    MtrrNumber,

-  IN  EFI_PHYSICAL_ADDRESS      MemoryAddress,

-  IN  UINT64                    MemoryLength,

-  IN  EFI_MEMORY_CACHE_TYPE     MemoryCacheType,

-  IN  UINT64                    ValidMtrrAddressMask

+  IN  UINT32                 MtrrNumber,

+  IN  EFI_PHYSICAL_ADDRESS   MemoryAddress,

+  IN  UINT64                 MemoryLength,

+  IN  EFI_MEMORY_CACHE_TYPE  MemoryCacheType,

+  IN  UINT64                 ValidMtrrAddressMask

   )

 {

-  UINT64                        TempQword;

-  UINT64                        OldMtrr;

+  UINT64  TempQword;

+  UINT64  OldMtrr;

 

   if (MemoryLength == 0) {

     return;

@@ -206,11 +206,11 @@ EfiProgramMtrr (
 **/

 UINT64

 Power2MaxMemory (

-  IN UINT64                 MemoryAddress,

-  IN UINT64                 MemoryLength

+  IN UINT64  MemoryAddress,

+  IN UINT64  MemoryLength

   )

 {

-  UINT64                    Result;

+  UINT64  Result;

 

   if (MemoryLength == 0) {

     return EFI_INVALID_PARAMETER;

@@ -219,7 +219,7 @@ Power2MaxMemory (
   //

   // Compute initial power of 2 size to return

   //

-  Result = GetPowerOfTwo64(MemoryLength);

+  Result = GetPowerOfTwo64 (MemoryLength);

 

   //

   // Special case base of 0 as all ranges are valid

@@ -253,20 +253,20 @@ Power2MaxMemory (
 **/

 UINT32

 CheckMtrrAlignment (

-  IN  UINT64    BaseAddress,

-  IN  UINT64    Size

+  IN  UINT64  BaseAddress,

+  IN  UINT64  Size

   )

 {

-  UINT32      ShiftedBase;

-  UINT32      ShiftedSize;

+  UINT32  ShiftedBase;

+  UINT32  ShiftedSize;

 

   //

   // Shift base and size right 12 bits to allow for larger memory sizes.  The

   // MTRRs do not use the first 12 bits so this is safe for now.  Only supports

   // up to 52 bits of physical address space.

   //

-  ShiftedBase = (UINT32) RShiftU64 (BaseAddress, 12);

-  ShiftedSize = (UINT32) RShiftU64 (Size, 12);

+  ShiftedBase = (UINT32)RShiftU64 (BaseAddress, 12);

+  ShiftedSize = (UINT32)RShiftU64 (Size, 12);

 

   //

   // Return the results to the caller of the MOD

@@ -288,47 +288,53 @@ CheckMtrrAlignment (
 **/

 EFI_STATUS

 ProgramFixedMtrr (

-  IN  EFI_MEMORY_CACHE_TYPE     MemoryCacheType,

-  IN  UINT64                    *Base,

-  IN  UINT64                    *Len

+  IN  EFI_MEMORY_CACHE_TYPE  MemoryCacheType,

+  IN  UINT64                 *Base,

+  IN  UINT64                 *Len

   )

 {

-  UINT32                      MsrNum;

-  UINT32                      ByteShift;

-  UINT64                      TempQword;

-  UINT64                      OrMask;

-  UINT64                      ClearMask;

+  UINT32  MsrNum;

+  UINT32  ByteShift;

+  UINT64  TempQword;

+  UINT64  OrMask;

+  UINT64  ClearMask;

 

   TempQword = 0;

-  OrMask =  0;

+  OrMask    =  0;

   ClearMask = 0;

 

   for (MsrNum = 0; MsrNum < V_EFI_FIXED_MTRR_NUMBER; MsrNum++) {

     if ((*Base >= mFixedMtrrTable[MsrNum].BaseAddress) &&

-        (*Base < (mFixedMtrrTable[MsrNum].BaseAddress + 8 * mFixedMtrrTable[MsrNum].Length))) {

+        (*Base < (mFixedMtrrTable[MsrNum].BaseAddress + 8 * mFixedMtrrTable[MsrNum].Length)))

+    {

       break;

     }

   }

+

   if (MsrNum == V_EFI_FIXED_MTRR_NUMBER ) {

     return EFI_DEVICE_ERROR;

   }

+

   //

   // We found the fixed MTRR to be programmed

   //

-  for (ByteShift=0; ByteShift < 8; ByteShift++) {

+  for (ByteShift = 0; ByteShift < 8; ByteShift++) {

     if ( *Base == (mFixedMtrrTable[MsrNum].BaseAddress + ByteShift * mFixedMtrrTable[MsrNum].Length)) {

       break;

     }

   }

+

   if (ByteShift == 8 ) {

     return EFI_DEVICE_ERROR;

   }

-  for (; ((ByteShift<8) && (*Len >= mFixedMtrrTable[MsrNum].Length));ByteShift++) {

-    OrMask |= LShiftU64((UINT64) MemoryCacheType, (UINT32) (ByteShift* 8));

-    ClearMask |= LShiftU64((UINT64) 0xFF, (UINT32) (ByteShift * 8));

-    *Len -= mFixedMtrrTable[MsrNum].Length;

-    *Base += mFixedMtrrTable[MsrNum].Length;

+

+  for ( ; ((ByteShift < 8) && (*Len >= mFixedMtrrTable[MsrNum].Length)); ByteShift++) {

+    OrMask    |= LShiftU64 ((UINT64)MemoryCacheType, (UINT32)(ByteShift* 8));

+    ClearMask |= LShiftU64 ((UINT64)0xFF, (UINT32)(ByteShift * 8));

+    *Len      -= mFixedMtrrTable[MsrNum].Length;

+    *Base     += mFixedMtrrTable[MsrNum].Length;

   }

+

   TempQword = (AsmReadMsr64 (mFixedMtrrTable[MsrNum].Msr) & (~ClearMask)) | OrMask;

   AsmWriteMsr64 (mFixedMtrrTable[MsrNum].Msr, TempQword);

 

@@ -346,8 +352,8 @@ ProgramFixedMtrr (
 **/

 BOOLEAN

 CheckMtrrOverlap (

-  IN  EFI_PHYSICAL_ADDRESS      Start,

-  IN  EFI_PHYSICAL_ADDRESS      End

+  IN  EFI_PHYSICAL_ADDRESS  Start,

+  IN  EFI_PHYSICAL_ADDRESS  End

   )

 {

   return FALSE;

@@ -369,33 +375,33 @@ CheckMtrrOverlap (
 EFI_STATUS

 EFIAPI

 SetCacheAttributes (

-  IN  EFI_PHYSICAL_ADDRESS      MemoryAddress,

-  IN  UINT64                    MemoryLength,

-  IN  EFI_MEMORY_CACHE_TYPE     MemoryCacheType

+  IN  EFI_PHYSICAL_ADDRESS   MemoryAddress,

+  IN  UINT64                 MemoryLength,

+  IN  EFI_MEMORY_CACHE_TYPE  MemoryCacheType

   )

 {

-  EFI_STATUS            Status;

-  UINT32                MsrNum, MsrNumEnd;

-  UINT64                TempQword;

-  UINT32                LastVariableMtrrForBios;

-  UINT64                OldMtrr;

-  UINT32                UsedMsrNum;

-  EFI_MEMORY_CACHE_TYPE UsedMemoryCacheType;

-  UINT64                ValidMtrrAddressMask;

-  UINT32                Cpuid_RegEax;

+  EFI_STATUS             Status;

+  UINT32                 MsrNum, MsrNumEnd;

+  UINT64                 TempQword;

+  UINT32                 LastVariableMtrrForBios;

+  UINT64                 OldMtrr;

+  UINT32                 UsedMsrNum;

+  EFI_MEMORY_CACHE_TYPE  UsedMemoryCacheType;

+  UINT64                 ValidMtrrAddressMask;

+  UINT32                 Cpuid_RegEax;

 

   AsmCpuid (CPUID_EXTENDED_FUNCTION, &Cpuid_RegEax, NULL, NULL, NULL);

   if (Cpuid_RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {

     AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Cpuid_RegEax, NULL, NULL, NULL);

-    ValidMtrrAddressMask = (LShiftU64((UINT64) 1, (Cpuid_RegEax & 0xFF)) - 1) & (~(UINT64)0x0FFF);

+    ValidMtrrAddressMask = (LShiftU64 ((UINT64)1, (Cpuid_RegEax & 0xFF)) - 1) & (~(UINT64)0x0FFF);

   } else {

-    ValidMtrrAddressMask = (LShiftU64((UINT64) 1, 36) - 1) & (~(UINT64)0x0FFF);

+    ValidMtrrAddressMask = (LShiftU64 ((UINT64)1, 36) - 1) & (~(UINT64)0x0FFF);

   }

 

   //

   // Check for invalid parameter

   //

-  if ((MemoryAddress & ~ValidMtrrAddressMask) != 0 || (MemoryLength & ~ValidMtrrAddressMask) != 0) {

+  if (((MemoryAddress & ~ValidMtrrAddressMask) != 0) || ((MemoryLength & ~ValidMtrrAddressMask) != 0)) {

     return EFI_INVALID_PARAMETER;

   }

 

@@ -424,6 +430,7 @@ SetCacheAttributes (
     while ((MemoryLength > 0) && (Status == EFI_SUCCESS)) {

       Status = ProgramFixedMtrr (MemoryCacheType, &MemoryAddress, &MemoryLength);

     }

+

     EfiRecoverCacheMtrr (TRUE, OldMtrr);

     return Status;

   }

@@ -431,15 +438,15 @@ SetCacheAttributes (
   //

   // Search if the range attribute has been set before

   //

-  Status = SearchForExactMtrr(

-                              MemoryAddress,

-                              MemoryLength,

-                              ValidMtrrAddressMask,

-                              &UsedMsrNum,

-                              &UsedMemoryCacheType

-                              );

+  Status = SearchForExactMtrr (

+             MemoryAddress,

+             MemoryLength,

+             ValidMtrrAddressMask,

+             &UsedMsrNum,

+             &UsedMemoryCacheType

+             );

 

-  if (!EFI_ERROR(Status)) {

+  if (!EFI_ERROR (Status)) {

     //

     // Compare if it has the same type as current setting

     //

@@ -453,49 +460,51 @@ SetCacheAttributes (
       //

       // Check if the set type is the same as Default Type

       //

-      if (IsDefaultType(MemoryCacheType)) {

+      if (IsDefaultType (MemoryCacheType)) {

         //

         // Clear the MTRR

         //

-        AsmWriteMsr64(UsedMsrNum, 0);

-        AsmWriteMsr64(UsedMsrNum + 1, 0);

+        AsmWriteMsr64 (UsedMsrNum, 0);

+        AsmWriteMsr64 (UsedMsrNum + 1, 0);

 

         return EFI_SUCCESS;

       } else {

         //

         // Modify the MTRR type

         //

-        EfiProgramMtrr(UsedMsrNum,

-                       MemoryAddress,

-                       MemoryLength,

-                       MemoryCacheType,

-                       ValidMtrrAddressMask

-                       );

+        EfiProgramMtrr (

+          UsedMsrNum,

+          MemoryAddress,

+          MemoryLength,

+          MemoryCacheType,

+          ValidMtrrAddressMask

+          );

         return EFI_SUCCESS;

       }

     }

   }

 

-#if 0

+ #if 0

   //

   // @bug - Need to create memory map so that when checking for overlap we

   //        can determine if an overlap exists based on all caching requests.

   //

   // Don't waste a variable MTRR if the caching attrib is same as default in MTRR_DEF_TYPE

   //

-  if (MemoryCacheType == (AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE))  {

+  if (MemoryCacheType == (AsmReadMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE)) {

     if (!CheckMtrrOverlap (MemoryAddress, MemoryAddress+MemoryLength-1)) {

       return EFI_SUCCESS;

     }

   }

-#endif

+

+ #endif

 

   //

   // Find first unused MTRR

   //

-  MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));

-  for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum +=2) {

-    if ((AsmReadMsr64(MsrNum+1) & B_EFI_MSR_CACHE_MTRR_VALID) == 0 ) {

+  MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64 (EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));

+  for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum += 2) {

+    if ((AsmReadMsr64 (MsrNum+1) & B_EFI_MSR_CACHE_MTRR_VALID) == 0 ) {

       break;

     }

   }

@@ -520,14 +529,14 @@ SetCacheAttributes (
   //

   TempQword = MemoryLength;

 

-  if (TempQword == Power2MaxMemory(MemoryAddress, TempQword)) {

-    EfiProgramMtrr(MsrNum,

-                   MemoryAddress,

-                   MemoryLength,

-                   MemoryCacheType,

-                   ValidMtrrAddressMask

-                   );

-

+  if (TempQword == Power2MaxMemory (MemoryAddress, TempQword)) {

+    EfiProgramMtrr (

+      MsrNum,

+      MemoryAddress,

+      MemoryLength,

+      MemoryCacheType,

+      ValidMtrrAddressMask

+      );

   } else {

     //

     // Fill in MTRRs with values.  Direction can not be checked for this method

@@ -545,16 +554,17 @@ SetCacheAttributes (
       //

       // Set next power of 2 region

       //

-      MemoryLength = Power2MaxMemory(MemoryAddress, TempQword);

-      EfiProgramMtrr(MsrNum,

-                     MemoryAddress,

-                     MemoryLength,

-                     MemoryCacheType,

-                     ValidMtrrAddressMask

-                     );

+      MemoryLength = Power2MaxMemory (MemoryAddress, TempQword);

+      EfiProgramMtrr (

+        MsrNum,

+        MemoryAddress,

+        MemoryLength,

+        MemoryCacheType,

+        ValidMtrrAddressMask

+        );

       MemoryAddress += MemoryLength;

-      TempQword -= MemoryLength;

-      MsrNum += 2;

+      TempQword     -= MemoryLength;

+      MsrNum        += 2;

     } while (TempQword != 0);

   }

 

@@ -573,12 +583,13 @@ ResetCacheAttributes (
   VOID

   )

 {

-  UINT32                      MsrNum, MsrNumEnd;

-  UINT16                      Index;

-  UINT64                      OldMtrr;

-  UINT64                      CacheType;

-  BOOLEAN                     DisableCar;

-  Index = 0;

+  UINT32   MsrNum, MsrNumEnd;

+  UINT16   Index;

+  UINT64   OldMtrr;

+  UINT64   CacheType;

+  BOOLEAN  DisableCar;

+

+  Index      = 0;

   DisableCar = TRUE;

 

   //

@@ -589,7 +600,7 @@ ResetCacheAttributes (
   //

   // Set default cache type

   //

-  AsmWriteMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, CacheType);

+  AsmWriteMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, CacheType);

 

   //

   // Disable CAR

@@ -608,7 +619,7 @@ ResetCacheAttributes (
   //

   // Reset Variable MTRRs

   //

-  MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));

+  MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64 (EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));

   for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum++) {

     AsmWriteMsr64 (MsrNum, 0);

   }

@@ -636,23 +647,23 @@ ResetCacheAttributes (
 **/

 EFI_STATUS

 SearchForExactMtrr (

-  IN  EFI_PHYSICAL_ADDRESS      MemoryAddress,

-  IN  UINT64                    MemoryLength,

-  IN  UINT64                    ValidMtrrAddressMask,

-  OUT UINT32                    *UsedMsrNum,

-  OUT EFI_MEMORY_CACHE_TYPE     *UsedMemoryCacheType

+  IN  EFI_PHYSICAL_ADDRESS   MemoryAddress,

+  IN  UINT64                 MemoryLength,

+  IN  UINT64                 ValidMtrrAddressMask,

+  OUT UINT32                 *UsedMsrNum,

+  OUT EFI_MEMORY_CACHE_TYPE  *UsedMemoryCacheType

   )

 {

-  UINT32                      MsrNum, MsrNumEnd;

-  UINT64                      TempQword;

+  UINT32  MsrNum, MsrNumEnd;

+  UINT64  TempQword;

 

   if (MemoryLength == 0) {

     return EFI_INVALID_PARAMETER;

   }

 

-  MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));

-  for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum +=2) {

-    TempQword = AsmReadMsr64(MsrNum+1);

+  MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64 (EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));

+  for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum += 2) {

+    TempQword = AsmReadMsr64 (MsrNum+1);

     if ((TempQword & B_EFI_MSR_CACHE_MTRR_VALID) == 0) {

       continue;

     }

@@ -667,7 +678,7 @@ SearchForExactMtrr (
     }

 

     *UsedMemoryCacheType = (EFI_MEMORY_CACHE_TYPE)(TempQword & B_EFI_MSR_CACHE_MEMORY_TYPE);

-    *UsedMsrNum = MsrNum;

+    *UsedMsrNum          = MsrNum;

 

     return EFI_SUCCESS;

   }

@@ -685,13 +696,12 @@ SearchForExactMtrr (
 **/

 BOOLEAN

 IsDefaultType (

-  IN  EFI_MEMORY_CACHE_TYPE     MemoryCacheType

+  IN  EFI_MEMORY_CACHE_TYPE  MemoryCacheType

   )

 {

-  if ((AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE) != MemoryCacheType) {

+  if ((AsmReadMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE) != MemoryCacheType) {

     return FALSE;

   }

 

   return TRUE;

 }

-

diff --git a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLibInternal.h b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLibInternal.h
index 56d3727111..7dcf7fef24 100644
--- a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLibInternal.h
+++ b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLibInternal.h
@@ -8,46 +8,45 @@
 #ifndef _CACHE_LIB_INTERNAL_H_

 #define _CACHE_LIB_INTERNAL_H_

 

-#define EFI_MSR_CACHE_VARIABLE_MTRR_BASE       0x00000200

-#define EFI_MSR_CACHE_VARIABLE_MTRR_END        0x0000020F

-#define   V_EFI_FIXED_MTRR_NUMBER                                      11

-

-#define EFI_MSR_IA32_MTRR_FIX64K_00000         0x00000250

-#define EFI_MSR_IA32_MTRR_FIX16K_80000         0x00000258

-#define EFI_MSR_IA32_MTRR_FIX16K_A0000         0x00000259

-#define EFI_MSR_IA32_MTRR_FIX4K_C0000          0x00000268

-#define EFI_MSR_IA32_MTRR_FIX4K_C8000          0x00000269

-#define EFI_MSR_IA32_MTRR_FIX4K_D0000          0x0000026A

-#define EFI_MSR_IA32_MTRR_FIX4K_D8000          0x0000026B

-#define EFI_MSR_IA32_MTRR_FIX4K_E0000          0x0000026C

-#define EFI_MSR_IA32_MTRR_FIX4K_E8000          0x0000026D

-#define EFI_MSR_IA32_MTRR_FIX4K_F0000          0x0000026E

-#define EFI_MSR_IA32_MTRR_FIX4K_F8000          0x0000026F

-#define EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE       0x000002FF

-#define   B_EFI_MSR_CACHE_MTRR_VALID                                   BIT11

-#define   B_EFI_MSR_GLOBAL_MTRR_ENABLE                                 BIT11

-#define   B_EFI_MSR_FIXED_MTRR_ENABLE                                  BIT10

-#define   B_EFI_MSR_CACHE_MEMORY_TYPE                                  (BIT2 | BIT1 | BIT0)

-

-#define EFI_MSR_VALID_MASK                     0xFFFFFFFFF

-#define EFI_CACHE_VALID_ADDRESS                0xFFFFFF000

-#define EFI_SMRR_CACHE_VALID_ADDRESS           0xFFFFF000

-#define EFI_CACHE_VALID_EXTENDED_ADDRESS       0xFFFFFFFFFF000

+#define EFI_MSR_CACHE_VARIABLE_MTRR_BASE  0x00000200

+#define EFI_MSR_CACHE_VARIABLE_MTRR_END   0x0000020F

+#define   V_EFI_FIXED_MTRR_NUMBER         11

+

+#define EFI_MSR_IA32_MTRR_FIX64K_00000    0x00000250

+#define EFI_MSR_IA32_MTRR_FIX16K_80000    0x00000258

+#define EFI_MSR_IA32_MTRR_FIX16K_A0000    0x00000259

+#define EFI_MSR_IA32_MTRR_FIX4K_C0000     0x00000268

+#define EFI_MSR_IA32_MTRR_FIX4K_C8000     0x00000269

+#define EFI_MSR_IA32_MTRR_FIX4K_D0000     0x0000026A

+#define EFI_MSR_IA32_MTRR_FIX4K_D8000     0x0000026B

+#define EFI_MSR_IA32_MTRR_FIX4K_E0000     0x0000026C

+#define EFI_MSR_IA32_MTRR_FIX4K_E8000     0x0000026D

+#define EFI_MSR_IA32_MTRR_FIX4K_F0000     0x0000026E

+#define EFI_MSR_IA32_MTRR_FIX4K_F8000     0x0000026F

+#define EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE  0x000002FF

+#define   B_EFI_MSR_CACHE_MTRR_VALID      BIT11

+#define   B_EFI_MSR_GLOBAL_MTRR_ENABLE    BIT11

+#define   B_EFI_MSR_FIXED_MTRR_ENABLE     BIT10

+#define   B_EFI_MSR_CACHE_MEMORY_TYPE     (BIT2 | BIT1 | BIT0)

+

+#define EFI_MSR_VALID_MASK                0xFFFFFFFFF

+#define EFI_CACHE_VALID_ADDRESS           0xFFFFFF000

+#define EFI_SMRR_CACHE_VALID_ADDRESS      0xFFFFF000

+#define EFI_CACHE_VALID_EXTENDED_ADDRESS  0xFFFFFFFFFF000

 

 // Leave one MTRR pairs for OS use

-#define EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS   1

-#define EFI_CACHE_LAST_VARIABLE_MTRR_FOR_BIOS (EFI_MSR_CACHE_VARIABLE_MTRR_END) - \

+#define EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS    1

+#define EFI_CACHE_LAST_VARIABLE_MTRR_FOR_BIOS  (EFI_MSR_CACHE_VARIABLE_MTRR_END) -\

         (EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS * 2)

 

-#define EFI_MSR_IA32_MTRR_CAP                  0x000000FE

-#define   B_EFI_MSR_IA32_MTRR_CAP_EMRR_SUPPORT                         BIT12

-#define   B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT                         BIT11

-#define   B_EFI_MSR_IA32_MTRR_CAP_WC_SUPPORT                           BIT10

-#define   B_EFI_MSR_IA32_MTRR_CAP_FIXED_SUPPORT                        BIT8

-#define   B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT                     (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)

+#define EFI_MSR_IA32_MTRR_CAP                       0x000000FE

+#define   B_EFI_MSR_IA32_MTRR_CAP_EMRR_SUPPORT      BIT12

+#define   B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT      BIT11

+#define   B_EFI_MSR_IA32_MTRR_CAP_WC_SUPPORT        BIT10

+#define   B_EFI_MSR_IA32_MTRR_CAP_FIXED_SUPPORT     BIT8

+#define   B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT  (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)

 

-#define CPUID_VIR_PHY_ADDRESS_SIZE                                    0x80000008

-#define CPUID_EXTENDED_FUNCTION                                       0x80000000

+#define CPUID_VIR_PHY_ADDRESS_SIZE  0x80000008

+#define CPUID_EXTENDED_FUNCTION     0x80000000

 

 #endif

-

diff --git a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
index 0a5bc76aa7..8f8453915e 100644
--- a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
+++ b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
@@ -57,11 +57,11 @@ typedef struct {
 VOID

 EFIAPI

 SetFspGlobalDataPointer (

-  IN FSP_GLOBAL_DATA   *FspData

+  IN FSP_GLOBAL_DATA  *FspData

   )

 {

   ASSERT (FspData != NULL);

-  *((volatile UINT32 *)(UINTN)PcdGet32(PcdGlobalDataPointerAddress)) = (UINT32)(UINTN)FspData;

+  *((volatile UINT32 *)(UINTN)PcdGet32 (PcdGlobalDataPointerAddress)) = (UINT32)(UINTN)FspData;

 }

 

 /**

@@ -74,9 +74,9 @@ GetFspGlobalDataPointer (
   VOID

   )

 {

-  FSP_GLOBAL_DATA   *FspData;

+  FSP_GLOBAL_DATA  *FspData;

 

-  FspData = *(FSP_GLOBAL_DATA  **)(UINTN)PcdGet32(PcdGlobalDataPointerAddress);

+  FspData = *(FSP_GLOBAL_DATA  **)(UINTN)PcdGet32 (PcdGlobalDataPointerAddress);

   return FspData;

 }

 

@@ -93,8 +93,8 @@ GetFspApiParameter (
 {

   FSP_GLOBAL_DATA  *FspData;

 

-  FspData  = GetFspGlobalDataPointer ();

-  return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam[0]));

+  FspData = GetFspGlobalDataPointer ();

+  return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (ApiParam[0]));

 }

 

 /**

@@ -102,7 +102,7 @@ GetFspApiParameter (
 

   @retval FSP entry stack pointer.

 **/

-VOID*

+VOID *

 EFIAPI

 GetFspEntryStack (

   VOID

@@ -110,8 +110,8 @@ GetFspEntryStack (
 {

   FSP_GLOBAL_DATA  *FspData;

 

-  FspData  = GetFspGlobalDataPointer ();

-  return (VOID*)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam[0]));

+  FspData = GetFspGlobalDataPointer ();

+  return (VOID *)(FspData->CoreStack + CONTEXT_STACK_OFFSET (ApiParam[0]));

 }

 

 /**

@@ -127,8 +127,8 @@ GetFspApiParameter2 (
 {

   FSP_GLOBAL_DATA  *FspData;

 

-  FspData  = GetFspGlobalDataPointer ();

-  return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam[1]));

+  FspData = GetFspGlobalDataPointer ();

+  return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (ApiParam[1]));

 }

 

 /**

@@ -140,13 +140,13 @@ GetFspApiParameter2 (
 VOID

 EFIAPI

 SetFspApiParameter (

-  IN UINT32      Value

+  IN UINT32  Value

   )

 {

   FSP_GLOBAL_DATA  *FspData;

 

-  FspData  = GetFspGlobalDataPointer ();

-  *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam)) = Value;

+  FspData                                                                  = GetFspGlobalDataPointer ();

+  *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (ApiParam)) = Value;

 }

 

 /**

@@ -163,8 +163,8 @@ SetFspApiReturnStatus (
 {

   FSP_GLOBAL_DATA  *FspData;

 

-  FspData  = GetFspGlobalDataPointer ();

-  *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(Eax)) = ReturnStatus;

+  FspData                                                             = GetFspGlobalDataPointer ();

+  *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (Eax)) = ReturnStatus;

 }

 

 /**

@@ -176,7 +176,7 @@ SetFspApiReturnStatus (
 VOID

 EFIAPI

 SetFspCoreStackPointer (

-  IN VOID   *NewStackTop

+  IN VOID  *NewStackTop

   )

 {

   FSP_GLOBAL_DATA  *FspData;

@@ -184,14 +184,14 @@ SetFspCoreStackPointer (
   UINT32           *NewStack;

   UINT32           StackContextLen;

 

-  FspData  = GetFspGlobalDataPointer ();

-  StackContextLen = sizeof(CONTEXT_STACK) / sizeof(UINT32);

+  FspData         = GetFspGlobalDataPointer ();

+  StackContextLen = sizeof (CONTEXT_STACK) / sizeof (UINT32);

 

   //

   // Reserve space for the ContinuationFunc two parameters

   //

-  OldStack = (UINT32 *)FspData->CoreStack;

-  NewStack = (UINT32 *)NewStackTop - StackContextLen - 2;

+  OldStack           = (UINT32 *)FspData->CoreStack;

+  NewStack           = (UINT32 *)NewStackTop - StackContextLen - 2;

   FspData->CoreStack = (UINT32)NewStack;

   while (StackContextLen-- != 0) {

     *NewStack++ = *OldStack++;

@@ -207,16 +207,15 @@ SetFspCoreStackPointer (
 VOID

 EFIAPI

 SetFspPlatformDataPointer (

-  IN VOID   *PlatformData

+  IN VOID  *PlatformData

   )

 {

   FSP_GLOBAL_DATA  *FspData;

 

-  FspData  = GetFspGlobalDataPointer ();

+  FspData                       = GetFspGlobalDataPointer ();

   FspData->PlatformData.DataPtr = PlatformData;

 }

 

-

 /**

   This function gets the platform specific data pointer.

 

@@ -231,11 +230,10 @@ GetFspPlatformDataPointer (
 {

   FSP_GLOBAL_DATA  *FspData;

 

-  FspData  = GetFspGlobalDataPointer ();

+  FspData = GetFspGlobalDataPointer ();

   return FspData->PlatformData.DataPtr;

 }

 

-

 /**

   This function sets the UPD data pointer.

 

@@ -244,7 +242,7 @@ GetFspPlatformDataPointer (
 VOID

 EFIAPI

 SetFspUpdDataPointer (

-  IN VOID    *UpdDataPtr

+  IN VOID  *UpdDataPtr

   )

 {

   FSP_GLOBAL_DATA  *FspData;

@@ -252,7 +250,7 @@ SetFspUpdDataPointer (
   //

   // Get the FSP Global Data Pointer

   //

-  FspData  = GetFspGlobalDataPointer ();

+  FspData = GetFspGlobalDataPointer ();

 

   //

   // Set the UPD pointer.

@@ -273,11 +271,10 @@ GetFspUpdDataPointer (
 {

   FSP_GLOBAL_DATA  *FspData;

 

-  FspData  = GetFspGlobalDataPointer ();

+  FspData = GetFspGlobalDataPointer ();

   return FspData->UpdDataPtr;

 }

 

-

 /**

   This function sets the FspMemoryInit UPD data pointer.

 

@@ -286,7 +283,7 @@ GetFspUpdDataPointer (
 VOID

 EFIAPI

 SetFspMemoryInitUpdDataPointer (

-  IN VOID    *MemoryInitUpdPtr

+  IN VOID  *MemoryInitUpdPtr

   )

 {

   FSP_GLOBAL_DATA  *FspData;

@@ -294,7 +291,7 @@ SetFspMemoryInitUpdDataPointer (
   //

   // Get the FSP Global Data Pointer

   //

-  FspData  = GetFspGlobalDataPointer ();

+  FspData = GetFspGlobalDataPointer ();

 

   //

   // Set the FspMemoryInit UPD pointer.

@@ -315,11 +312,10 @@ GetFspMemoryInitUpdDataPointer (
 {

   FSP_GLOBAL_DATA  *FspData;

 

-  FspData  = GetFspGlobalDataPointer ();

+  FspData = GetFspGlobalDataPointer ();

   return FspData->MemoryInitUpdPtr;

 }

 

-

 /**

   This function sets the FspSiliconInit UPD data pointer.

 

@@ -328,7 +324,7 @@ GetFspMemoryInitUpdDataPointer (
 VOID

 EFIAPI

 SetFspSiliconInitUpdDataPointer (

-  IN VOID    *SiliconInitUpdPtr

+  IN VOID  *SiliconInitUpdPtr

   )

 {

   FSP_GLOBAL_DATA  *FspData;

@@ -336,7 +332,7 @@ SetFspSiliconInitUpdDataPointer (
   //

   // Get the FSP Global Data Pointer

   //

-  FspData  = GetFspGlobalDataPointer ();

+  FspData = GetFspGlobalDataPointer ();

 

   //

   // Set the FspSiliconInit UPD data pointer.

@@ -357,11 +353,10 @@ GetFspSiliconInitUpdDataPointer (
 {

   FSP_GLOBAL_DATA  *FspData;

 

-  FspData  = GetFspGlobalDataPointer ();

+  FspData = GetFspGlobalDataPointer ();

   return FspData->SiliconInitUpdPtr;

 }

 

-

 /**

   Set FSP measurement point timestamp.

 

@@ -381,9 +376,9 @@ SetFspMeasurePoint (
   // Bit [55: 0]  will be the timestamp

   // Bit [63:56]  will be the ID

   //

-  FspData  = GetFspGlobalDataPointer ();

-  if (FspData->PerfIdx < sizeof(FspData->PerfData) / sizeof(FspData->PerfData[0])) {

-    FspData->PerfData[FspData->PerfIdx] = AsmReadTsc ();

+  FspData = GetFspGlobalDataPointer ();

+  if (FspData->PerfIdx < sizeof (FspData->PerfData) / sizeof (FspData->PerfData[0])) {

+    FspData->PerfData[FspData->PerfIdx]                  = AsmReadTsc ();

     ((UINT8 *)(&FspData->PerfData[FspData->PerfIdx]))[7] = Id;

   }

 

@@ -401,7 +396,7 @@ GetFspInfoHeader (
   VOID

   )

 {

-  return  GetFspGlobalDataPointer()->FspInfoHeader;

+  return GetFspGlobalDataPointer ()->FspInfoHeader;

 }

 

 /**

@@ -412,10 +407,10 @@ GetFspInfoHeader (
 VOID

 EFIAPI

 SetFspInfoHeader (

-  FSP_INFO_HEADER *FspInfoHeader

+  FSP_INFO_HEADER  *FspInfoHeader

   )

 {

-  GetFspGlobalDataPointer()->FspInfoHeader = FspInfoHeader;

+  GetFspGlobalDataPointer ()->FspInfoHeader = FspInfoHeader;

 }

 

 /**

@@ -431,8 +426,8 @@ GetFspInfoHeaderFromApiContext (
 {

   FSP_GLOBAL_DATA  *FspData;

 

-  FspData  = GetFspGlobalDataPointer ();

-  return  (FSP_INFO_HEADER *)(*(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(FspInfoHeader)));

+  FspData = GetFspGlobalDataPointer ();

+  return (FSP_INFO_HEADER *)(*(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (FspInfoHeader)));

 }

 

 /**

@@ -446,7 +441,7 @@ GetFspCfgRegionDataPointer (
   VOID

   )

 {

-  FSP_INFO_HEADER   *FspInfoHeader;

+  FSP_INFO_HEADER  *FspInfoHeader;

 

   FspInfoHeader = GetFspInfoHeader ();

   return (VOID *)(FspInfoHeader->ImageBase + FspInfoHeader->CfgRegionOffset);

@@ -463,7 +458,7 @@ GetFspApiCallingIndex (
   VOID

   )

 {

-  return  GetFspGlobalDataPointer()->ApiIdx;

+  return GetFspGlobalDataPointer ()->ApiIdx;

 }

 

 /**

@@ -479,7 +474,7 @@ SetFspApiCallingIndex (
 {

   FSP_GLOBAL_DATA  *FspData;

 

-  FspData  = GetFspGlobalDataPointer ();

+  FspData         = GetFspGlobalDataPointer ();

   FspData->ApiIdx = Index;

 }

 

@@ -494,7 +489,7 @@ GetPhaseStatusCode (
   VOID

   )

 {

-  return  GetFspGlobalDataPointer()->StatusCode;

+  return GetFspGlobalDataPointer ()->StatusCode;

 }

 

 /**

@@ -510,7 +505,7 @@ SetPhaseStatusCode (
 {

   FSP_GLOBAL_DATA  *FspData;

 

-  FspData  = GetFspGlobalDataPointer ();

+  FspData             = GetFspGlobalDataPointer ();

   FspData->StatusCode = StatusCode;

 }

 

@@ -523,13 +518,13 @@ SetPhaseStatusCode (
 VOID

 EFIAPI

 FspApiReturnStatusReset (

-  IN UINT32   FspResetType

+  IN UINT32  FspResetType

   )

 {

   volatile BOOLEAN  LoopUntilReset;

 

   LoopUntilReset = TRUE;

-  DEBUG ((DEBUG_INFO, "FSP returning control to Bootloader with reset required return status %x\n",FspResetType));

+  DEBUG ((DEBUG_INFO, "FSP returning control to Bootloader with reset required return status %x\n", FspResetType));

   if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {

     ///

     /// Below code is not an infinite loop.The control will go back to API calling function in BootLoader each time BootLoader

diff --git a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c
index b34905365d..c8824cde7f 100644
--- a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c
+++ b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c
@@ -26,7 +26,7 @@ CONST CHAR8  *mHexTable = "0123456789ABCDEF";
 // VA_LIST can not initialize to NULL for all compiler, so we use this to

 // indicate a null VA_LIST

 //

-VA_LIST     mVaListNull;

+VA_LIST  mVaListNull;

 

 /**

   Get stack frame pointer of function call.

@@ -39,7 +39,6 @@ GetStackFramePointer (
   VOID

   );

 

-

 /**

   Prints a debug message to the debug output device if the specified error level is enabled.

 

@@ -63,7 +62,7 @@ DebugPrint (
   ...

   )

 {

-  VA_LIST         Marker;

+  VA_LIST  Marker;

 

   VA_START (Marker, Format);

   DebugVPrint (ErrorLevel, Format, Marker);

@@ -89,13 +88,13 @@ DebugPrint (
 **/

 VOID

 DebugPrintMarker (

-  IN  UINTN         ErrorLevel,

-  IN  CONST CHAR8   *Format,

-  IN  VA_LIST       VaListMarker,

-  IN  BASE_LIST     BaseListMarker

+  IN  UINTN        ErrorLevel,

+  IN  CONST CHAR8  *Format,

+  IN  VA_LIST      VaListMarker,

+  IN  BASE_LIST    BaseListMarker

   )

 {

-  CHAR8    Buffer[MAX_DEBUG_MESSAGE_LENGTH];

+  CHAR8  Buffer[MAX_DEBUG_MESSAGE_LENGTH];

 

   //

   // If Format is NULL, then ASSERT().

@@ -149,9 +148,9 @@ DebugPrintMarker (
 VOID

 EFIAPI

 DebugVPrint (

-  IN  UINTN         ErrorLevel,

-  IN  CONST CHAR8   *Format,

-  IN  VA_LIST       VaListMarker

+  IN  UINTN        ErrorLevel,

+  IN  CONST CHAR8  *Format,

+  IN  VA_LIST      VaListMarker

   )

 {

   DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL);

@@ -177,9 +176,9 @@ DebugVPrint (
 VOID

 EFIAPI

 DebugBPrint (

-  IN  UINTN         ErrorLevel,

-  IN  CONST CHAR8   *Format,

-  IN  BASE_LIST     BaseListMarker

+  IN  UINTN        ErrorLevel,

+  IN  CONST CHAR8  *Format,

+  IN  BASE_LIST    BaseListMarker

   )

 {

   DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker);

@@ -194,14 +193,15 @@ DebugBPrint (
 **/

 VOID

 FillHex (

-  UINT32   Value,

+  UINT32  Value,

   CHAR8   *Buffer

   )

 {

   INTN  Idx;

+

   for (Idx = 7; Idx >= 0; Idx--) {

     Buffer[Idx] = mHexTable[Value & 0x0F];

-    Value >>= 4;

+    Value     >>= 4;

   }

 }

 

@@ -227,8 +227,8 @@ DebugAssertInternal (
   VOID

   )

 {

-  CHAR8     Buffer[MAX_DEBUG_MESSAGE_LENGTH];

-  UINT32   *Frame;

+  CHAR8   Buffer[MAX_DEBUG_MESSAGE_LENGTH];

+  UINT32  *Frame;

 

   Frame = (UINT32 *)GetStackFramePointer ();

 

@@ -237,9 +237,9 @@ DebugAssertInternal (
   //

   AsciiStrnCpyS (

     Buffer,

-    sizeof(Buffer) / sizeof(CHAR8),

+    sizeof (Buffer) / sizeof (CHAR8),

     "-> EBP:0x00000000  EIP:0x00000000\n",

-    sizeof(Buffer) / sizeof(CHAR8) - 1

+    sizeof (Buffer) / sizeof (CHAR8) - 1

     );

   SerialPortWrite ((UINT8 *)"ASSERT DUMP:\n", 13);

   while (Frame != NULL) {

@@ -291,7 +291,6 @@ DebugAssert (
   DebugAssertInternal ();

 }

 

-

 /**

   Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.

 

@@ -317,7 +316,6 @@ DebugClearMemory (
   return Buffer;

 }

 

-

 /**

   Returns TRUE if ASSERT() macros are enabled.

 

@@ -334,10 +332,9 @@ DebugAssertEnabled (
   VOID

   )

 {

-  return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);

+  return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);

 }

 

-

 /**

   Returns TRUE if DEBUG() macros are enabled.

 

@@ -354,7 +351,7 @@ DebugPrintEnabled (
   VOID

   )

 {

-  return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);

+  return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);

 }

 

 /**

@@ -373,10 +370,9 @@ DebugCodeEnabled (
   VOID

   )

 {

-  return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);

+  return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);

 }

 

-

 /**

   Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.

 

@@ -393,7 +389,7 @@ DebugClearMemoryEnabled (
   VOID

   )

 {

-  return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);

+  return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);

 }

 

 /**

@@ -408,8 +404,8 @@ DebugClearMemoryEnabled (
 BOOLEAN

 EFIAPI

 DebugPrintLevelEnabled (

-  IN  CONST UINTN        ErrorLevel

+  IN  CONST UINTN  ErrorLevel

   )

 {

-  return (BOOLEAN) ((ErrorLevel & PcdGet32(PcdFixedDebugPrintErrorLevel)) != 0);

+  return (BOOLEAN)((ErrorLevel & PcdGet32 (PcdFixedDebugPrintErrorLevel)) != 0);

 }

diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c
index a8d94cb417..2573e4e421 100644
--- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c
+++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c
@@ -25,10 +25,10 @@
 EFI_HOB_RESOURCE_DESCRIPTOR *

 EFIAPI

 FspGetResourceDescriptorByOwner (

-  IN EFI_GUID   *OwnerGuid

+  IN EFI_GUID  *OwnerGuid

   )

 {

-  EFI_PEI_HOB_POINTERS    Hob;

+  EFI_PEI_HOB_POINTERS  Hob;

 

   //

   // Get the HOB list for processing

@@ -41,10 +41,12 @@ FspGetResourceDescriptorByOwner (
   while (!END_OF_HOB_LIST (Hob)) {

     if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {

       if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) && \

-          (CompareGuid (&Hob.ResourceDescriptor->Owner, OwnerGuid))) {

-        return  Hob.ResourceDescriptor;

+          (CompareGuid (&Hob.ResourceDescriptor->Owner, OwnerGuid)))

+      {

+        return Hob.ResourceDescriptor;

       }

     }

+

     Hob.Raw = GET_NEXT_HOB (Hob);

   }

 

@@ -60,14 +62,14 @@ FspGetResourceDescriptorByOwner (
 VOID

 EFIAPI

 FspGetSystemMemorySize (

-  IN OUT UINT64              *LowMemoryLength,

-  IN OUT UINT64              *HighMemoryLength

+  IN OUT UINT64  *LowMemoryLength,

+  IN OUT UINT64  *HighMemoryLength

   )

 {

-  EFI_STATUS                  Status;

-  EFI_BOOT_MODE               BootMode;

-  EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;

-  EFI_PEI_HOB_POINTERS        Hob;

+  EFI_STATUS                   Status;

+  EFI_BOOT_MODE                BootMode;

+  EFI_RESOURCE_ATTRIBUTE_TYPE  ResourceAttribute;

+  EFI_PEI_HOB_POINTERS         Hob;

 

   ResourceAttribute = (

                        EFI_RESOURCE_ATTRIBUTE_PRESENT |

@@ -99,18 +101,21 @@ FspGetSystemMemorySize (
     if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {

       if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||

           ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&

-           (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))) {

+           (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute)))

+      {

         //

         // Need memory above 1MB to be collected here

         //

-        if (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB &&

-            Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) BASE_4GB) {

-          *LowMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);

-        } else if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) BASE_4GB) {

-          *HighMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);

+        if ((Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB) &&

+            (Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS)BASE_4GB))

+        {

+          *LowMemoryLength += (UINT64)(Hob.ResourceDescriptor->ResourceLength);

+        } else if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS)BASE_4GB) {

+          *HighMemoryLength += (UINT64)(Hob.ResourceDescriptor->ResourceLength);

         }

       }

     }

+

     Hob.Raw = GET_NEXT_HOB (Hob);

   }

 }

diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c
index 9274771155..795bb28c0f 100644
--- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c
+++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c
@@ -21,21 +21,21 @@
 #include <Protocol/PciEnumerationComplete.h>

 #include <Library/ReportStatusCodeLib.h>

 #include <Library/PerformanceLib.h>

-extern EFI_GUID gFspPerformanceDataGuid;

+extern EFI_GUID  gFspPerformanceDataGuid;

 

-EFI_PEI_PPI_DESCRIPTOR      mPeiPostPciEnumerationPpi = {

+EFI_PEI_PPI_DESCRIPTOR  mPeiPostPciEnumerationPpi = {

   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),

   &gEfiPciEnumerationCompleteProtocolGuid,

   NULL

 };

 

-EFI_PEI_PPI_DESCRIPTOR      mPeiReadyToBootPpi = {

+EFI_PEI_PPI_DESCRIPTOR  mPeiReadyToBootPpi = {

   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),

   &gEfiEventReadyToBootGuid,

   NULL

 };

 

-EFI_PEI_PPI_DESCRIPTOR      mPeiEndOfFirmwarePpi = {

+EFI_PEI_PPI_DESCRIPTOR  mPeiEndOfFirmwarePpi = {

   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),

   &gFspEventEndOfFirmwareGuid,

   NULL

@@ -59,41 +59,41 @@ UINT32  mFspNotifySequence[] = {
 EFI_STATUS

 EFIAPI

 FspNotificationHandler (

-  IN  UINT32     NotificationCode

+  IN  UINT32  NotificationCode

   )

 {

-  EFI_STATUS                Status;

+  EFI_STATUS  Status;

 

-  Status   = EFI_SUCCESS;

+  Status = EFI_SUCCESS;

 

   switch (NotificationCode) {

-  case EnumInitPhaseAfterPciEnumeration:

-    //

-    // Do POST PCI initialization if needed

-    //

-    DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Post PCI Enumeration ...\n"));

-    PeiServicesInstallPpi (&mPeiPostPciEnumerationPpi);

-    break;

-

-  case EnumInitPhaseReadyToBoot:

-    //

-    // Ready To Boot

-    //

-    DEBUG ((DEBUG_INFO| DEBUG_INIT, "FSP Ready To Boot ...\n"));

-    PeiServicesInstallPpi (&mPeiReadyToBootPpi);

-    break;

-

-  case EnumInitPhaseEndOfFirmware:

-    //

-    // End of Firmware

-    //

-    DEBUG ((DEBUG_INFO| DEBUG_INIT, "FSP End of Firmware ...\n"));

-    PeiServicesInstallPpi (&mPeiEndOfFirmwarePpi);

-    break;

-

-  default:

-    Status = EFI_INVALID_PARAMETER;

-    break;

+    case EnumInitPhaseAfterPciEnumeration:

+      //

+      // Do POST PCI initialization if needed

+      //

+      DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Post PCI Enumeration ...\n"));

+      PeiServicesInstallPpi (&mPeiPostPciEnumerationPpi);

+      break;

+

+    case EnumInitPhaseReadyToBoot:

+      //

+      // Ready To Boot

+      //

+      DEBUG ((DEBUG_INFO| DEBUG_INIT, "FSP Ready To Boot ...\n"));

+      PeiServicesInstallPpi (&mPeiReadyToBootPpi);

+      break;

+

+    case EnumInitPhaseEndOfFirmware:

+      //

+      // End of Firmware

+      //

+      DEBUG ((DEBUG_INFO| DEBUG_INIT, "FSP End of Firmware ...\n"));

+      PeiServicesInstallPpi (&mPeiEndOfFirmwarePpi);

+      break;

+

+    default:

+      Status = EFI_INVALID_PARAMETER;

+      break;

   }

 

   return Status;

@@ -108,10 +108,10 @@ FspNotificationHandler (
 VOID

 EFIAPI

 FspSiliconInitDone2 (

-  IN EFI_STATUS Status

+  IN EFI_STATUS  Status

   )

 {

-  volatile EFI_STATUS FspStatus;

+  volatile EFI_STATUS  FspStatus;

 

   FspStatus = Status;

   //

@@ -128,6 +128,7 @@ FspSiliconInitDone2 (
       Status = EFI_DEVICE_ERROR;  // Force to known error.

       break;

   }

+

   //

   // This is the end of the FspSiliconInit API

   // Give control back to the boot loader

@@ -156,12 +157,12 @@ FspSiliconInitDone2 (
 VOID

 EFIAPI

 FspMemoryInitDone2 (

-  IN EFI_STATUS Status,

-  IN OUT VOID   **HobListPtr

+  IN EFI_STATUS  Status,

+  IN OUT VOID    **HobListPtr

   )

 {

-  FSP_GLOBAL_DATA   *FspData;

-  volatile EFI_STATUS FspStatus;

+  FSP_GLOBAL_DATA      *FspData;

+  volatile EFI_STATUS  FspStatus;

 

   FspStatus = Status;

   //

@@ -171,9 +172,11 @@ FspMemoryInitDone2 (
   if (HobListPtr == NULL) {

     HobListPtr = (VOID **)GetFspApiParameter2 ();

   }

+

   if (HobListPtr != NULL) {

-    *HobListPtr = (VOID *) GetHobList ();

+    *HobListPtr = (VOID *)GetHobList ();

   }

+

   //

   // Convert to FSP EAS defined API return codes

   //

@@ -189,6 +192,7 @@ FspMemoryInitDone2 (
       Status = EFI_DEVICE_ERROR;  // Force to known error.

       break;

   }

+

   //

   // This is the end of the FspMemoryInit API

   // Give control back to the boot loader

@@ -196,10 +200,10 @@ FspMemoryInitDone2 (
   DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspMemoryInitApi() - [Status: 0x%08X] - End\n", Status));

   SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT);

   FspData = GetFspGlobalDataPointer ();

-  PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[0] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE| FSP_STATUS_CODE_API_ENTRY);

-  PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[1] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

-  PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[2] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

-  PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

+  PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[0] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE| FSP_STATUS_CODE_API_ENTRY);

+  PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[1] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

+  PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[2] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

+  PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

   REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

   if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {

     do {

@@ -217,13 +221,13 @@ FspMemoryInitDone2 (
   if (GetFspApiCallingIndex () == TempRamExitApiIndex) {

     SetPhaseStatusCode (FSP_STATUS_CODE_TEMP_RAM_EXIT);

     SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY);

-    PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

+    PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

     REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

     DEBUG ((DEBUG_INFO | DEBUG_INIT, "TempRamExitApi() - Begin\n"));

   } else {

     SetPhaseStatusCode (FSP_STATUS_CODE_SILICON_INIT);

     SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY);

-    PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

+    PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

     REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

     DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspSiliconInitApi() - Begin\n"));

   }

@@ -238,11 +242,11 @@ FspMemoryInitDone2 (
 VOID

 EFIAPI

 FspTempRamExitDone2 (

-  IN EFI_STATUS Status

+  IN EFI_STATUS  Status

   )

 {

   //

-  volatile EFI_STATUS FspStatus;

+  volatile EFI_STATUS  FspStatus;

 

   FspStatus = Status;

   // Convert to FSP EAS defined API return codes

@@ -258,13 +262,14 @@ FspTempRamExitDone2 (
       Status = EFI_DEVICE_ERROR;  // Force to known error.

       break;

   }

+

   //

   // This is the end of the TempRamExit API

   // Give control back to the boot loader

   //

   DEBUG ((DEBUG_INFO | DEBUG_INIT, "TempRamExitApi() - [Status: 0x%08X] - End\n", Status));

   SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT);

-  PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

+  PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

   REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

   if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {

     do {

@@ -275,9 +280,10 @@ FspTempRamExitDone2 (
       }

     } while (FspStatus != EFI_SUCCESS);

   }

+

   SetPhaseStatusCode (FSP_STATUS_CODE_SILICON_INIT);

   SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY);

-  PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

+  PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

   REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

   DEBUG ((DEBUG_INFO | DEBUG_INIT, "SiliconInitApi() - Begin\n"));

 }

@@ -294,15 +300,14 @@ FspWaitForNotify (
   VOID

   )

 {

-  EFI_STATUS                 Status;

-  UINT32                     NotificationValue;

-  UINT32                     NotificationCount;

-  UINT8                      Count;

-  volatile EFI_STATUS        FspStatus;

+  EFI_STATUS           Status;

+  UINT32               NotificationValue;

+  UINT32               NotificationCount;

+  UINT8                Count;

+  volatile EFI_STATUS  FspStatus;

 

   NotificationCount = 0;

-  while (NotificationCount < sizeof(mFspNotifySequence) / sizeof(UINT32)) {

-

+  while (NotificationCount < sizeof (mFspNotifySequence) / sizeof (UINT32)) {

     Count = (UINT8)((NotificationCount << 1) & 0x07);

     SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + Count);

 

@@ -312,7 +317,7 @@ FspWaitForNotify (
       REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

     } else if (NotificationCount == 1) {

       SetPhaseStatusCode (FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION);

-      PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

+      PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

       REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);

     } else if (NotificationCount == 2) {

       SetPhaseStatusCode (FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION);

@@ -333,7 +338,7 @@ FspWaitForNotify (
       // Process Notification and Give control back to the boot loader framework caller

       //

       Status = FspNotificationHandler (NotificationValue);

-      if (!EFI_ERROR(Status)) {

+      if (!EFI_ERROR (Status)) {

         NotificationCount++;

       }

     }

@@ -342,26 +347,28 @@ FspWaitForNotify (
     SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT + Count);

 

     if ((NotificationCount - 1) == 0) {

-      PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

+      PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

       REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

     } else if ((NotificationCount - 1) == 1) {

-      PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

+      PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

       REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

     } else if ((NotificationCount - 1) == 2) {

-      PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

+      PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

       REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);

     }

+

     if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {

       FspStatus = Status;

       do {

-        SetFspApiReturnStatus(Status);

-        Pei2LoaderSwitchStack();

+        SetFspApiReturnStatus (Status);

+        Pei2LoaderSwitchStack ();

         if (Status != EFI_SUCCESS) {

           DEBUG ((DEBUG_ERROR, "!!!ERROR: NotifyPhaseApi() [Phase: %08X] - Failed - [Status: 0x%08X]\n", NotificationValue, Status));

         }

       } while (FspStatus != EFI_SUCCESS);

     }

   }

+

   //

   // Control goes back to the PEI Core and it dispatches further PEIMs.

   // DXEIPL is the final one to transfer control back to the boot loader.

@@ -389,7 +396,7 @@ FspSiliconInitDone (
 VOID

 EFIAPI

 FspMemoryInitDone (

-  IN OUT VOID   **HobListPtr

+  IN OUT VOID  **HobListPtr

   )

 {

   FspMemoryInitDone2 (EFI_SUCCESS, HobListPtr);

diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/FspSwitchStackLib.c b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/FspSwitchStackLib.c
index fd553db629..618c25c3b0 100644
--- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/FspSwitchStackLib.c
+++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/FspSwitchStackLib.c
@@ -22,15 +22,14 @@
 **/

 UINT32

 SwapStack (

-  IN  UINT32 NewStack

+  IN  UINT32  NewStack

   )

 {

   FSP_GLOBAL_DATA  *FspData;

-  UINT32         OldStack;

+  UINT32           OldStack;

 

-  FspData  = GetFspGlobalDataPointer ();

-  OldStack = FspData->CoreStack;

+  FspData            = GetFspGlobalDataPointer ();

+  OldStack           = FspData->CoreStack;

   FspData->CoreStack = NewStack;

   return OldStack;

 }

-

diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c
index df8c5d121f..a6f3892ed8 100644
--- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c
+++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c
@@ -19,8 +19,8 @@
 EFI_STATUS

 EFIAPI

 FspUpdSignatureCheck (

-  IN UINT32   ApiIdx,

-  IN VOID     *ApiParam

+  IN UINT32  ApiIdx,

+  IN VOID    *ApiParam

   )

 {

   return EFI_SUCCESS;

@@ -36,8 +36,8 @@ FspUpdSignatureCheck (
 EFI_STATUS

 EFIAPI

 FspMultiPhaseSiInitApiHandler (

-  IN UINT32   ApiIdx,

-  IN VOID     *ApiParam

+  IN UINT32  ApiIdx,

+  IN VOID    *ApiParam

   )

 {

   return EFI_SUCCESS;

diff --git a/IntelFsp2Pkg/Tools/Tests/ExpectedFspUpd.h b/IntelFsp2Pkg/Tools/Tests/ExpectedFspUpd.h
index be2ed8aa99..10bb0c60f3 100644
--- a/IntelFsp2Pkg/Tools/Tests/ExpectedFspUpd.h
+++ b/IntelFsp2Pkg/Tools/Tests/ExpectedFspUpd.h
@@ -5,11 +5,11 @@
 

 #pragma pack(1)

 

-#define FSPT_UPD_SIGNATURE               0x545F4450554D4551        /* 'QEMUPD_T' */

+#define FSPT_UPD_SIGNATURE  0x545F4450554D4551                     /* 'QEMUPD_T' */

 

-#define FSPM_UPD_SIGNATURE               0x4D5F4450554D4551        /* 'QEMUPD_M' */

+#define FSPM_UPD_SIGNATURE  0x4D5F4450554D4551                     /* 'QEMUPD_M' */

 

-#define FSPS_UPD_SIGNATURE               0x535F4450554D4551        /* 'QEMUPD_S' */

+#define FSPS_UPD_SIGNATURE  0x535F4450554D4551                     /* 'QEMUPD_S' */

 

 #pragma pack()

 

diff --git a/IntelFsp2Pkg/Tools/Tests/ExpectedFspmUpd.h b/IntelFsp2Pkg/Tools/Tests/ExpectedFspmUpd.h
index 49dadbac62..0000ea7e60 100644
--- a/IntelFsp2Pkg/Tools/Tests/ExpectedFspmUpd.h
+++ b/IntelFsp2Pkg/Tools/Tests/ExpectedFspmUpd.h
@@ -5,69 +5,66 @@
 

 #pragma pack(1)

 

-

 /** Fsp M Configuration

 **/

 typedef struct {

-

-/** Offset 0x00C8 - Debug Serial Port Base address

-  Debug serial port base address. This option will be used only when the 'Serial Port

-  Debug Device' option is set to 'External Device'. 0x00000000(Default).

-**/

-  UINT32                      SerialDebugPortAddress;

-

-/** Offset 0x00CC - Debug Serial Port Type

-  16550 compatible debug serial port resource type. NONE means no serial port support.

-  0x02:MMIO(Default).

-  0:NONE, 1:I/O, 2:MMIO

-**/

-  UINT8                       SerialDebugPortType;

-

-/** Offset 0x00CD - Serial Port Debug Device

-  Select active serial port device for debug.For SOC UART devices,'Debug Serial Port

-  Base' options will be ignored. 0x02:SOC UART2(Default).

-  0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device

-**/

-  UINT8                       SerialDebugPortDevice;

-

-/** Offset 0x00CE - Debug Serial Port Stride Size

-  Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default).

-  0:1, 2:4

-**/

-  UINT8                       SerialDebugPortStrideSize;

-

-/** Offset 0x00CF

-**/

-  UINT8                       UnusedUpdSpace2[1];

-

-/** Offset 0x00D0

-**/

-  UINT8                       ReservedFspmUpd[4];

+  /** Offset 0x00C8 - Debug Serial Port Base address

+    Debug serial port base address. This option will be used only when the 'Serial Port

+    Debug Device' option is set to 'External Device'. 0x00000000(Default).

+  **/

+  UINT32    SerialDebugPortAddress;

+

+  /** Offset 0x00CC - Debug Serial Port Type

+    16550 compatible debug serial port resource type. NONE means no serial port support.

+    0x02:MMIO(Default).

+    0:NONE, 1:I/O, 2:MMIO

+  **/

+  UINT8     SerialDebugPortType;

+

+  /** Offset 0x00CD - Serial Port Debug Device

+    Select active serial port device for debug.For SOC UART devices,'Debug Serial Port

+    Base' options will be ignored. 0x02:SOC UART2(Default).

+    0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device

+  **/

+  UINT8     SerialDebugPortDevice;

+

+  /** Offset 0x00CE - Debug Serial Port Stride Size

+    Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default).

+    0:1, 2:4

+  **/

+  UINT8     SerialDebugPortStrideSize;

+

+  /** Offset 0x00CF

+  **/

+  UINT8     UnusedUpdSpace2[1];

+

+  /** Offset 0x00D0

+  **/

+  UINT8     ReservedFspmUpd[4];

 } FSP_M_CONFIG;

 

 /** Fsp M UPD Configuration

 **/

 typedef struct {

+  /** Offset 0x0000

+  **/

+  FSP_UPD_HEADER    FspUpdHeader;

 

-/** Offset 0x0000

-**/

-  FSP_UPD_HEADER              FspUpdHeader;

+  /** Offset 0x00A8

+  **/

+  FSPM_ARCH_UPD     FspmArchUpd;

 

-/** Offset 0x00A8

-**/

-  FSPM_ARCH_UPD               FspmArchUpd;

+  /** Offset 0x00C8

+  **/

+  FSP_M_CONFIG      FspmConfig;

 

-/** Offset 0x00C8

-**/

-  FSP_M_CONFIG                FspmConfig;

-

-/** Offset 0x00D4

-**/

-  UINT8                       UnusedUpdSpace3[2];

+  /** Offset 0x00D4

+  **/

+  UINT8             UnusedUpdSpace3[2];

 

-/** Offset 0x00D6

-**/

-  UINT16                      UpdTerminator;

+  /** Offset 0x00D6

+  **/

+  UINT16            UpdTerminator;

 } FSPM_UPD;

 

 #pragma pack()

diff --git a/IntelFsp2Pkg/Tools/Tests/ExpectedFspsUpd.h b/IntelFsp2Pkg/Tools/Tests/ExpectedFspsUpd.h
index e2bc54a61d..5ada5c910a 100644
--- a/IntelFsp2Pkg/Tools/Tests/ExpectedFspsUpd.h
+++ b/IntelFsp2Pkg/Tools/Tests/ExpectedFspsUpd.h
@@ -5,63 +5,60 @@
 

 #pragma pack(1)

 

-

 /** Fsp S Configuration

 **/

 typedef struct {

-

-/** Offset 0x0118 - BMP Logo Data Size

-  BMP logo data buffer size. 0x00000000(Default).

-**/

-  UINT32                      LogoSize;

-

-/** Offset 0x011C - BMP Logo Data Pointer

-  BMP logo data pointer to a BMP format buffer. 0x00000000(Default).

-**/

-  UINT32                      LogoPtr;

-

-/** Offset 0x0120 - Graphics Configuration Data Pointer

-  Graphics configuration data used for initialization. 0x00000000(Default).

-**/

-  UINT32                      GraphicsConfigPtr;

-

-/** Offset 0x0124 - PCI GFX Temporary MMIO Base

-  PCI Temporary PCI GFX Base used before full PCI enumeration. 0x80000000(Default).

-**/

-  UINT32                      PciTempResourceBase;

-

-/** Offset 0x0128

-**/

-  UINT8                       UnusedUpdSpace1[3];

-

-/** Offset 0x012B

-**/

-  UINT8                       ReservedFspsUpd;

+  /** Offset 0x0118 - BMP Logo Data Size

+    BMP logo data buffer size. 0x00000000(Default).

+  **/

+  UINT32    LogoSize;

+

+  /** Offset 0x011C - BMP Logo Data Pointer

+    BMP logo data pointer to a BMP format buffer. 0x00000000(Default).

+  **/

+  UINT32    LogoPtr;

+

+  /** Offset 0x0120 - Graphics Configuration Data Pointer

+    Graphics configuration data used for initialization. 0x00000000(Default).

+  **/

+  UINT32    GraphicsConfigPtr;

+

+  /** Offset 0x0124 - PCI GFX Temporary MMIO Base

+    PCI Temporary PCI GFX Base used before full PCI enumeration. 0x80000000(Default).

+  **/

+  UINT32    PciTempResourceBase;

+

+  /** Offset 0x0128

+  **/

+  UINT8     UnusedUpdSpace1[3];

+

+  /** Offset 0x012B

+  **/

+  UINT8     ReservedFspsUpd;

 } FSP_S_CONFIG;

 

 /** Fsp S UPD Configuration

 **/

 typedef struct {

+  /** Offset 0x0000

+  **/

+  FSP_UPD_HEADER    FspUpdHeader;

 

-/** Offset 0x0000

-**/

-  FSP_UPD_HEADER              FspUpdHeader;

+  /** Offset 0x00F8

+  **/

+  FSPS_ARCH_UPD     FspsArchUpd;

 

-/** Offset 0x00F8

-**/

-  FSPS_ARCH_UPD               FspsArchUpd;

+  /** Offset 0x0118

+  **/

+  FSP_S_CONFIG      FspsConfig;

 

-/** Offset 0x0118

-**/

-  FSP_S_CONFIG                FspsConfig;

-

-/** Offset 0x012C

-**/

-  UINT8                       UnusedUpdSpace2[2];

+  /** Offset 0x012C

+  **/

+  UINT8             UnusedUpdSpace2[2];

 

-/** Offset 0x012E

-**/

-  UINT16                      UpdTerminator;

+  /** Offset 0x012E

+  **/

+  UINT16            UpdTerminator;

 } FSPS_UPD;

 

 #pragma pack()

diff --git a/IntelFsp2Pkg/Tools/Tests/ExpectedFsptUpd.h b/IntelFsp2Pkg/Tools/Tests/ExpectedFsptUpd.h
index 25b8a7d63a..48310b4fc1 100644
--- a/IntelFsp2Pkg/Tools/Tests/ExpectedFsptUpd.h
+++ b/IntelFsp2Pkg/Tools/Tests/ExpectedFsptUpd.h
@@ -5,81 +5,77 @@
 

 #pragma pack(1)

 

-

 /** Fsp T Common UPD

 **/

 typedef struct {

+  /** Offset 0x0040

+  **/

+  UINT8     Revision;

 

-/** Offset 0x0040

-**/

-  UINT8                       Revision;

+  /** Offset 0x0041

+  **/

+  UINT8     Reserved[3];

 

-/** Offset 0x0041

-**/

-  UINT8                       Reserved[3];

-

-/** Offset 0x0044

-**/

-  UINT32                      MicrocodeRegionBase;

+  /** Offset 0x0044

+  **/

+  UINT32    MicrocodeRegionBase;

 

-/** Offset 0x0048

-**/

-  UINT32                      MicrocodeRegionLength;

+  /** Offset 0x0048

+  **/

+  UINT32    MicrocodeRegionLength;

 

-/** Offset 0x004C

-**/

-  UINT32                      CodeRegionBase;

+  /** Offset 0x004C

+  **/

+  UINT32    CodeRegionBase;

 

-/** Offset 0x0050

-**/

-  UINT32                      CodeRegionLength;

+  /** Offset 0x0050

+  **/

+  UINT32    CodeRegionLength;

 

-/** Offset 0x0054

-**/

-  UINT8                       Reserved1[12];

+  /** Offset 0x0054

+  **/

+  UINT8     Reserved1[12];

 } FSPT_COMMON_UPD;

 

 /** Fsp T Configuration

 **/

 typedef struct {

-

-/** Offset 0x0060 - Chicken bytes to test Hex config

-  This option shows how to present option for 4 bytes data

-**/

-  UINT32                      ChickenBytes;

-

-/** Offset 0x0064

-**/

-  UINT8                       ReservedFsptUpd1[28];

+  /** Offset 0x0060 - Chicken bytes to test Hex config

+    This option shows how to present option for 4 bytes data

+  **/

+  UINT32    ChickenBytes;

+

+  /** Offset 0x0064

+  **/

+  UINT8     ReservedFsptUpd1[28];

 } FSP_T_CONFIG;

 

 /** Fsp T UPD Configuration

 **/

 typedef struct {

+  /** Offset 0x0000

+  **/

+  FSP_UPD_HEADER     FspUpdHeader;

 

-/** Offset 0x0000

-**/

-  FSP_UPD_HEADER              FspUpdHeader;

-

-/** Offset 0x0020

-**/

-  FSPT_ARCH_UPD               FsptArchUpd;

+  /** Offset 0x0020

+  **/

+  FSPT_ARCH_UPD      FsptArchUpd;

 

-/** Offset 0x0040

-**/

-  FSPT_COMMON_UPD             FsptCommonUpd;

+  /** Offset 0x0040

+  **/

+  FSPT_COMMON_UPD    FsptCommonUpd;

 

-/** Offset 0x0060

-**/

-  FSP_T_CONFIG                FsptConfig;

+  /** Offset 0x0060

+  **/

+  FSP_T_CONFIG       FsptConfig;

 

-/** Offset 0x0080

-**/

-  UINT8                       UnusedUpdSpace0[6];

+  /** Offset 0x0080

+  **/

+  UINT8              UnusedUpdSpace0[6];

 

-/** Offset 0x0086

-**/

-  UINT16                      UpdTerminator;

+  /** Offset 0x0086

+  **/

+  UINT16             UpdTerminator;

 } FSPT_UPD;

 

 #pragma pack()