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authorChasel, Chiu <chasel.chiu@intel.com>2018-11-22 09:44:28 +0800
committerChasel, Chiu <chasel.chiu@intel.com>2018-11-26 11:40:27 +0800
commit2098de6279033a56d27539b393e2c29cd9eb718f (patch)
tree0834014580be936fea537c96a12068b221454477
parented3951ebbd20e1e29b093c753cf051e7e4b2bfae (diff)
downloadedk2-2098de6279033a56d27539b393e2c29cd9eb718f.tar.gz
edk2-2098de6279033a56d27539b393e2c29cd9eb718f.tar.bz2
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IntelFsp2WrapperPkg: Fix line ending format issue
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1352 Fixed line ending format wrong issues on some files. Test: Verified building successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Cc: Wu Hao A <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
-rw-r--r--IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c32
-rw-r--r--IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf4
-rw-r--r--IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c24
-rw-r--r--IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf4
-rw-r--r--IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec22
5 files changed, 43 insertions, 43 deletions
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index e25854c080..fa0441ce6c 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
notify to call FspSiliconInit API.
- Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -65,7 +65,7 @@ PeiFspMemoryInit (
FspHobListPtr = NULL;
FspmUpdDataPtr = NULL;
- FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 (PcdFspmBaseAddress));
+ FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 (PcdFspmBaseAddress));
DEBUG ((DEBUG_INFO, "FspmHeaderPtr - 0x%x\n", FspmHeaderPtr));
if (FspmHeaderPtr == NULL) {
return EFI_DEVICE_ERROR;
@@ -155,20 +155,20 @@ FspmWrapperInit (
{
EFI_STATUS Status;
- Status = EFI_SUCCESS;
-
- if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
- Status = PeiFspMemoryInit ();
- ASSERT_EFI_ERROR (Status);
- } else {
- PeiServicesInstallFvInfoPpi (
- NULL,
- (VOID *)(UINTN) PcdGet32 (PcdFspmBaseAddress),
- (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFspmBaseAddress))->FvLength,
- NULL,
- NULL
- );
- }
+ Status = EFI_SUCCESS;
+
+ if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
+ Status = PeiFspMemoryInit ();
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *)(UINTN) PcdGet32 (PcdFspmBaseAddress),
+ (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFspmBaseAddress))->FvLength,
+ NULL,
+ NULL
+ );
+ }
return Status;
}
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index f4b7ef8db6..b3776a80f3 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
# register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
# notify to call FspSiliconInit API.
#
-# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -61,7 +61,7 @@
[Pcd]
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
[Sources]
FspmWrapperPeim.c
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index 69cf568380..87dd61e5c5 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -3,7 +3,7 @@
register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
notify to call FspSiliconInit API.
- Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -349,17 +349,17 @@ FspsWrapperPeimEntryPoint (
{
DEBUG ((DEBUG_INFO, "FspsWrapperPeimEntryPoint\n"));
- if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
- FspsWrapperInit ();
- } else {
- PeiServicesInstallFvInfoPpi (
- NULL,
- (VOID *)(UINTN) PcdGet32 (PcdFspsBaseAddress),
- (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFspsBaseAddress))->FvLength,
- NULL,
- NULL
- );
- }
+ if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
+ FspsWrapperInit ();
+ } else {
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *)(UINTN) PcdGet32 (PcdFspsBaseAddress),
+ (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFspsBaseAddress))->FvLength,
+ NULL,
+ NULL
+ );
+ }
return EFI_SUCCESS;
}
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
index 1e63f407cb..910286982b 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
@@ -6,7 +6,7 @@
# register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
# notify to call FspSiliconInit API.
#
-# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -68,7 +68,7 @@
[Pcd]
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
[Guids]
gFspHobGuid ## CONSUMES ## HOB
diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
index b901562bb3..96f2858fb4 100644
--- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
@@ -71,7 +71,7 @@
## Indicate the PEI memory size platform want to report
gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT32|0x40000005
- ## This is the base address of FSP-T
+ ## This is the base address of FSP-T
gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT32|0x00000300
## This PCD indicates if FSP APIs are skipped from FSP wrapper.<BR><BR>
@@ -92,17 +92,17 @@
# @Prompt Skip FSP API from FSP wrapper.
gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi|0x00000000|UINT32|0x40000009
- ## This PCD decides how Wrapper code utilizes FSP
- # 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without calling FSP API)
- # 1: API mode (FSP Wrapper will call FSP API)
- #
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0x00000001|UINT8|0x4000000A
-
+ ## This PCD decides how Wrapper code utilizes FSP
+ # 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without calling FSP API)
+ # 1: API mode (FSP Wrapper will call FSP API)
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0x00000001|UINT8|0x4000000A
+
[PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx]
- #
- ## These are the base address of FSP-M/S
- #
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0x00001000
+ #
+ ## These are the base address of FSP-M/S
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0x00001000
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x00001001
#
# To provide flexibility for platform to pre-allocate FSP UPD buffer