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| author | Heinrich Schuchardt <heinrich.schuchardt@canonical.com> | 2024-09-16 23:08:06 +0200 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-10-04 04:53:21 +0000 |
| commit | 28dd588ca80c61c4bea9294785d5d884ad3f2c41 (patch) | |
| tree | 1f2c839eec1602319a4589a7d0ae316ed4463b8b | |
| parent | 71239406652f78675499f2fbe937de03c53129cb (diff) | |
| download | edk2-28dd588ca80c61c4bea9294785d5d884ad3f2c41.tar.gz edk2-28dd588ca80c61c4bea9294785d5d884ad3f2c41.tar.bz2 edk2-28dd588ca80c61c4bea9294785d5d884ad3f2c41.zip | |
MdePkg/BaseLib: RISC-V: Add FPU CSR constants
* Define CSR fcsr
* Define bitmasks for vs and fs bit fields in the mstatus register
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
| -rw-r--r-- | MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h index a656d443a5..ea148f7810 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -20,6 +20,7 @@ #define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT)
#define MSTATUS_MPP_SHIFT 11
#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT)
+#define MSTATUS_FS 0x00006000UL
#define SSTATUS_SIE MSTATUS_SIE
#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT
@@ -76,6 +77,9 @@ #define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
+/* Floating-Point */
+#define CSR_FCSR 0x003
+
/* Supervisor Trap Setup */
#define CSR_SSTATUS 0x100
#define CSR_SEDELEG 0x102
|