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| author | Ard Biesheuvel <ardb@kernel.org> | 2023-02-09 10:01:45 +0100 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-03-16 21:14:49 +0000 |
| commit | 3b76284883df833170f741c9fb4037579635b7f2 (patch) | |
| tree | 33d91e3ac1e6dd7ee672f5f62dddd40a948daf52 | |
| parent | 82ccaaf8e77fcd461fe06f26b020254226e0f54a (diff) | |
| download | edk2-3b76284883df833170f741c9fb4037579635b7f2.tar.gz edk2-3b76284883df833170f741c9fb4037579635b7f2.tar.bz2 edk2-3b76284883df833170f741c9fb4037579635b7f2.zip | |
ArmPkg/ArmMmuLib ARM: Split off XN page descriptor bit from type field
With large page support out of the picture, we can treat bits 1 and 0 of
the page descriptor as individual valid and XN bits, instead of treating
XN as a page type. Doing so aligns the handling of the attribute with
the section descriptor layout, as well as the XN handling on AArch64,
and this is beneficial for maintainability.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
| -rw-r--r-- | ArmPkg/Include/Chipset/ArmV7Mmu.h | 8 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c | 12 |
2 files changed, 9 insertions, 11 deletions
diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/ArmV7Mmu.h index 7501ebfdf9..6a2584ceb3 100644 --- a/ArmPkg/Include/Chipset/ArmV7Mmu.h +++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -54,11 +54,9 @@ #define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)
// Translation table descriptor types
-#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)
-#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)
-#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)
-#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)
-#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_MASK (1UL << 1)
+#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 1)
+#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (1UL << 1)
// Section descriptor definitions
#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c index 9ca00c976d..12d0f4c30f 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c @@ -104,12 +104,8 @@ UpdatePageEntries ( // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
// EntryValue: values at bit positions specified by EntryMask
- EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK;
- if ((Attributes & EFI_MEMORY_XP) != 0) {
- EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN;
- } else {
- EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
- }
+ EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK;
+ EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
// Although the PI spec is unclear on this, the GCD guarantees that only
// one Attribute bit is set at a time, so the order of the conditionals below
@@ -148,6 +144,10 @@ UpdatePageEntries ( EntryValue |= TT_DESCRIPTOR_PAGE_AP_RW_RW;
}
+ if ((Attributes & EFI_MEMORY_XP) != 0) {
+ EntryValue |= TT_DESCRIPTOR_PAGE_XN_MASK;
+ }
+
// Obtain page table base
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
|