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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2016-08-15 16:40:16 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2016-08-17 13:54:13 +0800 |
| commit | 490b048b5afec06b1c78e6723530dcebd8b21612 (patch) | |
| tree | ed042ec75ad91f0387125f96a3eec568bdbce615 | |
| parent | 795c78cf190ba7ac3e7edd76e6c31b8505c2d739 (diff) | |
| download | edk2-490b048b5afec06b1c78e6723530dcebd8b21612.tar.gz edk2-490b048b5afec06b1c78e6723530dcebd8b21612.tar.bz2 edk2-490b048b5afec06b1c78e6723530dcebd8b21612.zip | |
UefiCpuPkg: MTRR_PHYSMASK.Valid should be one bit instead of 8 bits
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
| -rw-r--r-- | UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h index a4702edc73..4d4ade4df2 100644 --- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h +++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h @@ -2092,7 +2092,7 @@ typedef union { ///
/// [Bit 11] Valid Enable range mask.
///
- UINT32 V:8;
+ UINT32 V:1;
///
/// [Bits 31:12] PhysMask. MTRR address range mask.
///
|