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| author | Sheng Wei <w.sheng@intel.com> | 2023-11-15 10:31:33 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-12-07 09:43:43 +0000 |
| commit | b5f20eca8a08c2921b4844e736f97d3450144ed5 (patch) | |
| tree | 859e74251fb95d290b1d1d945f1c078d4db640a0 | |
| parent | ff4c49a5ee38d613384fb2e318d891a800d32999 (diff) | |
| download | edk2-b5f20eca8a08c2921b4844e736f97d3450144ed5.tar.gz edk2-b5f20eca8a08c2921b4844e736f97d3450144ed5.tar.bz2 edk2-b5f20eca8a08c2921b4844e736f97d3450144ed5.zip | |
UefiCpuPkg: Add macro definitions for CET feature for NASM files.
Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Wu Jiaxin <jiaxin.wu@intel.com>
Cc: Tan Dun <dun.tan@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc b/UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc new file mode 100644 index 0000000000..41c99988c9 --- /dev/null +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc @@ -0,0 +1,26 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Abstract:
+;
+; This file provides macro definitions for CET feature for NASM files.
+;
+;------------------------------------------------------------------------------
+
+%define MSR_IA32_U_CET 0x6A0
+%define MSR_IA32_S_CET 0x6A2
+%define MSR_IA32_CET_SH_STK_EN (1<<0)
+%define MSR_IA32_CET_WR_SHSTK_EN (1<<1)
+%define MSR_IA32_CET_ENDBR_EN (1<<2)
+%define MSR_IA32_CET_LEG_IW_EN (1<<3)
+%define MSR_IA32_CET_NO_TRACK_EN (1<<4)
+%define MSR_IA32_CET_SUPPRESS_DIS (1<<5)
+%define MSR_IA32_CET_SUPPRESS (1<<10)
+%define MSR_IA32_CET_TRACKER (1<<11)
+%define MSR_IA32_PL0_SSP 0x6A4
+%define MSR_IA32_INTERRUPT_SSP_TABLE_ADDR 0x6A8
+
+%define CR4_CET_BIT 23
+%define CR4_CET (1<<CR4_CET_BIT)
|