Removed duplicate PalCallStatic functions in different libraries. Moved ReadItc and InvalidateInstructionCacheRange to the BaseLib so other libs don't need .s files.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@1809 6f19259b-4bc3-4df7-8a09-765794883524

9 files changed, 139 insertions, 168 deletions

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index c1d1fa0900..e414e27399 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -5019,4 +5019,88 @@ AsmSwitchStackAndBackingStore (
   IN      VOID                      *NewBsp

   );

 

+typedef struct {

+  UINT64                            Status;

+  UINT64                            r9;

+  UINT64                            r10;

+  UINT64                            r11;

+} PAL_PROC_RETURN;

+

+//

+// IPF Specific functions

+//

+

+

+/**

+  Performs a PAL call using static calling convention.

+

+  An internal function to perform a PAL call using static calling convention.

+

+  @param  PalEntryPoint The entry point address of PAL. The address in ar.kr5

+                        would be used if this parameter were NULL on input.

+  @param  Arg1          The first argument of a PAL call.

+  @param  Arg1          The second argument of a PAL call.

+  @param  Arg1          The third argument of a PAL call.

+  @param  Arg1          The fourth argument of a PAL call.

+

+  @return The values returned in r8, r9, r10 and r11.

+

+**/

+PAL_PROC_RETURN

+PalCallStatic (

+  IN      CONST VOID                *PalEntryPoint,

+  IN      UINT64                    Arg1,

+  IN      UINT64                    Arg2,

+  IN      UINT64                    Arg3,

+  IN      UINT64                    Arg4

+  );

+

+

+/**

+  Returns the current value of ar.itc.

+

+  An internal function to return the current value of ar.itc, which is the

+  timer tick on IPF.

+

+  @return The currect value of ar.itc

+

+**/

+INT64

+IpfReadItc (

+  VOID

+  );

+

+

+/**

+  Invalidates a range of instruction cache lines in the cache coherency domain

+  of the calling CPU.

+

+  Invalidates the instruction cache lines specified by Address and Length. If

+  Address is not aligned on a cache line boundary, then entire instruction

+  cache line containing Address is invalidated. If Address + Length is not

+  aligned on a cache line boundary, then the entire instruction cache line

+  containing Address + Length -1 is invalidated. This function may choose to

+  invalidate the entire instruction cache if that is more efficient than

+  invalidating the specified range. If Length is 0, the no instruction cache

+  lines are invalidated. Address is returned.

+

+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().

+

+  @param  Address The base address of the instruction cache lines to

+                  invalidate. If the CPU is in a physical addressing mode, then

+                  Address is a physical address. If the CPU is in a virtual

+                  addressing mode, then Address is a virtual address.

+

+  @param  Length  The number of bytes to invalidate from the instruction cache.

+

+  @return Address

+

+**/

+VOID *

+EFIAPI

+IpfInvalidateInstructionCacheRange (

+  IN      VOID                      *Address,

+  IN      UINTN                     Length

+  );

+

 #endif

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa
index 02ea370151..16d5b20998 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa
@@ -1,19 +1,19 @@
 <?xml version="1.0" encoding="UTF-8"?>

-<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0">

+<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">

   <MsaHeader>

     <ModuleName>BaseCacheMaintenanceLib</ModuleName>

     <ModuleType>BASE</ModuleType>

     <GuidValue>123dd843-57c9-4158-8418-ce68b3944ce7</GuidValue>

     <Version>1.0</Version>

     <Abstract>Component description file for Base Cache Maintenance Library</Abstract>

-    <Description>Cache Maintenance Library that uses Base Library services to maintain caches.

+    <Description>Cache Maintenance Library that uses Base Library services to maintain caches.
     This library assumes there are no chipset dependencies required to maintain caches.</Description>

     <Copyright>Copyright (c) 2006, Intel Corporation</Copyright>

-    <License>All rights reserved. This program and the accompanying materials

-      are licensed and made available under the terms and conditions of the BSD License

-      which accompanies this distribution.  The full text of the license may be found at

-      http://opensource.org/licenses/bsd-license.php

-      THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+    <License>All rights reserved. This program and the accompanying materials
+      are licensed and made available under the terms and conditions of the BSD License
+      which accompanies this distribution.  The full text of the license may be found at
+      http://opensource.org/licenses/bsd-license.php
+      THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
       WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>

     <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION   0x00000052</Specification>

   </MsaHeader>

@@ -38,8 +38,6 @@
     <Filename SupArchList="X64">x86Cache.c</Filename>

     <Filename SupArchList="EBC">EbcCache.c</Filename>

     <Filename SupArchList="IPF">IpfCache.c</Filename>

-    <Filename SupArchList="IPF">Ipf/Cpu.s</Filename>

-    <Filename SupArchList="IPF">Ipf/PalCallStatic.s</Filename>

   </SourceFiles>

   <PackageDependencies>

     <Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
index 7e96d9b76a..0c6f0e4dc8 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
@@ -12,21 +12,6 @@
 

 **/

 

-typedef struct {

-  UINT64                            Status;

-  UINT64                            r9;

-  UINT64                            r10;

-  UINT64                            r11;

-} PAL_PROC_RETURN;

-

-PAL_PROC_RETURN

-PalCallStatic (

-  IN      CONST VOID                *PalEntryPoint,

-  IN      UINT64                    Arg1,

-  IN      UINT64                    Arg2,

-  IN      UINT64                    Arg3,

-  IN      UINT64                    Arg4

-  );

 

 /**

   Invalidates the entire instruction cache in cache coherency domain of the

@@ -46,6 +31,41 @@ InvalidateInstructionCache (
 }

 

 /**

+  Invalidates a range of instruction cache lines in the cache coherency domain

+  of the calling CPU.

+

+  Invalidates the instruction cache lines specified by Address and Length. If

+  Address is not aligned on a cache line boundary, then entire instruction

+  cache line containing Address is invalidated. If Address + Length is not

+  aligned on a cache line boundary, then the entire instruction cache line

+  containing Address + Length -1 is invalidated. This function may choose to

+  invalidate the entire instruction cache if that is more efficient than

+  invalidating the specified range. If Length is 0, the no instruction cache

+  lines are invalidated. Address is returned.

+

+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().

+

+  @param  Address The base address of the instruction cache lines to

+                  invalidate. If the CPU is in a physical addressing mode, then

+                  Address is a physical address. If the CPU is in a virtual

+                  addressing mode, then Address is a virtual address.

+

+  @param  Length  The number of bytes to invalidate from the instruction cache.

+

+  @return Address

+

+**/

+VOID *

+EFIAPI

+InvalidateInstructionCacheRange (

+  IN      VOID                      *Address,

+  IN      UINTN                     Length

+  )

+{

+  return IpfInvalidateInstructionCacheRange (Address, Length);

+}

+

+/**

   Writes Back and Invalidates the entire data cache in cache coherency domain

   of the calling CPU.

 

diff --git a/MdePkg/Library/BaseLib/BaseLib.msa b/MdePkg/Library/BaseLib/BaseLib.msa
index 5d24dcf425..52dbf7304a 100644
--- a/MdePkg/Library/BaseLib/BaseLib.msa
+++ b/MdePkg/Library/BaseLib/BaseLib.msa
@@ -1,4 +1,4 @@
-<?xml version="1.0" encoding="UTF-8"?>

+<?xml version="1.0" encoding="UTF-8"?>

 <!--

 Copyright (c) 2006, Intel Corporation

 All rights reserved. This program and the accompanying materials

@@ -425,6 +425,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
     <Filename SupArchList="IPF">Ipf/CpuFlushTlb.s</Filename>

     <Filename SupArchList="IPF">Ipf/GetInterruptState.s</Filename>

     <Filename SupArchList="IPF">Ipf/Non-existing.c</Filename>

+    <Filename SupArchList="IPF">Ipf/InvalidateInstructionCacheRange.s</Filename>

+    <Filename SupArchList="IPF">Ipf/ReadItc.s</Filename>

     

     <Filename SupArchList="EBC">Math64.c</Filename>

     <Filename SupArchList="EBC">Unaligned.c</Filename>

diff --git a/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c b/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
index 0097d991eb..49bd06b8c2 100644
--- a/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
+++ b/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
@@ -19,21 +19,6 @@
 #pragma intrinsic (__break)

 #pragma intrinsic (__mfa)

 

-typedef struct {

-  UINT64                            Status;

-  UINT64                            r9;

-  UINT64                            r10;

-  UINT64                            r11;

-} PAL_PROC_RETURN;

-

-PAL_PROC_RETURN

-PalCallStatic (

-  IN      CONST VOID                *PalEntryPoint,

-  IN      UINT64                    Arg1,

-  IN      UINT64                    Arg2,

-  IN      UINT64                    Arg3,

-  IN      UINT64                    Arg4

-  );

 

 /**

   Generates a breakpoint on the CPU.

diff --git a/MdePkg/Library/BaseTimerLibLocalApic/BaseTimerLibLocalApic.msa b/MdePkg/Library/BaseTimerLibLocalApic/BaseTimerLibLocalApic.msa
index 144a6f19bd..f24d6daabe 100644
--- a/MdePkg/Library/BaseTimerLibLocalApic/BaseTimerLibLocalApic.msa
+++ b/MdePkg/Library/BaseTimerLibLocalApic/BaseTimerLibLocalApic.msa
@@ -1,19 +1,19 @@
 <?xml version="1.0" encoding="UTF-8"?>

-<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0">

+<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">

   <MsaHeader>

     <ModuleName>BaseTimerLibLocalApic</ModuleName>

     <ModuleType>BASE</ModuleType>

     <GuidValue>b5a05743-9b71-489b-a0ed-a0eb3950d23b</GuidValue>

     <Version>1.0</Version>

     <Abstract>Component description file for Baser Timer Library</Abstract>

-    <Description>Timer Library that only uses CPU resources to provide calibrated

+    <Description>Timer Library that only uses CPU resources to provide calibrated
       delays on IA-32 and x64.</Description>

     <Copyright>Copyright (c) 2006, Intel Corporation.</Copyright>

-    <License>All rights reserved. This program and the accompanying materials

-      are licensed and made available under the terms and conditions of the BSD License

-      which accompanies this distribution.  The full text of the license may be found at

-      http://opensource.org/licenses/bsd-license.php

-      THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+    <License>All rights reserved. This program and the accompanying materials
+      are licensed and made available under the terms and conditions of the BSD License
+      which accompanies this distribution.  The full text of the license may be found at
+      http://opensource.org/licenses/bsd-license.php
+      THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
       WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>

     <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION   0x00000052</Specification>

   </MsaHeader>

@@ -39,8 +39,6 @@
   <SourceFiles>

     <Filename SupArchList="IA32">x86TimerLib.c</Filename>

     <Filename SupArchList="X64">x86TimerLib.c</Filename>

-    <Filename SupArchList="IPF">Ipf/PalCallStatic.s</Filename>

-    <Filename SupArchList="IPF">Ipf/ReadItc.s</Filename>

     <Filename SupArchList="IPF">Ipf/IpfTimerLib.c</Filename>

     <Filename SupArchList="EBC">Ebc/EbcTimerLib.c</Filename>

   </SourceFiles>

diff --git a/MdePkg/Library/BaseTimerLibLocalApic/Ipf/IpfTimerLib.c b/MdePkg/Library/BaseTimerLibLocalApic/Ipf/IpfTimerLib.c
index 12803d9fa4..65b58bc549 100644
--- a/MdePkg/Library/BaseTimerLibLocalApic/Ipf/IpfTimerLib.c
+++ b/MdePkg/Library/BaseTimerLibLocalApic/Ipf/IpfTimerLib.c
@@ -18,50 +18,8 @@
 

 **/

 

-typedef struct {

-  UINT64                            Status;

-  UINT64                            r9;

-  UINT64                            r10;

-  UINT64                            r11;

-} PAL_PROC_RETURN;

 

-/**

-  Performs a PAL call using static calling convention.

-

-  An internal function to perform a PAL call using static calling convention.

-

-  @param  PalEntryPoint The entry point address of PAL. The address in ar.kr5

-                        would be used if this parameter were NULL on input.

-  @param  Arg1          The first argument of a PAL call.

-  @param  Arg1          The second argument of a PAL call.

-  @param  Arg1          The third argument of a PAL call.

-  @param  Arg1          The fourth argument of a PAL call.

-

-  @return The values returned in r8, r9, r10 and r11.

-

-**/

-PAL_PROC_RETURN

-PalCallStatic (

-  IN      CONST VOID                *PalEntryPoint,

-  IN      UINT64                    Arg1,

-  IN      UINT64                    Arg2,

-  IN      UINT64                    Arg3,

-  IN      UINT64                    Arg4

-  );

 

-/**

-  Returns the current value of ar.itc.

-

-  An internal function to return the current value of ar.itc, which is the

-  timer tick on IPF.

-

-  @return The currect value of ar.itc

-

-**/

-INT64

-InternalIpfReadItc (

-  VOID

-  );

 

 /**

   Performs a delay measured as number of ticks.

@@ -83,14 +41,14 @@ InternalIpfDelay (
   //

   // The target timer count is calculated here

   //

-  Ticks = InternalIpfReadItc () + Delay;

+  Ticks = IpfReadItc () + Delay;

 

   //

   // Wait until time out

   // Delay > 2^63 could not be handled by this function

   // Timer wrap-arounds are handled correctly by this function

   //

-  while (Ticks - InternalIpfReadItc () >= 0);

+  while (Ticks - IpfReadItc () >= 0);

 }

 

 /**

@@ -159,7 +117,7 @@ GetPerformanceCounter (
   VOID

   )

 {

-  return InternalIpfReadItc ();

+  return IpfReadItc ();

 }

 

 /**

diff --git a/MdePkg/Library/BaseTimerLibLocalApic/Ipf/PalCallStatic.s b/MdePkg/Library/BaseTimerLibLocalApic/Ipf/PalCallStatic.s
deleted file mode 100644
index c21d7427f9..0000000000
--- a/MdePkg/Library/BaseTimerLibLocalApic/Ipf/PalCallStatic.s
+++ /dev/null
@@ -1,48 +0,0 @@
-/// @file

-///   Contains an implementation of CallPalProcStatic on Itanium-based

-///   architecture.

-///

-/// Copyright (c) 2006, Intel Corporation

-/// All rights reserved. This program and the accompanying materials

-/// are licensed and made available under the terms and conditions of the BSD License

-/// which accompanies this distribution.  The full text of the license may be found at

-/// http://opensource.org/licenses/bsd-license.php

-///

-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-///

-/// Module Name:  PalCallStatic.s

-///

-///

-

-.auto

-.text

-

-.proc   PalCallStatic

-.type   PalCallStatic, @function

-.regstk 5, 0, 0, 0

-PalCallStatic::

-        cmp.eq              p15 = in0, r0

-        mov                 r31 = in4

-        mov                 r8  = ip

-

-(p15)   mov                 in0 = ar.k5

-        add                 r8  = (_PalProcReturn - PalCallStatic), r8

-        mov                 r30 = in3

-

-        mov                 in4 = psr

-        mov                 in3 = b0

-        mov                 b7  = in0

-

-        rsm                 1 << 14                 // Disable interrupts

-        mov                 r29 = in2

-        mov                 r28 = in1

-

-        mov                 b0  = r8

-        br.cond.sptk.many   b7

-

-_PalProcReturn:

-        mov                 psr.l = in4

-        mov                 b0  = in3

-        br.ret.sptk.many    b0

-.endp   PalCallStatic

diff --git a/MdePkg/Library/BaseTimerLibLocalApic/Ipf/ReadItc.s b/MdePkg/Library/BaseTimerLibLocalApic/Ipf/ReadItc.s
deleted file mode 100644
index ea94b670e7..0000000000
--- a/MdePkg/Library/BaseTimerLibLocalApic/Ipf/ReadItc.s
+++ /dev/null
@@ -1,26 +0,0 @@
-/// @file

-///   Contains an implementation of InternalIpfReadItc () on Itanium-based

-///   architecture.

-///

-/// Copyright (c) 2006, Intel Corporation

-/// All rights reserved. This program and the accompanying materials

-/// are licensed and made available under the terms and conditions of the BSD License

-/// which accompanies this distribution.  The full text of the license may be found at

-/// http://opensource.org/licenses/bsd-license.php

-///

-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-///

-/// Module Name:  ReadItc.s

-///

-///

-

-.auto

-.text

-

-.proc   InternalIpfReadItc

-.type   InternalIpfReadItc, @function

-InternalIpfReadItc::

-        mov                 r8  = ar.itc

-        br.ret.sptk.many    b0

-.endp   InternalIpfReadItc