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| author | Abner Chang <abner.chang@hpe.com> | 2020-02-28 22:19:45 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-04-03 17:09:12 +0000 |
| commit | e576dfadd65c3046420ab3ffac4b0388883115c2 (patch) | |
| tree | 80f36054948b252c80319b9cffe82b4bdd533a59 | |
| parent | 9025a014f9d9a7e1bab3db8848bdb0e911480b0e (diff) | |
| download | edk2-e576dfadd65c3046420ab3ffac4b0388883115c2.tar.gz edk2-e576dfadd65c3046420ab3ffac4b0388883115c2.tar.bz2 edk2-e576dfadd65c3046420ab3ffac4b0388883115c2.zip | |
MdePkg/Include: Add RISC-V related definitions EDK2 CI.
HTTP/PXE boot RISC-V related definitions for EDK2 CI.
BZ:2562:
https://bugzilla.tianocore.org/show_bug.cgi?id=2562
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
| -rw-r--r-- | MdePkg/Include/IndustryStandard/Dhcp.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/MdePkg/Include/IndustryStandard/Dhcp.h b/MdePkg/Include/IndustryStandard/Dhcp.h index f41f9f2f5b..121c48c42d 100644 --- a/MdePkg/Include/IndustryStandard/Dhcp.h +++ b/MdePkg/Include/IndustryStandard/Dhcp.h @@ -3,6 +3,7 @@ They are used to carry additional information and parameters in DHCP messages.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -266,11 +267,17 @@ typedef enum { #define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE
#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE
#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE
+#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for PXE
+#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for PXE
+#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for PXE
#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http
#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http
#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http
#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http
#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http
+#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot from http
+#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot from http
+#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boot from http
#endif
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