ArmPkg: Tidy GIC code before changes.

This change is purely cosmetic, to tidy some code before change.
Mods involve:
    Re-order #includes
    Reformat comments.
    Use ns consistently (always "100ns" not sometimes "100 nS")
    Split overlength code lines.
    Make protocol functions STATIC.
    Remove "Horor vacui" comments.
    Rationalize GIC register address calculations
    Replace explicit test and assert with ASSERT_EFI_ERROR.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

1 files changed, 36 insertions, 24 deletions

diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
index b9ecd5543a..3d5d034efb 100644
--- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
@@ -2,7 +2,7 @@
 

 Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>

 Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>

-Portions copyright (c) 2011-2016, ARM Ltd. All rights reserved.<BR>

+Portions copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR>

 

 This program and the accompanying materials

 are licensed and made available under the terms and conditions of the BSD License

@@ -43,6 +43,7 @@ STATIC UINT32 mGicDistributorBase;
   @retval EFI_UNSUPPORTED   Source interrupt is not supported

 

 **/

+STATIC

 EFI_STATUS

 EFIAPI

 GicV2EnableInterruptSource (

@@ -70,6 +71,7 @@ GicV2EnableInterruptSource (
   @retval EFI_UNSUPPORTED   Source interrupt is not supported

 

 **/

+STATIC

 EFI_STATUS

 EFIAPI

 GicV2DisableInterruptSource (

@@ -98,6 +100,7 @@ GicV2DisableInterruptSource (
   @retval EFI_UNSUPPORTED   Source interrupt is not supported

 

 **/

+STATIC

 EFI_STATUS

 EFIAPI

 GicV2GetInterruptSourceState (

@@ -127,6 +130,7 @@ GicV2GetInterruptSourceState (
   @retval EFI_UNSUPPORTED   Source interrupt is not supported

 

 **/

+STATIC

 EFI_STATUS

 EFIAPI

 GicV2EndOfInterrupt (

@@ -147,13 +151,15 @@ GicV2EndOfInterrupt (
   EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.

 

   @param  InterruptType    Defines the type of interrupt or exception that

-                           occurred on the processor.This parameter is processor architecture specific.

+                           occurred on the processor.This parameter is

+                           processor architecture specific.

   @param  SystemContext    A pointer to the processor context when

                            the interrupt occurred on the processor.

 

   @return None

 

 **/

+STATIC

 VOID

 EFIAPI

 GicV2IrqInterruptHandler (

@@ -166,9 +172,10 @@ GicV2IrqInterruptHandler (
 

   GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);

 

-  // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).

+  // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the

+  // number of interrupt (ie: Spurious interrupt).

   if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {

-    // The special interrupt do not need to be acknowledge

+    // The special interrupts do not need to be acknowledged

     return;

   }

 

@@ -177,14 +184,12 @@ GicV2IrqInterruptHandler (
     // Call the registered interrupt handler.

     InterruptHandler (GicInterrupt, SystemContext);

   } else {

-    DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));

+    DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));

     GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);

   }

 }

 

-//

 // The protocol instance produced by this driver

-//

 EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {

   RegisterInterruptSource,

   GicV2EnableInterruptSource,

@@ -196,12 +201,13 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
 /**

   Shutdown our hardware

 

-  DXE Core will disable interrupts and turn off the timer and disable interrupts

-  after all the event handlers have run.

+  DXE Core will disable interrupts and turn off the timer and disable

+  interrupts after all the event handlers have run.

 

   @param[in]  Event   The Event that is being processed

   @param[in]  Context Event Context

 **/

+STATIC

 VOID

 EFIAPI

 GicV2ExitBootServicesEvent (

@@ -256,7 +262,8 @@ GicV2DxeInitialize (
   UINTN                   RegShift;

   UINT32                  CpuTarget;

 

-  // Make sure the Interrupt Controller Protocol is not already installed in the system.

+  // Make sure the Interrupt Controller Protocol is not already installed in

+  // the system.

   ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);

 

   mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase);

@@ -276,25 +283,27 @@ GicV2DxeInitialize (
       );

   }

 

-  //

   // Targets the interrupts to the Primary Cpu

-  //

-

-  // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading

-  // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each

-  // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.

-  // More Info in the GIC Specification about "Interrupt Processor Targets Registers"

-  //

-  // Read the first Interrupt Processor Targets Register (that corresponds to the 4

-  // first SGIs)

+

+  // Only Primary CPU will run this code. We can identify our GIC CPU ID by

+  // reading the GIC Distributor Target register. The 8 first GICD_ITARGETSRn

+  // are banked to each connected CPU. These 8 registers hold the CPU targets

+  // fields for interrupts 0-31. More Info in the GIC Specification about

+  // "Interrupt Processor Targets Registers"

+

+  // Read the first Interrupt Processor Targets Register (that corresponds to

+  // the 4 first SGIs)

   CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);

 

-  // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value

-  // is 0 when we run on a uniprocessor platform.

+  // The CPU target is a bit field mapping each CPU to a GIC CPU Interface.

+  // This value is 0 when we run on a uniprocessor platform.

   if (CpuTarget != 0) {

     // The 8 first Interrupt Processor Targets Registers are read-only

     for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {

-      MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);

+      MmioWrite32 (

+        mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),

+        CpuTarget

+        );

     }

   }

 

@@ -311,7 +320,10 @@ GicV2DxeInitialize (
   ArmGicEnableDistributor (mGicDistributorBase);

 

   Status = InstallAndRegisterInterruptService (

-          &gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent);

+             &gHardwareInterruptV2Protocol,

+             GicV2IrqInterruptHandler,

+             GicV2ExitBootServicesEvent

+             );

 

   return Status;

 }