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| author | Sami Mujawar <sami.mujawar@arm.com> | 2019-02-22 19:43:28 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2019-02-26 08:38:42 +0100 |
| commit | 1bb76029eff4993b31dbbb19acd86d1c8ad4933f (patch) | |
| tree | 8322f2fcb86ebefb5d7aaebb1b88a25c71ee8a96 /ArmPkg/Drivers/ArmGic/GicV3 | |
| parent | 1342d7679e10b45f0702679b521513804205cdaf (diff) | |
| download | edk2-1bb76029eff4993b31dbbb19acd86d1c8ad4933f.tar.gz edk2-1bb76029eff4993b31dbbb19acd86d1c8ad4933f.tar.bz2 edk2-1bb76029eff4993b31dbbb19acd86d1c8ad4933f.zip | |
ArmPkg: Fix writes to GICv3 GICD_IROUTER<n> reg
According to ARM Generic Interrupt Controller Architecture
Specification, GIC architecture version 3.0 and version 4.0,
GICD_IROUTER<n> is a 64-bit register.
Fixed code to use 64 bit MMIO write operations so that the
Aff3 value (bits [39:32]) is written to GICD_IROUTER<n>.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reported-by: Carl van Schaik <carl@cog.systems>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'ArmPkg/Drivers/ArmGic/GicV3')
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index 1558db3171..67c74f7965 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -1,6 +1,6 @@ /** @file
*
-* Copyright (c) 2011-2017, ARM Limited. All rights reserved.
+* Copyright (c) 2011-2018, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -467,7 +467,7 @@ GicV3DxeInitialize ( // Route the SPIs to the primary CPU. SPIs start at the INTID 32
for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
- MmioWrite32 (
+ MmioWrite64 (
mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),
CpuTarget
);
|