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| author | Ming Huang <ming.huang@linaro.org> | 2018-10-29 12:57:08 +0800 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-11-07 16:19:22 +0100 |
| commit | b66e38b50134728614bbca2a2449a36a5dc2bd91 (patch) | |
| tree | 643c748b36fade13e8f8c9754619cac247e50e1b /ArmPkg/Drivers/ArmGic | |
| parent | 0adc6eae9480ca1ae7ac01e239e09b58e447e467 (diff) | |
| download | edk2-b66e38b50134728614bbca2a2449a36a5dc2bd91.tar.gz edk2-b66e38b50134728614bbca2a2449a36a5dc2bd91.tar.bz2 edk2-b66e38b50134728614bbca2a2449a36a5dc2bd91.zip | |
ArmPkg/ArmGicDxe: Fix GICv3 interrupt routing mode bug
Setting GICD_IROUTERn.IRM and GICD_IROUTERn.{Aff3,Aff2,Aff1,Aff0}
at the same time is nonsensical (see 8.9.13 in the GICv3 spec, which
says of GICD_IROUTERn.IRM that "When this bit is set to 1,
GICD_IROUTER<n>.{Aff3,Aff2,Aff1,Aff0} are UNKNOWN"). There is also no
guarantee that IRM is implemented (see GICD_TYPER.No1N which indicates
whether the implementation supports this or not).
Let's thus not set this bit, as we want all SPIs to be delivered to the
same CPU, and not be broadcast to all of them.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'ArmPkg/Drivers/ArmGic')
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index 01154848f4..1558db3171 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -469,7 +469,7 @@ GicV3DxeInitialize ( for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
MmioWrite32 (
mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),
- CpuTarget | ARM_GICD_IROUTER_IRM
+ CpuTarget
);
}
}
|