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authorOlivier Martin <olivier.martin@arm.com>2014-06-03 16:42:18 +0000
committeroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2014-06-03 16:42:18 +0000
commitec17f0f56a1b6345baef5d73e6ed7bc2016f4b78 (patch)
tree679af189e6de724c3f925ec058019bb3346914e6 /ArmPkg/Drivers/CpuDxe/AArch64
parent27331bff97f4fb36bee3aad8e010576ca641304e (diff)
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ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt handling
See section "2.1 The need to align SP to a multiple of 8 at conforming call sites" in "Advisory Note. SP must be 8-byte aligned on entry to AAPCS-conforming functions" Source: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0046b/IHI0046B_ABI_Advisory_1.pdf Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15553 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Drivers/CpuDxe/AArch64')
-rw-r--r--ArmPkg/Drivers/CpuDxe/AArch64/Exception.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c b/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c
index 0cd80bb722..59246f80bc 100644
--- a/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c
+++ b/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c
@@ -133,7 +133,7 @@ InitializeExceptions (
// AArch64 alignment? The Vector table must be 2k-byte aligned (bottom 11 bits zero)?
//DEBUG ((EFI_D_ERROR, "vbar set addr: 0x%016lx\n",(UINTN)ExceptionHandlersStart));
- //ASSERT(((UINTN)ExceptionHandlersStart & ((1 << 11)-1)) == 0);
+ //ASSERT(((UINTN)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
// We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.
ArmWriteVBar ((UINTN)ExceptionHandlersStart);