ArmPkg/ArmPlatformPkg: position vectors relative to base

We currently rely on .align directives to ensure that each exception
vector entry is the appropriate offset from the vector base address.

This is slightly fragile, as were an entry to become too large (greater
than 32 A64 instructions), all following entries would be silently
shifted until they meet the next alignment boundary. Thus we might
execute the wrong code in response to an exception.

To prevent this, introduce a new macro, VECTOR_ENTRY, that uses .org
directives to position each entry at the precise required offset from
the base of a vector. A vector entry which is too large will trigger a
build failure rather than a runtime failure which is difficult to debug.

For consistency, the base and end of each vector is similarly annotated,
with VECTOR_BASE and VECTOR_END, which provide the necessary alignment
and symbol exports. The now redundant directives and labels are removed.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18904 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 20 insertions, 20 deletions

diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S b/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S
index ca6c9a1522..edf9973494 100644
--- a/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S
+++ b/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S
@@ -12,6 +12,7 @@
 //

 //------------------------------------------------------------------------------

 

+#include <Chipset/AArch64.h>

 #include <Library/PcdLib.h>

 #include <AsmMacroIoLibV8.h>

 

@@ -95,14 +96,12 @@
   UINT64  Padding;0x328   // Required for stack alignment

 */

 

-GCC_ASM_EXPORT(ExceptionHandlersStart)

 GCC_ASM_EXPORT(ExceptionHandlersEnd)

 GCC_ASM_EXPORT(CommonExceptionEntry)

 GCC_ASM_EXPORT(AsmCommonExceptionEntry)

 GCC_ASM_EXPORT(CommonCExceptionHandler)

 

 .text

-.align 11

 

 #define GP_CONTEXT_SIZE    (32 *  8)

 #define FP_CONTEXT_SIZE    (32 * 16)

@@ -160,84 +159,85 @@ GCC_ASM_EXPORT(CommonCExceptionHandler)
 // This code gets copied to the ARM vector table

 // VectorTableStart - VectorTableEnd gets copied

 //

-ASM_PFX(ExceptionHandlersStart):

+VECTOR_BASE(ExceptionHandlersStart)

 

 //

 // Current EL with SP0 : 0x0 - 0x180

 //

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SYNC)

 ASM_PFX(SynchronousExceptionSP0):

   b   ASM_PFX(SynchronousExceptionEntry)

 

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_IRQ)

 ASM_PFX(IrqSP0):

   b   ASM_PFX(IrqEntry)

 

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_FIQ)

 ASM_PFX(FiqSP0):

   b   ASM_PFX(FiqEntry)

 

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SERR)

 ASM_PFX(SErrorSP0):

   b   ASM_PFX(SErrorEntry)

 

 //

 // Current EL with SPx: 0x200 - 0x380

 //

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC)

 ASM_PFX(SynchronousExceptionSPx):

   b   ASM_PFX(SynchronousExceptionEntry)

 

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ)

 ASM_PFX(IrqSPx):

   b   ASM_PFX(IrqEntry)

 

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ)

 ASM_PFX(FiqSPx):

   b   ASM_PFX(FiqEntry)

 

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR)

 ASM_PFX(SErrorSPx):

   b   ASM_PFX(SErrorEntry)

 

 //

 // Lower EL using AArch64 : 0x400 - 0x580

 //

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SYNC)

 ASM_PFX(SynchronousExceptionA64):

   b   ASM_PFX(SynchronousExceptionEntry)

 

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_IRQ)

 ASM_PFX(IrqA64):

   b   ASM_PFX(IrqEntry)

 

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_FIQ)

 ASM_PFX(FiqA64):

   b   ASM_PFX(FiqEntry)

 

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SERR)

 ASM_PFX(SErrorA64):

   b   ASM_PFX(SErrorEntry)

 

 //

-// Lower EL using AArch32 : 0x0 - 0x180

+// Lower EL using AArch32 : 0x600 - 0x780

 //

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SYNC)

 ASM_PFX(SynchronousExceptionA32):

   b   ASM_PFX(SynchronousExceptionEntry)

 

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_IRQ)

 ASM_PFX(IrqA32):

   b   ASM_PFX(IrqEntry)

 

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_FIQ)

 ASM_PFX(FiqA32):

   b   ASM_PFX(FiqEntry)

 

-.align 7

+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SERR)

 ASM_PFX(SErrorA32):

   b   ASM_PFX(SErrorEntry)

 

+VECTOR_END(ExceptionHandlersStart)

 

 #undef  REG_PAIR

 #undef  REG_ONE