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| author | Olivier Martin <olivier.martin@arm.com> | 2014-06-03 16:37:29 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-06-03 16:37:29 +0000 |
| commit | 01674afdad3460f1c1f5f7a941c4c5895c8c3f86 (patch) | |
| tree | f0a06e07830cb71b1052fd2976da5420b1966106 /ArmPkg/Include/Chipset/AArch64.h | |
| parent | 8b7f930a14d1d5480b707b60323e95450e7361c1 (diff) | |
| download | edk2-01674afdad3460f1c1f5f7a941c4c5895c8c3f86.tar.gz edk2-01674afdad3460f1c1f5f7a941c4c5895c8c3f86.tar.bz2 edk2-01674afdad3460f1c1f5f7a941c4c5895c8c3f86.zip | |
ArmPkg/ArmLib: Drain Write Buffer before DCache maintenance operations.
Cache maintenance operations by Set/Way require that the Write Buffer
be drained before the cache is flushed. Without that, the flush can
miss the most recent values written as they are still "pipelined".
That has unfortunate consequences, especially where code is being
copied to RAM.
The fix is to add DSB instructions before the affected operations.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15551 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Include/Chipset/AArch64.h')
0 files changed, 0 insertions, 0 deletions