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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2015-11-12 11:40:57 +0000
committerabiesheuvel <abiesheuvel@Edk2>2015-11-12 11:40:57 +0000
commit0c9a522f28772049ae37c85b8ae589a98d2d3b81 (patch)
tree3b39f63cdbe3062f94c4a2e6fafbb98ff894c54c /ArmPkg/Include/Chipset/AArch64Mmu.h
parent83586b5d50f10a57d02233c066a92cb88718f5a1 (diff)
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ArmPkg/ArmLib: mark all cached mappings as (inner) shareable
Mark all cached memory mappings as shareable (or inner shareable on AArch64) so that our view of memory is kept coherent by the hardware. This is relevant for things like coherent DMA and virtualization (where a guest may migrate to another core) but in general, since UEFI on ARM is mostly used in a context where the secure firmware and possibly a secure OS are already up and running, it is best to refrain from using any non-shareable mappings. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18778 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Include/Chipset/AArch64Mmu.h')
-rw-r--r--ArmPkg/Include/Chipset/AArch64Mmu.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h
index 22e492d61d..3c3df6d983 100644
--- a/ArmPkg/Include/Chipset/AArch64Mmu.h
+++ b/ArmPkg/Include/Chipset/AArch64Mmu.h
@@ -74,6 +74,11 @@
#define TT_NS BIT5
#define TT_AF BIT10
+#define TT_SH_NON_SHAREABLE (0x0 << 8)
+#define TT_SH_OUTER_SHAREABLE (0x2 << 8)
+#define TT_SH_INNER_SHAREABLE (0x3 << 8)
+#define TT_SH_MASK (0x3 << 8)
+
#define TT_PXN_MASK BIT53
#define TT_UXN_MASK BIT54 // EL1&0
#define TT_XN_MASK BIT54 // EL2 / EL3