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| author | Ronald Cron <Ronald.Cron@arm.com> | 2015-02-26 10:57:27 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@Edk2> | 2015-02-26 10:57:27 +0000 |
| commit | 7aec2926b926ad90d09fb026af0ee04c4c831237 (patch) | |
| tree | b4e9bc435f6168a08261387f29a68e07e2f4030e /ArmPkg/Include/Chipset/ArmV7.h | |
| parent | cae7af275ed6bc8873fb5469b861f37b59685e07 (diff) | |
| download | edk2-7aec2926b926ad90d09fb026af0ee04c4c831237.tar.gz edk2-7aec2926b926ad90d09fb026af0ee04c4c831237.tar.bz2 edk2-7aec2926b926ad90d09fb026af0ee04c4c831237.zip | |
ArmPlatformPkg/ArmJunoDxe: Set the platform dependent FDT device path
The MIDR register of the CPU on which the UEFI firmware is running on
is used to infer if the platform is a Juno r0 or a Juno r1. The right
device path to the platform FDT is then stored in the
"gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths" dynamic PCD.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <Ronald.Cron@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16939 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Include/Chipset/ArmV7.h')
| -rw-r--r-- | ArmPkg/Include/Chipset/ArmV7.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h index ceb32170ed..4fb06636e0 100644 --- a/ArmPkg/Include/Chipset/ArmV7.h +++ b/ArmPkg/Include/Chipset/ArmV7.h @@ -1,7 +1,7 @@ /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -75,12 +75,15 @@ #define SCR_AW (1 << 5)
// MIDR - Main ID Register definitions
+#define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMv8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A15 0xC0F
+#define ARM_CPU_TYPE_A12 0xC0D
#define ARM_CPU_TYPE_A9 0xC09
+#define ARM_CPU_TYPE_A7 0xC07
#define ARM_CPU_TYPE_A5 0xC05
#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
|