ArmPkg: update InvalidateInstructionCacheRange to flush only to PoU

This patch updates the ArmPkg variant of InvalidateInstructionCacheRange to
flush the data cache only to the point of unification (PoU). This improves
performance and also allows invalidation in scenarios where it would be
inappropriate to flush to the point of coherency (like when executing code
from L2 configured as cache-as-ram).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>

Added AARCH64 and ARM/GCC implementations of the above.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19174 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 7 insertions, 1 deletions

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 9622444ec6..85fa1f600b 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -183,12 +183,18 @@ ArmInvalidateDataCacheEntryByMVA (
 

 VOID

 EFIAPI

-ArmCleanDataCacheEntryByMVA (

+ArmCleanDataCacheEntryToPoUByMVA(

   IN  UINTN   Address

   );

 

 VOID

 EFIAPI

+ArmCleanDataCacheEntryByMVA(

+IN  UINTN   Address

+);

+

+VOID

+EFIAPI

 ArmCleanInvalidateDataCacheEntryByMVA (

   IN  UINTN   Address

   );