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| author | Rebecca Cran <rebecca@nuviainc.com> | 2021-12-15 20:46:31 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-01-30 11:04:41 +0000 |
| commit | 103fa647d159e3d76be2634d2653c2d215dd0d46 (patch) | |
| tree | 74716bf923600dcb97249524888b43da9c602a03 /ArmPkg/Include | |
| parent | ba79becd553c4d9118fafcaedef4d36f1cb9c851 (diff) | |
| download | edk2-103fa647d159e3d76be2634d2653c2d215dd0d46.tar.gz edk2-103fa647d159e3d76be2634d2653c2d215dd0d46.tar.bz2 edk2-103fa647d159e3d76be2634d2653c2d215dd0d46.zip | |
ArmPkg: Replace CoreId and ClusterId with Mpidr in ARM_CORE_INFO struct
Remove the ClusterId and CoreId fields in the ARM_CORE_INFO structure in
favor of a new Mpidr field. Update code in
ArmPlatformPkg/PrePeiCore/MainMPCore and ArmPlatformPkg/PrePi/MainMPCore.c
to use the new field and call new macros GET_MPIDR_AFF0 and GET_MPIDR_AFF1
instead.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Diffstat (limited to 'ArmPkg/Include')
| -rw-r--r-- | ArmPkg/Include/Guid/ArmMpCoreInfo.h | 3 | ||||
| -rw-r--r-- | ArmPkg/Include/Library/ArmLib.h | 4 |
2 files changed, 5 insertions, 2 deletions
diff --git a/ArmPkg/Include/Guid/ArmMpCoreInfo.h b/ArmPkg/Include/Guid/ArmMpCoreInfo.h index 06f9326ca0..43f0848e78 100644 --- a/ArmPkg/Include/Guid/ArmMpCoreInfo.h +++ b/ArmPkg/Include/Guid/ArmMpCoreInfo.h @@ -14,8 +14,7 @@ #define MPIDR_U_BIT_MASK 0x40000000
typedef struct {
- UINT32 ClusterId;
- UINT32 CoreId;
+ UINT64 Mpidr;
// MP Core Mailbox
EFI_PHYSICAL_ADDRESS MailboxSetAddress;
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index e4d0476090..6566deebdd 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -111,6 +111,10 @@ typedef enum { #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
+#define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)
+#define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)
+#define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)
+#define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
/** Reads the CCSIDR register for the specified cache.
|