ArmPkg: Added Aarch64 support

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14486 6f19259b-4bc3-4df7-8a09-765794883524

9 files changed, 652 insertions, 13 deletions

diff --git a/ArmPkg/Include/AsmMacroIoLibV8.h b/ArmPkg/Include/AsmMacroIoLibV8.h
new file mode 100644
index 0000000000..933ef7043b
--- /dev/null
+++ b/ArmPkg/Include/AsmMacroIoLibV8.h
@@ -0,0 +1,200 @@
+/** @file

+  Macros to work around lack of Apple support for LDR register, =expr

+

+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

+  Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+

+#ifndef __MACRO_IO_LIBV8_H__

+#define __MACRO_IO_LIBV8_H__

+

+#if defined (__GNUC__)

+

+#define MmioWrite32(Address, Data) \

+  ldr  x1, =Address ;              \

+  ldr  x0, =Data    ;              \

+  str  x0, [x1]

+

+#define MmioOr32(Address, OrData) \

+  ldr  x1, =Address ;             \

+  ldr  x2, =OrData  ;             \

+  ldr  x0, [x1]     ;             \

+  orr  x0, x0, x2   ;             \

+  str  x0, [x1]

+

+#define MmioAnd32(Address, AndData) \

+  ldr  x1, =Address ;               \

+  ldr  x2, =AndData ;               \

+  ldr  x0, [x1]     ;               \

+  and  x0, x0, x2   ;               \

+  str  x0, [x1]

+

+#define MmioAndThenOr32(Address, AndData, OrData) \

+  ldr  x1, =Address ;                             \

+  ldr  x0, [x1]     ;                             \

+  ldr  x2, =AndData ;                             \

+  and  x0, x0, x2   ;                             \

+  ldr  x2, =OrData  ;                             \

+  orr  x0, x0, x2   ;                             \

+  str  x0, [x1]

+

+#define MmioWriteFromReg32(Address, Reg) \

+  ldr  x1, =Address ;                    \

+  str  Reg, [x1]

+

+#define MmioRead32(Address) \

+  ldr  x1, =Address ;       \

+  ldr  x0, [x1]

+

+#define MmioReadToReg32(Address, Reg) \

+  ldr  x1, =Address ;                 \

+  ldr  Reg, [x1]

+

+#define LoadConstant(Data) \

+  ldr  x0, =Data

+

+#define LoadConstantToReg(Data, Reg) \

+  ldr  Reg, =Data

+

+#define SetPrimaryStack(StackTop, GlobalSize, Tmp, Tmp1)  \

+  ands    Tmp, GlobalSize, #15        ;                   \

+  mov     Tmp1, #16                   ;                   \

+  sub     Tmp1, Tmp1, Tmp             ;                   \

+  csel    Tmp, Tmp1, Tmp, ne          ;                   \

+  add     GlobalSize, GlobalSize, Tmp ;                   \

+  sub     sp, StackTop, GlobalSize    ;                   \

+                                      ;                   \

+  mov     Tmp, sp                     ;                   \

+  mov     GlobalSize, #0x0            ;                   \

+_SetPrimaryStackInitGlobals:          ;                   \

+  cmp     Tmp, StackTop               ;                   \

+  b.eq    _SetPrimaryStackEnd         ;                   \

+  str     GlobalSize, [Tmp], #8       ;                   \

+  b       _SetPrimaryStackInitGlobals ;                   \

+_SetPrimaryStackEnd:

+

+// Initialize the Global Variable with '0'

+#define InitializePrimaryStack(GlobalSize, Tmp1, Tmp2) \

+  and     Tmp1, GlobalSize, #15       ;             \

+  mov     Tmp2, #16                   ;             \

+  sub     Tmp2, Tmp2, Tmp1            ;             \

+  add     GlobalSize, GlobalSize, Tmp2 ;            \

+                                      ;             \

+  mov     Tmp1, sp                    ;             \

+  sub     sp, sp, GlobalSize          ;             \

+  mov     GlobalSize, #0x0            ;             \

+_InitializePrimaryStackLoop:          ;             \

+  mov     Tmp2, sp                    ;             \

+  cmp     Tmp1, Tmp2                  ;             \

+  bls     _InitializePrimaryStackEnd  ;             \

+  str     GlobalSize, [Tmp1, #-8]!    ;             \

+  b       _InitializePrimaryStackLoop ;             \

+_InitializePrimaryStackEnd:

+

+// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1

+// This only selects between EL1 and EL2, else we die.

+// Provide the Macro with a safe temp xreg to use.

+#define EL1_OR_EL2(SAFE_XREG)        \

+        mrs    SAFE_XREG, CurrentEL ;\

+        cmp    SAFE_XREG, #0x4	    ;\

+        b.eq   1f		    ;\

+        cmp    SAFE_XREG, #0x8	    ;\

+        b.eq   2f		    ;\

+        b      dead		    ;// We should never get here.

+

+// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1

+// This only selects between EL1 and EL2 and EL3, else we die.

+// Provide the Macro with a safe temp xreg to use.

+#define EL1_OR_EL2_OR_EL3(SAFE_XREG)        \

+        mrs    SAFE_XREG, CurrentEL ;\

+        cmp    SAFE_XREG, #0x4      ;\

+        b.eq   1f           ;\

+        cmp    SAFE_XREG, #0x8	    ;\

+        b.eq   2f		    ;\

+        cmp    SAFE_XREG, #0xC	    ;\

+        b.eq   3f		    ;\

+        b      dead		    ;// We should never get here.

+

+#else

+

+//

+// Use ARM assembly macros, form armasm

+//

+//  Less magic in the macros if ldr reg, =expr works

+//

+

+// returns _Data in X0 and _Address in X1

+

+

+

+#define MmioWrite32(Address, Data) MmioWrite32Macro Address, Data

+

+

+

+

+// returns Data in X0 and Address in X1, and OrData in X2

+#define MmioOr32(Address, OrData) MmioOr32Macro Address, OrData

+

+

+// returns _Data in X0 and _Address in X1, and _OrData in X2

+

+

+#define MmioAnd32(Address, AndData)  MmioAnd32Macro Address, AndData

+

+// returns result in X0, _Address in X1, and _OrData in X2

+

+

+#define MmioAndThenOr32(Address, AndData, OrData) MmioAndThenOr32Macro Address, AndData, OrData

+

+

+// returns _Data in _Reg and _Address in X1

+

+

+#define MmioWriteFromReg32(Address, Reg) MmioWriteFromReg32Macro Address, Reg

+

+// returns _Data in X0 and _Address in X1

+

+

+#define MmioRead32(Address)  MmioRead32Macro Address

+

+// returns _Data in Reg and _Address in X1

+

+

+#define MmioReadToReg32(Address, Reg) MmioReadToReg32Macro Address, Reg

+

+

+// load X0 with _Data

+

+

+#define LoadConstant(Data)  LoadConstantMacro Data

+

+// load _Reg with _Data

+

+

+#define LoadConstantToReg(Data, Reg)  LoadConstantToRegMacro Data, Reg

+

+// conditional load testing eq flag

+#define LoadConstantToRegIfEq(Data, Reg)  LoadConstantToRegIfEqMacro Data, Reg

+

+#define SetPrimaryStack(StackTop,GlobalSize,Tmp, Tmp1) SetPrimaryStack StackTop, GlobalSize, Tmp, Tmp1

+

+#define InitializePrimaryStack(GlobalSize, Tmp1, Tmp2) InitializePrimaryStack GlobalSize, Tmp1, Tmp2

+

+#define EL1_OR_EL2(SAFE_XREG)  EL1_OR_EL2 SAFE_XREG

+

+#define EL1_OR_EL2_OR_EL3(SAFE_XREG)  EL1_OR_EL2_OR_EL3 SAFE_XREG

+

+#endif

+

+#endif // __MACRO_IO_LIBV8_H__

+

diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h
new file mode 100644
index 0000000000..7f1f44ccc3
--- /dev/null
+++ b/ArmPkg/Include/Chipset/AArch64.h
@@ -0,0 +1,179 @@
+/** @file

+

+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

+  Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#ifndef __AARCH64_H__

+#define __AARCH64_H__

+

+#include <Chipset/AArch64Mmu.h>

+#include <Chipset/ArmArchTimer.h>

+

+// ARM Interrupt ID in Exception Table

+#define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_AARCH64_IRQ

+

+// CPACR - Coprocessor Access Control Register definitions

+#define CPACR_TTA_EN            (1UL << 28)

+#define CPACR_FPEN_EL1          (1UL << 20)

+#define CPACR_FPEN_FULL         (3UL << 20)

+#define CPACR_CP_FULL_ACCESS    0x300000

+

+// Coprocessor Trap Register (CPTR)

+#define AARCH64_CPTR_TFP        (1 << 10)

+

+// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions

+#define AARCH64_PFR0_FP         (0xF << 16)

+

+// NSACR - Non-Secure Access Control Register definitions

+#define NSACR_CP(cp)            ((1 << (cp)) & 0x3FFF)

+#define NSACR_NSD32DIS          (1 << 14)

+#define NSACR_NSASEDIS          (1 << 15)

+#define NSACR_PLE               (1 << 16)

+#define NSACR_TL                (1 << 17)

+#define NSACR_NS_SMP            (1 << 18)

+#define NSACR_RFR               (1 << 19)

+

+// SCR - Secure Configuration Register definitions

+#define SCR_NS                  (1 << 0)

+#define SCR_IRQ                 (1 << 1)

+#define SCR_FIQ                 (1 << 2)

+#define SCR_EA                  (1 << 3)

+#define SCR_FW                  (1 << 4)

+#define SCR_AW                  (1 << 5)

+

+// MIDR - Main ID Register definitions

+#define ARM_CPU_TYPE_MASK       0xFFF

+#define ARM_CPU_TYPE_AEMv8      0xD0F

+#define ARM_CPU_TYPE_A15        0xC0F

+#define ARM_CPU_TYPE_A9         0xC09

+#define ARM_CPU_TYPE_A5         0xC05

+

+// Hypervisor Configuration Register

+#define ARM_HCR_FMO				BIT3

+#define ARM_HCR_IMO				BIT4

+#define ARM_HCR_AMO				BIT5

+#define ARM_HCR_TGE				BIT27

+

+// AArch64 Exception Level

+#define AARCH64_EL3       0xC

+#define AARCH64_EL2       0x8

+#define AARCH64_EL1       0x4

+

+#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)

+

+VOID

+EFIAPI

+ArmEnableSWPInstruction (

+  VOID

+  );

+

+UINTN

+EFIAPI

+ArmReadCbar (

+  VOID

+  );

+

+UINTN

+EFIAPI

+ArmReadTpidrurw (

+  VOID

+  );

+

+VOID

+EFIAPI

+ArmWriteTpidrurw (

+  UINTN Value

+  );

+

+UINTN

+EFIAPI

+ArmIsArchTimerImplemented (

+  VOID

+  );

+

+UINTN

+EFIAPI

+ArmReadIdPfr0 (

+  VOID

+  );

+

+UINTN

+EFIAPI

+ArmReadIdPfr1 (

+  VOID

+  );

+

+UINTN

+EFIAPI

+ArmGetTCR (

+  VOID

+  );

+

+VOID

+EFIAPI

+ArmSetTCR (

+  UINTN Value

+  );

+

+UINTN

+EFIAPI

+ArmGetMAIR (

+  VOID

+  );

+

+VOID

+EFIAPI

+ArmSetMAIR (

+  UINTN Value

+  );

+

+VOID

+EFIAPI

+ArmDisableAlignmentCheck (

+  VOID

+  );

+

+

+VOID

+EFIAPI

+ArmEnableAlignmentCheck (

+  VOID

+  );

+

+VOID

+EFIAPI

+ArmDisableAllExceptions (

+  VOID

+  );

+

+VOID

+ArmWriteHcr (

+  IN UINTN Hcr

+  );

+

+UINTN

+ArmReadCurrentEL (

+  VOID

+  );

+

+UINT64

+PageAttributeToGcdAttribute (

+  IN UINT64 PageAttributes

+  );

+

+UINT64

+GcdAttributeToPageAttribute (

+  IN UINT64 GcdAttributes

+  );

+

+#endif // __AARCH64_H__

diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h
new file mode 100644
index 0000000000..0799734a19
--- /dev/null
+++ b/ArmPkg/Include/Chipset/AArch64Mmu.h
@@ -0,0 +1,208 @@
+/** @file

+*

+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.

+*

+*  This program and the accompanying materials

+*  are licensed and made available under the terms and conditions of the BSD License

+*  which accompanies this distribution.  The full text of the license may be found at

+*  http://opensource.org/licenses/bsd-license.php

+*

+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+*

+**/

+

+#ifndef __AARCH64_MMU_H_

+#define __AARCH64_MMU_H_

+

+//

+// Memory Attribute Indirection register Definitions

+//

+#define MAIR_ATTR_DEVICE_MEMORY                 0x0ULL

+#define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE   0x44ULL

+#define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH   0xBBULL

+#define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK      0xFFULL

+

+#define MAIR_ATTR(n,value)                      ((value) << (((n) >> 2)*8))

+

+//

+// Long-descriptor Translation Table format

+//

+

+// Return the smallest offset from the table level.

+// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0

+#define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel)  (12 + ((3 - (TableLevel)) * 9))

+

+#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level)     (1 << TT_ADDRESS_OFFSET_AT_LEVEL(Level))

+

+// Get the associated entry in the given Translation Table

+#define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address)  \

+    ((UINTN)(TranslationTable) + ((((Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64)))

+

+// Return the smallest address granularity from the table level.

+// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0

+#define TT_ADDRESS_AT_LEVEL(TableLevel)       (1 << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))

+

+// There are 512 entries per table when 4K Granularity

+#define TT_ENTRY_COUNT                          512

+#define TT_ALIGNMENT_BLOCK_ENTRY                BIT12

+#define TT_ALIGNMENT_DESCRIPTION_TABLE          BIT12

+

+#define TT_ADDRESS_MASK_BLOCK_ENTRY             (0xFFFFFFFULL << 12)

+#define TT_ADDRESS_MASK_DESCRIPTION_TABLE       (0xFFFFFFFULL << 12)

+

+#define TT_TYPE_MASK                            0x3

+#define TT_TYPE_TABLE_ENTRY                     0x3

+#define TT_TYPE_BLOCK_ENTRY                     0x1

+#define TT_TYPE_BLOCK_ENTRY_LEVEL3              0x3

+

+#define TT_ATTR_INDX_MASK                       (0x7 << 2)

+#define TT_ATTR_INDX_DEVICE_MEMORY              (0x0 << 2)

+#define TT_ATTR_INDX_MEMORY_NON_CACHEABLE       (0x1 << 2)

+#define TT_ATTR_INDX_MEMORY_WRITE_THROUGH       (0x2 << 2)

+#define TT_ATTR_INDX_MEMORY_WRITE_BACK          (0x3 << 2)

+

+#define TT_AP_MASK                              (0x3UL << 6)

+#define TT_AP_NO_RW                             (0x0UL << 6)

+#define TT_AP_RW_RW                             (0x1UL << 6)

+#define TT_AP_NO_RO                             (0x2UL << 6)

+#define TT_AP_RO_RO                             (0x3UL << 6)

+

+#define TT_NS                                   BIT5

+#define TT_AF                                   BIT10

+

+#define TT_PXN_MASK                             BIT53

+#define TT_UXN_MASK                             BIT54

+

+#define TT_ATTRIBUTES_MASK                      ((0xFFFULL << 52) | (0x3FFULL << 2))

+

+#define TT_TABLE_PXN                            BIT59

+#define TT_TABLE_XN                             BIT60

+#define TT_TABLE_NS                             BIT63

+

+#define TT_TABLE_AP_MASK                        (BIT62 | BIT61)

+#define TT_TABLE_AP_NO_PERMISSION               (0x0ULL << 61)

+#define TT_TABLE_AP_EL0_NO_ACCESS               (0x1ULL << 61)

+#define TT_TABLE_AP_NO_WRITE_ACCESS             (0x2ULL << 61)

+

+//

+// Translation Control Register

+//

+#define TCR_T0SZ_MASK                           0x3F

+

+#define TCR_PS_4GB                              (0 << 16)

+#define TCR_PS_64GB                             (1 << 16)

+#define TCR_PS_1TB                              (2 << 16)

+#define TCR_PS_4TB                              (3 << 16)

+#define TCR_PS_16TB                             (4 << 16)

+#define TCR_PS_256TB                            (5 << 16)

+

+#define TCR_TG0_4KB                             (0 << 14)

+

+#define TCR_IPS_4GB                             (0UL << 32)

+#define TCR_IPS_64GB                            (1UL << 32)

+#define TCR_IPS_1TB                             (2UL << 32)

+#define TCR_IPS_4TB                             (3UL << 32)

+#define TCR_IPS_16TB                            (4UL << 32)

+#define TCR_IPS_256TB                           (5UL << 32)

+

+

+#define TTBR_ASID_FIELD                      (48)

+#define TTBR_ASID_MASK                       (0xFF << TTBR_ASID_FIELD)

+#define TTBR_BADDR_MASK                      (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits

+

+#define TCR_EL1_T0SZ_FIELD                   (0)

+#define TCR_EL1_EPD0_FIELD                   (7)

+#define TCR_EL1_IRGN0_FIELD                  (8)

+#define TCR_EL1_ORGN0_FIELD                  (10)

+#define TCR_EL1_SH0_FIELD                    (12)

+#define TCR_EL1_TG0_FIELD                    (14)

+#define TCR_EL1_T1SZ_FIELD                   (16)

+#define TCR_EL1_A1_FIELD                     (22)

+#define TCR_EL1_EPD1_FIELD                   (23)

+#define TCR_EL1_IRGN1_FIELD                  (24)

+#define TCR_EL1_ORGN1_FIELD                  (26)

+#define TCR_EL1_SH1_FIELD                    (28)

+#define TCR_EL1_TG1_FIELD                    (30)

+#define TCR_EL1_IPS_FIELD                    (32)

+#define TCR_EL1_AS_FIELD                     (36)

+#define TCR_EL1_TBI0_FIELD                   (37)

+#define TCR_EL1_TBI1_FIELD                   (38)

+#define TCR_EL1_T0SZ_MASK                    (0x1F << TCR_EL1_T0SZ_FIELD)

+#define TCR_EL1_EPD0_MASK                    (0x1  << TCR_EL1_EPD0_FIELD)

+#define TCR_EL1_IRGN0_MASK                   (0x3  << TCR_EL1_IRGN0_FIELD)

+#define TCR_EL1_ORGN0_MASK                   (0x3  << TCR_EL1_ORGN0_FIELD)

+#define TCR_EL1_SH0_MASK                     (0x3  << TCR_EL1_SH0_FIELD)

+#define TCR_EL1_TG0_MASK                     (0x1  << TCR_EL1_TG0_FIELD)

+#define TCR_EL1_T1SZ_MASK                    (0x1F << TCR_EL1_T1SZ_FIELD)

+#define TCR_EL1_A1_MASK                      (0x1  << TCR_EL1_A1_FIELD)

+#define TCR_EL1_EPD1_MASK                    (0x1  << TCR_EL1_EPD1_FIELD)

+#define TCR_EL1_IRGN1_MASK                   (0x3  << TCR_EL1_IRGN1_FIELD)

+#define TCR_EL1_ORGN1_MASK                   (0x3  << TCR_EL1_ORGN1_FIELD)

+#define TCR_EL1_SH1_MASK                     (0x3  << TCR_EL1_SH1_FIELD)

+#define TCR_EL1_TG1_MASK                     (0x1  << TCR_EL1_TG1_FIELD)

+#define TCR_EL1_IPS_MASK                     (0x7  << TCR_EL1_IPS_FIELD)

+#define TCR_EL1_AS_MASK                      (0x1  << TCR_EL1_AS_FIELD)

+#define TCR_EL1_TBI0_MASK                    (0x1  << TCR_EL1_TBI0_FIELD)

+#define TCR_EL1_TBI1_MASK                    (0x1  << TCR_EL1_TBI1_FIELD)

+

+

+#define VTCR_EL23_T0SZ_FIELD                 (0)

+#define VTCR_EL23_IRGN0_FIELD                (8)

+#define VTCR_EL23_ORGN0_FIELD                (10)

+#define VTCR_EL23_SH0_FIELD                  (12)

+#define TCR_EL23_TG0_FIELD                   (14)

+#define VTCR_EL23_PS_FIELD                   (16)

+#define TCR_EL23_T0SZ_MASK                   (0x1F << VTCR_EL23_T0SZ_FIELD)

+#define TCR_EL23_IRGN0_MASK                  (0x3  << VTCR_EL23_IRGN0_FIELD)

+#define TCR_EL23_ORGN0_MASK                  (0x3  << VTCR_EL23_ORGN0_FIELD)

+#define TCR_EL23_SH0_MASK                    (0x3  << VTCR_EL23_SH0_FIELD)

+#define TCR_EL23_TG0_MASK                    (0x1  << TCR_EL23_TG0_FIELD)

+#define TCR_EL23_PS_MASK                     (0x7  << VTCR_EL23_PS_FIELD)

+

+

+#define VTCR_EL2_T0SZ_FIELD                  (0)

+#define VTCR_EL2_SL0_FIELD                   (6)

+#define VTCR_EL2_IRGN0_FIELD                 (8)

+#define VTCR_EL2_ORGN0_FIELD                 (10)

+#define VTCR_EL2_SH0_FIELD                   (12)

+#define VTCR_EL2_TG0_FIELD                   (14)

+#define VTCR_EL2_PS_FIELD                    (16)

+#define VTCR_EL2_T0SZ_MASK                   (0x1F << VTCR_EL2_T0SZ_FIELD)

+#define VTCR_EL2_SL0_MASK                    (0x1F << VTCR_EL2_SL0_FIELD)

+#define VTCR_EL2_IRGN0_MASK                  (0x3  << VTCR_EL2_IRGN0_FIELD)

+#define VTCR_EL2_ORGN0_MASK                  (0x3  << VTCR_EL2_ORGN0_FIELD)

+#define VTCR_EL2_SH0_MASK                    (0x3  << VTCR_EL2_SH0_FIELD)

+#define VTCR_EL2_TG0_MASK                    (0x1  << VTCR_EL2_TG0_FIELD)

+#define VTCR_EL2_PS_MASK                     (0x7  << VTCR_EL2_PS_FIELD)

+

+

+#define TCR_RGN_OUTER_NON_CACHEABLE          (0x0 << 10)

+#define TCR_RGN_OUTER_WRITE_BACK_ALLOC       (0x1 << 10)

+#define TCR_RGN_OUTER_WRITE_THROUGH          (0x2 << 10)

+#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC    (0x3 << 10)

+

+#define TCR_RGN_INNER_NON_CACHEABLE          (0x0 << 8)

+#define TCR_RGN_INNER_WRITE_BACK_ALLOC       (0x1 << 8)

+#define TCR_RGN_INNER_WRITE_THROUGH          (0x2 << 8)

+#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC    (0x3 << 8)

+

+#define TCR_SH_NON_SHAREABLE                 (0x0 << 12)

+#define TCR_SH_OUTER_SHAREABLE               (0x2 << 12)

+#define TCR_SH_INNER_SHAREABLE               (0x3 << 12)

+

+#define TCR_PASZ_32BITS_4GB                  (0x0)

+#define TCR_PASZ_36BITS_64GB                 (0x1)

+#define TCR_PASZ_40BITS_1TB                  (0x2)

+#define TCR_PASZ_42BITS_4TB                  (0x3)

+#define TCR_PASZ_44BITS_16TB                 (0x4)

+#define TCR_PASZ_48BITS_256TB                (0x5)

+

+// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit

+// Virtual address range for 512GB of virtual space sets T*SZ to 25

+#define INPUT_ADDRESS_SIZE_TO_TxSZ(a)        (64 - a)

+

+// Uses LPAE Page Table format

+

+#endif // __AARCH64_MMU_H_

+

diff --git a/ArmPkg/Include/Chipset/ArmAemV8.h b/ArmPkg/Include/Chipset/ArmAemV8.h
new file mode 100644
index 0000000000..a64a92124e
--- /dev/null
+++ b/ArmPkg/Include/Chipset/ArmAemV8.h
@@ -0,0 +1,21 @@
+/** @file

+

+  Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#ifndef __ARM_AEM_V8_H__

+#define __ARM_AEM_V8_H__

+

+#include <Chipset/AArch64.h>

+

+#endif //__ARM_AEM_V8_H__

+

diff --git a/ArmPkg/Include/Chipset/ArmV7ArchTimer.h b/ArmPkg/Include/Chipset/ArmArchTimer.h
index 734c8855ee..fcc03ca921 100644
--- a/ArmPkg/Include/Chipset/ArmV7ArchTimer.h
+++ b/ArmPkg/Include/Chipset/ArmArchTimer.h
@@ -1,6 +1,6 @@
 /** @file

 *

-*  Copyright (c) 2011, ARM Limited. All rights reserved.

+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.

 *  

 *  This program and the accompanying materials                          

 *  are licensed and made available under the terms and conditions of the BSD License         

@@ -12,8 +12,8 @@
 *

 **/

 

-#ifndef __ARMV7_ARCH_TIMER_H_

-#define __ARMV7_ARCH_TIMER_H_

+#ifndef __ARM_ARCH_TIMER_H_

+#define __ARM_ARCH_TIMER_H_

 

 UINTN

 EFIAPI

@@ -135,4 +135,5 @@ ArmWriteCntvOff (
   UINT64   Val

   );

 

-#endif

+#endif // __ARM_ARCH_TIMER_H_

+

diff --git a/ArmPkg/Include/Chipset/ArmCortexA5x.h b/ArmPkg/Include/Chipset/ArmCortexA5x.h
new file mode 100644
index 0000000000..e2217e3f3a
--- /dev/null
+++ b/ArmPkg/Include/Chipset/ArmCortexA5x.h
@@ -0,0 +1,23 @@
+/** @file

+

+  Copyright (c) 2012-2013, ARM Limited. All rights reserved.

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#ifndef __ARM_CORTEX_A5x_H__

+#define __ARM_CORTEX_A5x_H__

+

+//

+// Cortex A5x feature bit definitions

+//

+#define A5X_FEATURE_SMP     (1 << 6)

+

+#endif

diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h
index e64deb141b..479e8d05e1 100644
--- a/ArmPkg/Include/Chipset/ArmV7.h
+++ b/ArmPkg/Include/Chipset/ArmV7.h
@@ -17,7 +17,7 @@
 #define __ARM_V7_H__

 

 #include <Chipset/ArmV7Mmu.h>

-#include <Chipset/ArmV7ArchTimer.h>

+#include <Chipset/ArmArchTimer.h>

 

 // ARM Interrupt ID in Exception Table

 #define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_ARM_IRQ

diff --git a/ArmPkg/Include/Library/ArmV7ArchTimerLib.h b/ArmPkg/Include/Library/ArmArchTimerLib.h
index 983184810f..1ecada383b 100644
--- a/ArmPkg/Include/Library/ArmV7ArchTimerLib.h
+++ b/ArmPkg/Include/Library/ArmArchTimerLib.h
@@ -1,6 +1,6 @@
 /** @file

 

-  Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>

+  Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -12,8 +12,8 @@
 

 **/

 

-#ifndef __ARM_V7_ARCH_TIMER_LIB_H__

-#define __ARM_V7_ARCH_TIMER_LIB_H__

+#ifndef __ARM_ARCH_TIMER_LIB_H__

+#define __ARM_ARCH_TIMER_LIB_H__

 

 #define ARM_ARCH_TIMER_ENABLE           (1 << 0)

 #define ARM_ARCH_TIMER_IMASK            (1 << 1)

@@ -36,7 +36,7 @@ typedef enum {
   CnthpCtl,

   CnthpCval,

   RegMaximum

-}ARM_ARCH_TIMER_REGS;

+} ARM_ARCH_TIMER_REGS;

 

 VOID

 EFIAPI

@@ -112,4 +112,4 @@ ArmArchTimerSetCompareVal (
   IN   UINT64   Val

   );

 

-#endif // __ARM_V7_ARCH_TIMER_LIB_H__

+#endif // __ARM_ARCH_TIMER_LIB_H__

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 8174845c6f..1f1fd9e515 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -18,10 +18,16 @@
 

 #include <Uefi/UefiBaseType.h>

 

-#ifdef ARM_CPU_ARMv6

-#include <Chipset/ARM1176JZ-S.h>

+#ifdef MDE_CPU_ARM

+  #ifdef ARM_CPU_ARMv6

+    #include <Chipset/ARM1176JZ-S.h>

+  #else

+    #include <Chipset/ArmV7.h>

+  #endif

+#elif defined(MDE_CPU_AARCH64)

+  #include <Chipset/AArch64.h>

 #else

-#include <Chipset/ArmV7.h>

+ #error "Unknown chipset."

 #endif

 

 typedef enum {

@@ -501,6 +507,7 @@ ArmCallWFE (
 VOID

 EFIAPI

 ArmCallWFI (

+

   VOID

   );