Added support for L2 (4K) page tables and made the CPU driver change cachability attributes on request. Also got the DebugUncache infrastructure working for the first time. Looks like it works for the simple case. Checking in so we can get more eyes looking at the code.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9734 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 4 insertions, 8 deletions

diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
index 7da6b42a92..b5754e6dca 100644
--- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
@@ -27,19 +27,15 @@ CacheRangeOperation (
   UINTN ArmCacheLineAlignmentMask  = ArmCacheLineLength - 1;
   UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
   
-  if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold))
-  {
-    CacheOperation();
-  }
-  else
-  {
+  if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {
+    CacheOperation ();
+  } else {
     // Align address (rounding down)
     UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
     UINTN EndAddress     = (UINTN)Start + Length;
 
     // Perform the line operation on an address in each cache line
-    while (AlignedAddress < EndAddress)
-    {
+    while (AlignedAddress < EndAddress) {
       LineOperation(AlignedAddress);
       AlignedAddress += ArmCacheLineLength;
     }