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authorAntoine Cœur <coeur@gmx.fr>2019-02-06 23:39:35 +0800
committerLeif Lindholm <leif.lindholm@linaro.org>2019-07-04 12:20:28 +0100
commitff5fef1428dafc8f73e1f5d63966ef5c9bd8c420 (patch)
treee101e619122fa00859d5d776a026556ef7401e76 /ArmPkg/Library/ArmExceptionLib
parent080981d72dcbb782ad73716c439639324b0aa4dd (diff)
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ArmPkg: Fix various typos
Fix various typos in ArmPkg. Signed-off-by: Coeur <coeur@gmx.fr> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'ArmPkg/Library/ArmExceptionLib')
-rw-r--r--ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.S2
-rw-r--r--ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm2
-rw-r--r--ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c4
3 files changed, 4 insertions, 4 deletions
diff --git a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.S b/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.S
index 481dee9b80..d9ad775934 100644
--- a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.S
+++ b/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.S
@@ -227,7 +227,7 @@ ASM_PFX(AsmCommonExceptionEntry):
ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
@ Check to see if we have to adjust for Thumb entry
sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType == 2)) {
- cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb
+ cmp r4, #1 @ // UND & SVC have different LR adjust for Thumb
bhi NoAdjustNeeded
tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry
diff --git a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm b/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
index 06507c6404..aa0229d2e8 100644
--- a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
+++ b/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
@@ -221,7 +221,7 @@ AsmCommonExceptionEntry
ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd
; Check to see if we have to adjust for Thumb entry
sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType == 2)) {
- cmp r4, #1 ; // UND & SVC have differnt LR adjust for Thumb
+ cmp r4, #1 ; // UND & SVC have different LR adjust for Thumb
bhi NoAdjustNeeded
tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry
diff --git a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c
index bd1895ef1d..1ff90dede5 100644
--- a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c
+++ b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c
@@ -94,7 +94,7 @@ InitializeCpuExceptionHandlers(
Status = EFI_SUCCESS;
- // if we are requested to copy exceptin handlers to another location
+ // if we are requested to copy exception handlers to another location
if (gArmRelocateVectorTable) {
VectorBase = PcdGet64(PcdCpuVectorBaseAddress);
@@ -131,7 +131,7 @@ InitializeCpuExceptionHandlers(
}
/**
-Copies exception handlers to the speciifed address.
+Copies exception handlers to the specified address.
Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.