ArmPkg/ArmLib: ASSERT on set/way cache ops being used with MMU on

On ARMv7 and up, doing cache maintenance by set/way is only
permitted in the context of on/offlining a core, and any other
uses should be avoided. Add ASSERT()s in the right place to
ensure that any uses with the MMU enabled are caught in DEBUG
builds.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
index 924bf48020..3fbd591192 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
@@ -10,6 +10,7 @@
 #include <Base.h>

 

 #include <Library/ArmLib.h>

+#include <Library/DebugLib.h>

 

 #include <Chipset/AArch64.h>

 

@@ -41,6 +42,8 @@ ArmInvalidateDataCache (
   VOID

   )

 {

+  ASSERT (!ArmMmuEnabled ());

+

   ArmDataSynchronizationBarrier ();

   AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);

 }

@@ -51,6 +54,8 @@ ArmCleanInvalidateDataCache (
   VOID

   )

 {

+  ASSERT (!ArmMmuEnabled ());

+

   ArmDataSynchronizationBarrier ();

   AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);

 }

@@ -61,6 +66,8 @@ ArmCleanDataCache (
   VOID

   )

 {

+  ASSERT (!ArmMmuEnabled ());

+

   ArmDataSynchronizationBarrier ();

   AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);

 }