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| author | Olivier Martin <olivier.martin@arm.com> | 2013-07-26 17:14:07 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-07-26 17:14:07 +0000 |
| commit | 70f89c0b5fa54dc8879e2ece3be2d2596b0b37cc (patch) | |
| tree | f4d295f1be8fa480dd46bcf1406d8696bc96ec41 /ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | |
| parent | e21227c62730aa438b8f6e48f81c58a2ddfd6656 (diff) | |
| download | edk2-70f89c0b5fa54dc8879e2ece3be2d2596b0b37cc.tar.gz edk2-70f89c0b5fa54dc8879e2ece3be2d2596b0b37cc.tar.bz2 edk2-70f89c0b5fa54dc8879e2ece3be2d2596b0b37cc.zip | |
ArmPkg/ArmLib: Fixed TBLs invalidation in EL1
'tlb alle1' was used to invalidate the TLBs in EL1. Expect this instruction can only
be invoked from EL2.
The correct instruction to invalidate TLBs in EL1 is 'tlbi vmalle1' - it invalidates
the TLBs of the current VMID.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14509 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/AArch64/AArch64Support.S')
| -rw-r--r-- | ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S index c45e33d6b9..ad9fdda525 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -123,7 +123,7 @@ ASM_PFX(ArmEnableMmu): 3: mrs x0, sctlr_el3 // Read System control register EL3
4: orr x0, x0, #CTRL_M_BIT // Set MMU enable bit
EL1_OR_EL2_OR_EL3(x1)
-1: tlbi alle1
+1: tlbi vmalle1
isb
msr sctlr_el1, x0 // Write back
b 4f
@@ -149,7 +149,7 @@ ASM_PFX(ArmDisableMmu): 4: bic x0, x0, #CTRL_M_BIT // Clear MMU enable bit
EL1_OR_EL2_OR_EL3(x1)
1: msr sctlr_el1, x0 // Write back
- tlbi alle1
+ tlbi vmalle1
b 4f
2: msr sctlr_el2, x0 // Write back
tlbi alle2
@@ -441,7 +441,7 @@ ASM_PFX(ArmCallWFI): ASM_PFX(ArmInvalidateInstructionAndDataTlb):
EL1_OR_EL2_OR_EL3(x0)
-1: tlbi alle1
+1: tlbi vmalle1
b 4f
2: tlbi alle2
b 4f
|