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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2015-11-09 13:26:11 +0000 |
|---|---|---|
| committer | abiesheuvel <abiesheuvel@Edk2> | 2015-11-09 13:26:11 +0000 |
| commit | acdb6dc8b739ccddd8425e609b68871151c5b94e (patch) | |
| tree | b68d79f88282be3aa239f2b987b2fa33cc630df4 /ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | |
| parent | cf93a37859e6d06efdbc5b1a91a6bf66f06b578b (diff) | |
| download | edk2-acdb6dc8b739ccddd8425e609b68871151c5b94e.tar.gz edk2-acdb6dc8b739ccddd8425e609b68871151c5b94e.tar.bz2 edk2-acdb6dc8b739ccddd8425e609b68871151c5b94e.zip | |
ArmPkg/ArmLib: remove unused ArmCleanDataCacheToPoU()
The function ArmCleanDataCacheToPoU() has no users, and its purpose
is unclear, since it uses cache maintenance by set/way to perform
the clean to PoU, which is a dubious practice to begin with. So
remove the declaration and all definitions.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18752 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/AArch64/AArch64Support.S')
| -rw-r--r-- | ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S index 8b5e0fb6e7..f973a35c21 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -40,7 +40,6 @@ GCC_ASM_EXPORT (ArmEnableAlignmentCheck) GCC_ASM_EXPORT (ArmEnableBranchPrediction)
GCC_ASM_EXPORT (ArmDisableBranchPrediction)
GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
-GCC_ASM_EXPORT (AArch64PerformPoUDataCacheOperation)
GCC_ASM_EXPORT (ArmDataMemoryBarrier)
GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
@@ -324,19 +323,6 @@ ASM_PFX(AArch64AllDataCachesOperation): // right to ease the access to CSSELR and the Set/Way operation.
cbz x3, L_Finished // No need to clean if LoC is 0
mov x10, #0 // Start clean at cache level 0
- b Loop1
-
-ASM_PFX(AArch64PerformPoUDataCacheOperation):
-// We can use regs 0-7 and 9-15 without having to save/restore.
-// Save our link register on the stack. - The stack must always be quad-word aligned
- str x30, [sp, #-16]!
- mov x1, x0 // Save Function call in x1
- mrs x6, clidr_el1 // Read EL1 CLIDR
- and x3, x6, #0x38000000 // Mask out all but Point of Unification (PoU)
- lsr x3, x3, #26 // Left align cache level value - the level is shifted by 1 to the
- // right to ease the access to CSSELR and the Set/Way operation.
- cbz x3, L_Finished // No need to clean if LoC is 0
- mov x10, #0 // Start clean at cache level 0
Loop1:
add x2, x10, x10, lsr #1 // Work out 3x cachelevel for cache info
|