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| author | Cohen, Eugene <eugene@hp.com> | 2016-02-22 23:08:27 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-02-23 12:07:11 +0100 |
| commit | 4af3dd80abb759f3c439f8d1369a57745db08d30 (patch) | |
| tree | 60c26300065cf79a8fbd29330a21af224d2bad97 /ArmPkg/Library/ArmLib/AArch64 | |
| parent | 2ba36b2f0ea77661a4a3dcce6785df49be20698d (diff) | |
| download | edk2-4af3dd80abb759f3c439f8d1369a57745db08d30.tar.gz edk2-4af3dd80abb759f3c439f8d1369a57745db08d30.tar.bz2 edk2-4af3dd80abb759f3c439f8d1369a57745db08d30.zip | |
ArmPkg: CpuDxe: fix AArch64 interrupt read masks
The AArch64 DAIF bits are different for reading (mrs) versus writing
(msr). The bitmask definitions assumed they were the same causing
incorrect results when trying to determine the current interrupt
state through ArmGetInterruptState.
The logic for interpreting the DAIF read data using the csel instruction
was also incorrect and is fixed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'ArmPkg/Library/ArmLib/AArch64')
| -rw-r--r-- | ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S | 32 |
1 files changed, 17 insertions, 15 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S index 8fd4194ab2..341bbce76c 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S @@ -35,12 +35,14 @@ GCC_ASM_EXPORT (ReadCLIDR) .set MPIDR_U_BIT, (30)
.set MPIDR_U_MASK, (1 << MPIDR_U_BIT)
-.set DAIF_FIQ_BIT, (1 << 0)
-.set DAIF_IRQ_BIT, (1 << 1)
-.set DAIF_ABORT_BIT, (1 << 2)
-.set DAIF_DEBUG_BIT, (1 << 3)
-.set DAIF_INT_BITS, (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
-.set DAIF_ALL, (DAIF_DEBUG_BIT | DAIF_ABORT_BIT | DAIF_INT_BITS)
+
+// DAIF bit definitions for writing through msr daifclr/sr daifset
+.set DAIF_WR_FIQ_BIT, (1 << 0)
+.set DAIF_WR_IRQ_BIT, (1 << 1)
+.set DAIF_WR_ABORT_BIT, (1 << 2)
+.set DAIF_WR_DEBUG_BIT, (1 << 3)
+.set DAIF_WR_INT_BITS, (DAIF_WR_FIQ_BIT | DAIF_WR_IRQ_BIT)
+.set DAIF_WR_ALL, (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS)
ASM_PFX(ArmIsMpCore):
@@ -52,55 +54,55 @@ ASM_PFX(ArmIsMpCore): ASM_PFX(ArmEnableAsynchronousAbort):
- msr daifclr, #DAIF_ABORT_BIT
+ msr daifclr, #DAIF_WR_ABORT_BIT
isb
ret
ASM_PFX(ArmDisableAsynchronousAbort):
- msr daifset, #DAIF_ABORT_BIT
+ msr daifset, #DAIF_WR_ABORT_BIT
isb
ret
ASM_PFX(ArmEnableIrq):
- msr daifclr, #DAIF_IRQ_BIT
+ msr daifclr, #DAIF_WR_IRQ_BIT
isb
ret
ASM_PFX(ArmDisableIrq):
- msr daifset, #DAIF_IRQ_BIT
+ msr daifset, #DAIF_WR_IRQ_BIT
isb
ret
ASM_PFX(ArmEnableFiq):
- msr daifclr, #DAIF_FIQ_BIT
+ msr daifclr, #DAIF_WR_FIQ_BIT
isb
ret
ASM_PFX(ArmDisableFiq):
- msr daifset, #DAIF_FIQ_BIT
+ msr daifset, #DAIF_WR_FIQ_BIT
isb
ret
ASM_PFX(ArmEnableInterrupts):
- msr daifclr, #DAIF_INT_BITS
+ msr daifclr, #DAIF_WR_INT_BITS
isb
ret
ASM_PFX(ArmDisableInterrupts):
- msr daifset, #DAIF_INT_BITS
+ msr daifset, #DAIF_WR_INT_BITS
isb
ret
ASM_PFX(ArmDisableAllExceptions):
- msr daifset, #DAIF_ALL
+ msr daifset, #DAIF_WR_ALL
isb
ret
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