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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2018-11-23 13:14:27 +0100
committerArd Biesheuvel <ard.biesheuvel@linaro.org>2018-11-29 18:54:09 +0100
commit95d04ebca8be8f71a23e85a2f4822ba90a2e32cc (patch)
tree6813d0031bcb4a3462b0db112f99475160fbd312 /ArmPkg/Library/ArmLib/AArch64
parent82379bf6603274e81604d5a6f6bb14bdde616286 (diff)
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ArmPkg/ArmLib: add support for reading the max physical address space size
Add a helper function that returns the maximum physical address space size as supported by the current CPU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'ArmPkg/Library/ArmLib/AArch64')
-rw-r--r--ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S17
1 files changed, 17 insertions, 0 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
index 1ef2f61f59..b7173e00b0 100644
--- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
@@ -196,4 +196,21 @@ ASM_FUNC(ArmWriteSctlr)
3:msr sctlr_el3, x0
4:ret
+ASM_FUNC(ArmGetPhysicalAddressBits)
+ mrs x0, id_aa64mmfr0_el1
+ adr x1, .LPARanges
+ and x0, x0, #0xf
+ ldrb w0, [x1, x0]
+ ret
+
+//
+// Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the
+// physical address space support on this CPU:
+// 0 == 32 bits, 1 == 36 bits, etc etc
+// 7 and up are reserved
+//
+.LPARanges:
+ .byte 32, 36, 40, 42, 44, 48, 52, 0
+ .byte 0, 0, 0, 0, 0, 0, 0, 0
+
ASM_FUNCTION_REMOVE_IF_UNREFERENCED