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| author | Eugene Cohen <eugene@hp.com> | 2015-12-08 15:58:53 +0000 |
|---|---|---|
| committer | abiesheuvel <abiesheuvel@Edk2> | 2015-12-08 15:58:53 +0000 |
| commit | b7de7e3cab3f172bb8ef3e2638f90889981d791a (patch) | |
| tree | 72f1cff046f798823c956cde71870b60b900a78b /ArmPkg/Library/ArmLib/AArch64 | |
| parent | 62c12ff8c7e7c34af2724758e49b35c26897f2d8 (diff) | |
| download | edk2-b7de7e3cab3f172bb8ef3e2638f90889981d791a.tar.gz edk2-b7de7e3cab3f172bb8ef3e2638f90889981d791a.tar.bz2 edk2-b7de7e3cab3f172bb8ef3e2638f90889981d791a.zip | |
ArmPkg: update InvalidateInstructionCacheRange to flush only to PoU
This patch updates the ArmPkg variant of InvalidateInstructionCacheRange to
flush the data cache only to the point of unification (PoU). This improves
performance and also allows invalidation in scenarios where it would be
inappropriate to flush to the point of coherency (like when executing code
from L2 configured as cache-as-ram).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Added AARCH64 and ARM/GCC implementations of the above.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19174 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/AArch64')
| -rw-r--r-- | ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S index c530d19e89..db21f73f0e 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -22,6 +22,7 @@ GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
+GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
@@ -72,6 +73,11 @@ ASM_PFX(ArmCleanDataCacheEntryByMVA): ret
+ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):
+ dc cvau, x0 // Clean single data cache line to PoU
+ ret
+
+
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
dc civac, x0 // Clean and invalidate single data cache line
ret
|