diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-05-11 10:38:47 +0200 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-05-12 13:53:08 +0200 |
| commit | cf580da1bc4c16026cb1732f741a892b2d3d3d67 (patch) | |
| tree | d4b3b771dbfb0914e8af897c27b3c8668084e185 /ArmPkg/Library/ArmLib/AArch64 | |
| parent | 14b2ebc30c8bc98f668fa78171b659e2cdc33aa5 (diff) | |
| download | edk2-cf580da1bc4c16026cb1732f741a892b2d3d3d67.tar.gz edk2-cf580da1bc4c16026cb1732f741a892b2d3d3d67.tar.bz2 edk2-cf580da1bc4c16026cb1732f741a892b2d3d3d67.zip | |
ArmPkg/ArmLib: don't invalidate entire I-cache on range operation
Instead of cleaning the data cache to the PoU by virtual address and
subsequently invalidating the entire I-cache, invalidate only the
range that we just cleaned. This way, we don't invalidate other
cachelines unnecessarily.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'ArmPkg/Library/ArmLib/AArch64')
| -rw-r--r-- | ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S index 43f7a795ac..9441f47e30 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -23,6 +23,7 @@ GCC_ASM_EXPORT (ArmInvalidateInstructionCache) GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)
+GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA)
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
@@ -80,6 +81,10 @@ ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA): dc cvau, x0 // Clean single data cache line to PoU
ret
+ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA):
+ ic ivau, x0 // Invalidate single instruction cache line to PoU
+ ret
+
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
dc civac, x0 // Clean and invalidate single data cache line
|