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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-06-21 09:17:52 +0200 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-06-21 16:09:22 +0200 |
| commit | 6e275c613e15ffc6dc79901fb244e8cb20af9948 (patch) | |
| tree | 01251e8680082fa82c83e3453146a21fb947d5b7 /ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | |
| parent | 713aea34864ce5fc0a248b85bf3caa64fcf22467 (diff) | |
| download | edk2-6e275c613e15ffc6dc79901fb244e8cb20af9948.tar.gz edk2-6e275c613e15ffc6dc79901fb244e8cb20af9948.tar.bz2 edk2-6e275c613e15ffc6dc79901fb244e8cb20af9948.zip | |
ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memory
Given that these days, our ARM port only supports ARMv7 and later, we
can assume that the page table walker's memory accesses are cache
coherent, and so there is no need to perform cache maintenance. It
does require the page tables themselves to reside in memory mapped as
writeback cacheable so ASSERT() that this is the case.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S')
| -rw-r--r-- | ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S index 149b57e059..f2a517671f 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S @@ -100,8 +100,6 @@ ASM_FUNC(ArmGetTTBR0BaseAddress) // IN VOID *MVA // R1
// );
ASM_FUNC(ArmUpdateTranslationTableEntry)
- mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
- dsb
mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
|