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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-11-23 13:14:27 +0100 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-11-29 18:54:09 +0100 |
| commit | 95d04ebca8be8f71a23e85a2f4822ba90a2e32cc (patch) | |
| tree | 6813d0031bcb4a3462b0db112f99475160fbd312 /ArmPkg/Library/ArmLib/Arm | |
| parent | 82379bf6603274e81604d5a6f6bb14bdde616286 (diff) | |
| download | edk2-95d04ebca8be8f71a23e85a2f4822ba90a2e32cc.tar.gz edk2-95d04ebca8be8f71a23e85a2f4822ba90a2e32cc.tar.bz2 edk2-95d04ebca8be8f71a23e85a2f4822ba90a2e32cc.zip | |
ArmPkg/ArmLib: add support for reading the max physical address space size
Add a helper function that returns the maximum physical address space
size as supported by the current CPU.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'ArmPkg/Library/ArmLib/Arm')
| -rw-r--r-- | ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 8 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm | 8 |
2 files changed, 16 insertions, 0 deletions
diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S index f2a517671f..0e9f9d0453 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr) isb
bx lr
+ASM_FUNC (ArmGetPhysicalAddressBits)
+ mrc p15, 0, r0, c0, c1, 4 // MMFR0
+ and r0, r0, #0xf // VMSA [3:0]
+ cmp r0, #5 // >= 5 implies LPAE support
+ movlt r0, #32 // 32 bits if no LPAE
+ movge r0, #40 // 40 bits if LPAE
+ bx lr
+
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm index 219140c22b..3eb5287597 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm @@ -169,4 +169,12 @@ isb
bx lr
+ RVCT_ASM_EXPORT ArmGetPhysicalAddressBits
+ mrc p15, 0, r0, c0, c1, 4 ; MMFR0
+ and r0, r0, #0xf ; VMSA [3:0]
+ cmp r0, #5 ; >= 5 implies LPAE support
+ movlt r0, #32 ; 32 bits if no LPAE
+ movge r0, #40 ; 40 bits if LPAE
+ bx lr
+
END
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