diff options
| author | Pierre Gondois <Pierre.Gondois@arm.com> | 2021-04-20 15:25:17 +0100 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-04-28 12:03:51 +0000 |
| commit | b8de64bedecf01b5df760d9f81bdd9c0d733399e (patch) | |
| tree | 277129b6ab154d20f455bcdb722294e44d6f0ba5 /ArmPkg/Library/ArmMmuLib | |
| parent | c2bd8a1a823f184e54f45e1eb7d8a14be77e502b (diff) | |
| download | edk2-b8de64bedecf01b5df760d9f81bdd9c0d733399e.tar.gz edk2-b8de64bedecf01b5df760d9f81bdd9c0d733399e.tar.bz2 edk2-b8de64bedecf01b5df760d9f81bdd9c0d733399e.zip | |
ArmPkg: Correct small typos
The 'cspell' CI test detected some small typos in ArmPkg.
Correct them.
Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Diffstat (limited to 'ArmPkg/Library/ArmMmuLib')
| -rw-r--r-- | ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c index 940e4bc797..6b9d7eba90 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c @@ -124,7 +124,7 @@ UpdatePageEntries ( } else if ((Attributes & EFI_MEMORY_WC) != 0) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
- // map to normal non-cachable
+ // map to normal non-cacheable
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
} else if ((Attributes & EFI_MEMORY_WT) != 0) {
// modify cacheability attributes
@@ -254,7 +254,7 @@ UpdateSectionEntries ( } else if ((Attributes & EFI_MEMORY_WC) != 0) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
- // map to normal non-cachable
+ // map to normal non-cacheable
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
} else if ((Attributes & EFI_MEMORY_WT) != 0) {
// modify cacheability attributes
|