diff options
| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2021-12-05 14:53:50 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-07 17:24:28 +0000 |
| commit | 429309e0c6b74792d679681a8edd0d5ae0ff850c (patch) | |
| tree | 9d26d88024790b459c60a44e14500b7c7076f0d1 /ArmPkg/Library | |
| parent | 7c2a6033c149625482a18cd51b65513c8fb8fe15 (diff) | |
| download | edk2-429309e0c6b74792d679681a8edd0d5ae0ff850c.tar.gz edk2-429309e0c6b74792d679681a8edd0d5ae0ff850c.tar.bz2 edk2-429309e0c6b74792d679681a8edd0d5ae0ff850c.zip | |
ArmPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the ArmPkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>
Diffstat (limited to 'ArmPkg/Library')
51 files changed, 3110 insertions, 2550 deletions
diff --git a/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c b/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c index 4b1c9ac49e..d663a76a9b 100644 --- a/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c +++ b/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c @@ -7,7 +7,6 @@ **/
-
#include <Base.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
@@ -16,16 +15,15 @@ #include <Library/PcdLib.h>
#include <Library/ArmGenericTimerCounterLib.h>
-#define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U)
+#define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U)
// Select appropriate multiply function for platform architecture.
#ifdef MDE_CPU_ARM
-#define MULT_U64_X_N MultU64x32
+#define MULT_U64_X_N MultU64x32
#else
-#define MULT_U64_X_N MultU64x64
+#define MULT_U64_X_N MultU64x64
#endif
-
RETURN_STATUS
EFIAPI
TimerConstructor (
@@ -36,7 +34,6 @@ TimerConstructor ( // Check if the ARM Generic Timer Extension is implemented.
//
if (ArmIsArchTimerImplemented ()) {
-
//
// Check if Architectural Timer frequency is pre-determined by the platform
// (ie. nonzero).
@@ -49,7 +46,7 @@ TimerConstructor ( //
ASSERT (TICKS_PER_MICRO_SEC);
-#ifdef MDE_CPU_ARM
+ #ifdef MDE_CPU_ARM
//
// Only set the frequency for ARMv7. We expect the secure firmware to
// have already done it.
@@ -59,7 +56,8 @@ TimerConstructor ( if (ArmHasSecurityExtensions ()) {
ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
}
-#endif
+
+ #endif
}
//
@@ -68,7 +66,6 @@ TimerConstructor ( // If the reset value (0) is returned, just ASSERT.
//
ASSERT (ArmGenericTimerGetTimerFreq () != 0);
-
} else {
DEBUG ((DEBUG_ERROR, "ARM Architectural Timer is not available in the CPU, hence this library cannot be used.\n"));
ASSERT (0);
@@ -90,16 +87,16 @@ EFIAPI GetPlatformTimerFreq (
)
{
- UINTN TimerFreq;
+ UINTN TimerFreq;
TimerFreq = PcdGet32 (PcdArmArchTimerFreqInHz);
if (TimerFreq == 0) {
TimerFreq = ArmGenericTimerGetTimerFreq ();
}
+
return TimerFreq;
}
-
/**
Stalls the CPU for the number of microseconds specified by MicroSeconds.
@@ -111,11 +108,11 @@ GetPlatformTimerFreq ( UINTN
EFIAPI
MicroSecondDelay (
- IN UINTN MicroSeconds
+ IN UINTN MicroSeconds
)
{
- UINT64 TimerTicks64;
- UINT64 SystemCounterVal;
+ UINT64 TimerTicks64;
+ UINT64 SystemCounterVal;
// Calculate counter ticks that represent requested delay:
// = MicroSeconds x TICKS_PER_MICRO_SEC
@@ -141,7 +138,6 @@ MicroSecondDelay ( return MicroSeconds;
}
-
/**
Stalls the CPU for at least the given number of nanoseconds.
@@ -158,13 +154,13 @@ MicroSecondDelay ( UINTN
EFIAPI
NanoSecondDelay (
- IN UINTN NanoSeconds
+ IN UINTN NanoSeconds
)
{
UINTN MicroSeconds;
// Round up to 1us Tick Number
- MicroSeconds = NanoSeconds / 1000;
+ MicroSeconds = NanoSeconds / 1000;
MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1;
MicroSecondDelay (MicroSeconds);
@@ -219,13 +215,13 @@ GetPerformanceCounter ( UINT64
EFIAPI
GetPerformanceCounterProperties (
- OUT UINT64 *StartValue OPTIONAL,
- OUT UINT64 *EndValue OPTIONAL
+ OUT UINT64 *StartValue OPTIONAL,
+ OUT UINT64 *EndValue OPTIONAL
)
{
if (StartValue != NULL) {
// Timer starts at 0
- *StartValue = (UINT64)0ULL ;
+ *StartValue = (UINT64)0ULL;
}
if (EndValue != NULL) {
@@ -250,7 +246,7 @@ GetPerformanceCounterProperties ( UINT64
EFIAPI
GetTimeInNanoSecond (
- IN UINT64 Ticks
+ IN UINT64 Ticks
)
{
UINT64 NanoSeconds;
@@ -267,7 +263,8 @@ GetTimeInNanoSecond ( DivU64x32Remainder (
Ticks,
TimerFreq,
- &Remainder),
+ &Remainder
+ ),
1000000000U
);
@@ -277,8 +274,9 @@ GetTimeInNanoSecond ( //
NanoSeconds += DivU64x32 (
MULT_U64_X_N (
- (UINT64) Remainder,
- 1000000000U),
+ (UINT64)Remainder,
+ 1000000000U
+ ),
TimerFreq
);
diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c index db9290f275..bad5d244cb 100644 --- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c +++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c @@ -20,20 +20,21 @@ CacheRangeOperation ( IN UINTN LineLength
)
{
- UINTN ArmCacheLineAlignmentMask;
+ UINTN ArmCacheLineAlignmentMask;
// Align address (rounding down)
- UINTN AlignedAddress;
- UINTN EndAddress;
+ UINTN AlignedAddress;
+ UINTN EndAddress;
ArmCacheLineAlignmentMask = LineLength - 1;
- AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
- EndAddress = (UINTN)Start + Length;
+ AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
+ EndAddress = (UINTN)Start + Length;
// Perform the line operation on an address in each cache line
while (AlignedAddress < EndAddress) {
- LineOperation(AlignedAddress);
+ LineOperation (AlignedAddress);
AlignedAddress += LineLength;
}
+
ArmDataSynchronizationBarrier ();
}
@@ -58,15 +59,22 @@ InvalidateDataCache ( VOID *
EFIAPI
InvalidateInstructionCacheRange (
- IN VOID *Address,
- IN UINTN Length
+ IN VOID *Address,
+ IN UINTN Length
)
{
- CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA,
- ArmDataCacheLineLength ());
- CacheRangeOperation (Address, Length,
+ CacheRangeOperation (
+ Address,
+ Length,
+ ArmCleanDataCacheEntryToPoUByMVA,
+ ArmDataCacheLineLength ()
+ );
+ CacheRangeOperation (
+ Address,
+ Length,
ArmInvalidateInstructionCacheEntryToPoUByMVA,
- ArmInstructionCacheLineLength ());
+ ArmInstructionCacheLineLength ()
+ );
ArmInstructionSynchronizationBarrier ();
@@ -85,12 +93,16 @@ WriteBackInvalidateDataCache ( VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
- IN VOID *Address,
- IN UINTN Length
+ IN VOID *Address,
+ IN UINTN Length
)
{
- CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA,
- ArmDataCacheLineLength ());
+ CacheRangeOperation (
+ Address,
+ Length,
+ ArmCleanInvalidateDataCacheEntryByMVA,
+ ArmDataCacheLineLength ()
+ );
return Address;
}
@@ -106,23 +118,31 @@ WriteBackDataCache ( VOID *
EFIAPI
WriteBackDataCacheRange (
- IN VOID *Address,
- IN UINTN Length
+ IN VOID *Address,
+ IN UINTN Length
)
{
- CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA,
- ArmDataCacheLineLength ());
+ CacheRangeOperation (
+ Address,
+ Length,
+ ArmCleanDataCacheEntryByMVA,
+ ArmDataCacheLineLength ()
+ );
return Address;
}
VOID *
EFIAPI
InvalidateDataCacheRange (
- IN VOID *Address,
- IN UINTN Length
+ IN VOID *Address,
+ IN UINTN Length
)
{
- CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA,
- ArmDataCacheLineLength ());
+ CacheRangeOperation (
+ Address,
+ Length,
+ ArmInvalidateDataCacheEntryByMVA,
+ ArmDataCacheLineLength ()
+ );
return Address;
}
diff --git a/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c b/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c index 353f41bfba..ac334f0ebf 100644 --- a/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c +++ b/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c @@ -26,12 +26,12 @@ **/
VOID
DisassembleInstruction (
- IN UINT8 **OpCodePtr,
- IN BOOLEAN Thumb,
- IN BOOLEAN Extended,
- IN OUT UINT32 *ItBlock,
- OUT CHAR8 *Buf,
- OUT UINTN Size
+ IN UINT8 **OpCodePtr,
+ IN BOOLEAN Thumb,
+ IN BOOLEAN Extended,
+ IN OUT UINT32 *ItBlock,
+ OUT CHAR8 *Buf,
+ OUT UINTN Size
)
{
// Not yet supported for AArch64.
diff --git a/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c b/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c index 03a9f1fbe2..0e09062957 100644 --- a/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c +++ b/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c @@ -13,7 +13,7 @@ #include <Library/PrintLib.h>
#include <Library/ArmDisassemblerLib.h>
-CHAR8 *gCondition[] = {
+CHAR8 *gCondition[] = {
"EQ",
"NE",
"CS",
@@ -34,7 +34,7 @@ CHAR8 *gCondition[] = { #define COND(_a) gCondition[((_a) >> 28)]
-CHAR8 *gReg[] = {
+CHAR8 *gReg[] = {
"r0",
"r1",
"r2",
@@ -53,37 +53,36 @@ CHAR8 *gReg[] = { "pc"
};
-CHAR8 *gLdmAdr[] = {
+CHAR8 *gLdmAdr[] = {
"DA",
"IA",
"DB",
"IB"
};
-CHAR8 *gLdmStack[] = {
+CHAR8 *gLdmStack[] = {
"FA",
"FD",
"EA",
"ED"
};
-#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)])
+#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)])
+#define SIGN(_U) ((_U) ? "" : "-")
+#define WRITE(_Write) ((_Write) ? "!" : "")
+#define BYTE(_B) ((_B) ? "B":"")
+#define USER(_B) ((_B) ? "^" : "")
-#define SIGN(_U) ((_U) ? "" : "-")
-#define WRITE(_Write) ((_Write) ? "!" : "")
-#define BYTE(_B) ((_B) ? "B":"")
-#define USER(_B) ((_B) ? "^" : "")
-
-CHAR8 mMregListStr[4*15 + 1];
+CHAR8 mMregListStr[4*15 + 1];
CHAR8 *
MRegList (
UINT32 OpCode
)
{
- UINTN Index, Start, End;
- BOOLEAN First;
+ UINTN Index, Start, End;
+ BOOLEAN First;
mMregListStr[0] = '\0';
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "{");
@@ -110,9 +109,11 @@ MRegList ( }
}
}
+
if (First) {
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "ERROR");
}
+
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "}");
// BugBug: Make caller pass in buffer it is cleaner
@@ -129,14 +130,13 @@ FieldMask ( UINT32
RotateRight (
- IN UINT32 Op,
- IN UINT32 Shift
+ IN UINT32 Op,
+ IN UINT32 Shift
)
{
return (Op >> Shift) | (Op << (32 - Shift));
}
-
/**
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
point to next instruction.
@@ -152,39 +152,38 @@ RotateRight ( **/
VOID
DisassembleArmInstruction (
- IN UINT32 **OpCodePtr,
- OUT CHAR8 *Buf,
- OUT UINTN Size,
- IN BOOLEAN Extended
+ IN UINT32 **OpCodePtr,
+ OUT CHAR8 *Buf,
+ OUT UINTN Size,
+ IN BOOLEAN Extended
)
{
- UINT32 OpCode;
- CHAR8 *Type;
- CHAR8 *Root;
- BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;
- UINT32 Rn, Rd, Rm;
- UINT32 IMod, Offset8, Offset12;
- UINT32 Index;
- UINT32 ShiftImm, Shift;
+ UINT32 OpCode;
+ CHAR8 *Type;
+ CHAR8 *Root;
+ BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;
+ UINT32 Rn, Rd, Rm;
+ UINT32 IMod, Offset8, Offset12;
+ UINT32 Index;
+ UINT32 ShiftImm, Shift;
OpCode = **OpCodePtr;
- Imm = (OpCode & BIT25) == BIT25; // I
- Pre = (OpCode & BIT24) == BIT24; // P
- Up = (OpCode & BIT23) == BIT23; // U
+ Imm = (OpCode & BIT25) == BIT25; // I
+ Pre = (OpCode & BIT24) == BIT24; // P
+ Up = (OpCode & BIT23) == BIT23; // U
WriteBack = (OpCode & BIT22) == BIT22; // B, also called S
- Write = (OpCode & BIT21) == BIT21; // W
- Load = (OpCode & BIT20) == BIT20; // L
- Sign = (OpCode & BIT6) == BIT6; // S
- Half = (OpCode & BIT5) == BIT5; // H
- Rn = (OpCode >> 16) & 0xf;
- Rd = (OpCode >> 12) & 0xf;
- Rm = (OpCode & 0xf);
-
+ Write = (OpCode & BIT21) == BIT21; // W
+ Load = (OpCode & BIT20) == BIT20; // L
+ Sign = (OpCode & BIT6) == BIT6; // S
+ Half = (OpCode & BIT5) == BIT5; // H
+ Rn = (OpCode >> 16) & 0xf;
+ Rd = (OpCode >> 12) & 0xf;
+ Rm = (OpCode & 0xf);
if (Extended) {
Index = AsciiSPrint (Buf, Size, "0x%08x ", OpCode);
- Buf += Index;
+ Buf += Index;
Size -= Index;
}
@@ -194,9 +193,10 @@ DisassembleArmInstruction ( // A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
} else {
- // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
+ // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);
}
+
return;
}
@@ -206,23 +206,25 @@ DisassembleArmInstruction ( // A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
- AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
+ AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
} else {
// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
- AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
+ AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
}
+
return;
}
// LDR/STR Address Mode 2
- if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) {
+ if (((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000) == 0xf550f000)) {
Offset12 = OpCode & 0xfff;
- if ((OpCode & 0xfd70f000 ) == 0xf550f000) {
+ if ((OpCode & 0xfd70f000) == 0xf550f000) {
Index = AsciiSPrint (Buf, Size, "PLD");
} else {
- Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T":"", gReg[Rd]);
+ Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T" : "", gReg[Rd]);
}
+
if (Pre) {
if (!Imm) {
// A5.2.2 [<Rn>, #+/-<offset_12>]
@@ -236,7 +238,7 @@ DisassembleArmInstruction ( // A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
ShiftImm = (OpCode >> 7) & 0x1f;
- Shift = (OpCode >> 5) & 0x3;
+ Shift = (OpCode >> 5) & 0x3;
if (Shift == 0x0) {
Type = "LSL";
} else if (Shift == 0x1) {
@@ -255,7 +257,8 @@ DisassembleArmInstruction ( AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write));
}
- } else { // !Pre
+ } else {
+ // !Pre
if (!Imm) {
// A5.2.8 [<Rn>], #+/-<offset_12>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12);
@@ -265,7 +268,7 @@ DisassembleArmInstruction ( } else {
// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>
ShiftImm = (OpCode >> 7) & 0x1f;
- Shift = (OpCode >> 5) & 0x3;
+ Shift = (OpCode >> 5) & 0x3;
if (Shift == 0x0) {
Type = "LSL";
@@ -287,6 +290,7 @@ DisassembleArmInstruction ( AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm);
}
}
+
return;
}
@@ -313,30 +317,31 @@ DisassembleArmInstruction ( Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
- Sign = (OpCode & BIT6) == BIT6;
- Half = (OpCode & BIT5) == BIT5;
+ Sign = (OpCode & BIT6) == BIT6;
+ Half = (OpCode & BIT5) == BIT5;
Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
if (Pre & !Write) {
// Immediate offset/index
if (WriteBack) {
// A5.3.2 [<Rn>, #+/-<offset_8>]
// A5.3.4 [<Rn>, #+/-<offset_8>]!
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));
} else {
// A5.3.3 [<Rn>, +/-<Rm>]
// A5.3.5 [<Rn>, +/-<Rm>]!
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
}
} else {
// Register offset/index
if (WriteBack) {
// A5.3.6 [<Rn>], #+/-<offset_8>
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);
} else {
// A5.3.7 [<Rn>], +/-<Rm>
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
}
}
+
return;
}
@@ -370,16 +375,21 @@ DisassembleArmInstruction ( if (((OpCode >> 6) & 0x7) == 0) {
AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
} else {
- IMod = (OpCode >> 18) & 0x3;
- Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a",
- (IMod == 3) ? "ID":"IE",
- ((OpCode & BIT8) != 0) ? "A":"",
- ((OpCode & BIT7) != 0) ? "I":"",
- ((OpCode & BIT6) != 0) ? "F":"");
+ IMod = (OpCode >> 18) & 0x3;
+ Index = AsciiSPrint (
+ Buf,
+ Size,
+ "CPS%a %a%a%a",
+ (IMod == 3) ? "ID" : "IE",
+ ((OpCode & BIT8) != 0) ? "A" : "",
+ ((OpCode & BIT7) != 0) ? "I" : "",
+ ((OpCode & BIT6) != 0) ? "F" : ""
+ );
if ((OpCode & BIT17) != 0) {
AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f);
}
}
+
return;
}
@@ -395,16 +405,16 @@ DisassembleArmInstruction ( return;
}
-
if ((OpCode & 0x0db00000) == 0x01200000) {
// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>
if (Imm) {
// MSR{<cond>} CPSR_<fields>, #<immediate>
- AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
+ AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
} else {
// MSR{<cond>} CPSR_<fields>, <Rm>
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]);
}
+
return;
}
@@ -417,35 +427,34 @@ DisassembleArmInstruction ( if ((OpCode & 0x0e000000) == 0x0c000000) {
// A4.1.19 LDC and A4.1.96 SDC
if ((OpCode & 0xf0000000) == 0xf0000000) {
- Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
+ Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC" : "SDC", (OpCode >> 8) & 0xf, Rd);
} else {
- Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
+ Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC" : "SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
}
if (!Pre) {
if (!Write) {
// A5.5.5.5 [<Rn>], <option>
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
} else {
// A.5.5.4 [<Rn>], #+/-<offset_8>*4
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);
}
} else {
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write));
}
-
}
if ((OpCode & 0x0f000010) == 0x0e000010) {
// A4.1.32 MRC2, MCR2
- AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
+ AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC" : "MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
return;
}
if ((OpCode & 0x0ff00000) == 0x0c400000) {
// A4.1.33 MRRC2, MCRR2
- AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
+ AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC" : "MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
return;
}
@@ -454,4 +463,3 @@ DisassembleArmInstruction ( *OpCodePtr += 1;
return;
}
-
diff --git a/ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c b/ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c index 3129ec6b92..6dae7a9121 100644 --- a/ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c +++ b/ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c @@ -20,24 +20,24 @@ #include <Library/DebugLib.h>
#include <Library/PrintLib.h>
-extern CHAR8 *gCondition[];
+extern CHAR8 *gCondition[];
-extern CHAR8 *gReg[];
+extern CHAR8 *gReg[];
// Thumb address modes
-#define LOAD_STORE_FORMAT1 1
-#define LOAD_STORE_FORMAT1_H 101
-#define LOAD_STORE_FORMAT1_B 111
-#define LOAD_STORE_FORMAT2 2
-#define LOAD_STORE_FORMAT3 3
-#define LOAD_STORE_FORMAT4 4
-#define LOAD_STORE_MULTIPLE_FORMAT1 5
-#define PUSH_FORMAT 6
-#define POP_FORMAT 106
-#define IMMED_8 7
-#define CONDITIONAL_BRANCH 8
-#define UNCONDITIONAL_BRANCH 9
-#define UNCONDITIONAL_BRANCH_SHORT 109
+#define LOAD_STORE_FORMAT1 1
+#define LOAD_STORE_FORMAT1_H 101
+#define LOAD_STORE_FORMAT1_B 111
+#define LOAD_STORE_FORMAT2 2
+#define LOAD_STORE_FORMAT3 3
+#define LOAD_STORE_FORMAT4 4
+#define LOAD_STORE_MULTIPLE_FORMAT1 5
+#define PUSH_FORMAT 6
+#define POP_FORMAT 106
+#define IMMED_8 7
+#define CONDITIONAL_BRANCH 8
+#define UNCONDITIONAL_BRANCH 9
+#define UNCONDITIONAL_BRANCH_SHORT 109
#define BRANCH_EXCHANGE 10
#define DATA_FORMAT1 11
#define DATA_FORMAT2 12
@@ -45,7 +45,7 @@ extern CHAR8 *gReg[]; #define DATA_FORMAT4 14
#define DATA_FORMAT5 15
#define DATA_FORMAT6_SP 16
-#define DATA_FORMAT6_PC 116
+#define DATA_FORMAT6_PC 116
#define DATA_FORMAT7 17
#define DATA_FORMAT8 19
#define CPS_FORMAT 20
@@ -55,344 +55,338 @@ extern CHAR8 *gReg[]; #define IT_BLOCK 24
// Thumb2 address modes
-#define B_T3 200
-#define B_T4 201
-#define BL_T2 202
-#define POP_T2 203
-#define POP_T3 204
-#define STM_FORMAT 205
-#define LDM_REG_IMM12_SIGNED 206
-#define LDM_REG_IMM12_LSL 207
-#define LDM_REG_IMM8 208
-#define LDM_REG_IMM12 209
-#define LDM_REG_INDIRECT_LSL 210
-#define LDM_REG_IMM8_SIGNED 211
-#define LDRD_REG_IMM8 212
-#define LDREXB 213
-#define LDREXD 214
-#define SRS_FORMAT 215
-#define RFE_FORMAT 216
-#define LDRD_REG_IMM8_SIGNED 217
-#define ADD_IMM12 218
-#define ADD_IMM5 219
-#define ADR_THUMB2 220
-#define CMN_THUMB2 221
-#define ASR_IMM5 222
-#define ASR_3REG 223
-#define BFC_THUMB2 224
-#define CDP_THUMB2 225
-#define THUMB2_NO_ARGS 226
-#define THUMB2_2REGS 227
-#define ADD_IMM5_2REG 228
-#define CPD_THUMB2 229
-#define THUMB2_4REGS 230
-#define ADD_IMM12_1REG 231
-#define THUMB2_IMM16 232
-#define MRC_THUMB2 233
-#define MRRC_THUMB2 234
-#define THUMB2_MRS 235
-#define THUMB2_MSR 236
-
-
-
+#define B_T3 200
+#define B_T4 201
+#define BL_T2 202
+#define POP_T2 203
+#define POP_T3 204
+#define STM_FORMAT 205
+#define LDM_REG_IMM12_SIGNED 206
+#define LDM_REG_IMM12_LSL 207
+#define LDM_REG_IMM8 208
+#define LDM_REG_IMM12 209
+#define LDM_REG_INDIRECT_LSL 210
+#define LDM_REG_IMM8_SIGNED 211
+#define LDRD_REG_IMM8 212
+#define LDREXB 213
+#define LDREXD 214
+#define SRS_FORMAT 215
+#define RFE_FORMAT 216
+#define LDRD_REG_IMM8_SIGNED 217
+#define ADD_IMM12 218
+#define ADD_IMM5 219
+#define ADR_THUMB2 220
+#define CMN_THUMB2 221
+#define ASR_IMM5 222
+#define ASR_3REG 223
+#define BFC_THUMB2 224
+#define CDP_THUMB2 225
+#define THUMB2_NO_ARGS 226
+#define THUMB2_2REGS 227
+#define ADD_IMM5_2REG 228
+#define CPD_THUMB2 229
+#define THUMB2_4REGS 230
+#define ADD_IMM12_1REG 231
+#define THUMB2_IMM16 232
+#define MRC_THUMB2 233
+#define MRRC_THUMB2 234
+#define THUMB2_MRS 235
+#define THUMB2_MSR 236
typedef struct {
- CHAR8 *Start;
- UINT32 OpCode;
- UINT32 Mask;
- UINT32 AddressMode;
+ CHAR8 *Start;
+ UINT32 OpCode;
+ UINT32 Mask;
+ UINT32 AddressMode;
} THUMB_INSTRUCTIONS;
-THUMB_INSTRUCTIONS gOpThumb[] = {
-// Thumb 16-bit instructions
-// Op Mask Format
- { "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 }, // ADC <Rndn>, <Rm>
- { "ADR", 0xa000, 0xf800, ADR_FORMAT }, // ADR <Rd>, <label>
- { "ADD" , 0x1c00, 0xfe00, DATA_FORMAT2 },
- { "ADD" , 0x3000, 0xf800, DATA_FORMAT3 },
- { "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },
- { "ADD" , 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9
- { "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC },
- { "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP },
- { "ADD" , 0xb000, 0xff80, DATA_FORMAT7 },
-
- { "AND" , 0x4000, 0xffc0, DATA_FORMAT5 },
-
- { "ASR" , 0x1000, 0xf800, DATA_FORMAT4 },
- { "ASR" , 0x4100, 0xffc0, DATA_FORMAT5 },
-
- { "B" , 0xd000, 0xf000, CONDITIONAL_BRANCH },
- { "B" , 0xe000, 0xf800, UNCONDITIONAL_BRANCH_SHORT },
- { "BLX" , 0x4780, 0xff80, BRANCH_EXCHANGE },
- { "BX" , 0x4700, 0xff87, BRANCH_EXCHANGE },
-
- { "BIC" , 0x4380, 0xffc0, DATA_FORMAT5 },
- { "BKPT", 0xdf00, 0xff00, IMMED_8 },
- { "CBZ", 0xb100, 0xfd00, DATA_CBZ },
- { "CBNZ", 0xb900, 0xfd00, DATA_CBZ },
- { "CMN" , 0x42c0, 0xffc0, DATA_FORMAT5 },
-
- { "CMP" , 0x2800, 0xf800, DATA_FORMAT3 },
- { "CMP" , 0x4280, 0xffc0, DATA_FORMAT5 },
- { "CMP" , 0x4500, 0xff00, DATA_FORMAT8 },
-
- { "CPS" , 0xb660, 0xffe8, CPS_FORMAT },
- { "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },
- { "EOR" , 0x4040, 0xffc0, DATA_FORMAT5 },
-
- { "LDMIA" , 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
- { "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 }, // LDR <Rt>, [<Rn> {,#<imm>}]
- { "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
- { "LDR" , 0x4800, 0xf800, LOAD_STORE_FORMAT3 },
- { "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 }, // LDR <Rt>, [SP, #<imm>]
- { "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1_B },
- { "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
- { "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1_H },
- { "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },
- { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
- { "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },
-
- { "MOVS", 0x0000, 0xffc0, DATA_FORMAT5 }, // LSL with imm5 == 0 is a MOVS, so this must go before LSL
- { "LSL" , 0x0000, 0xf800, DATA_FORMAT4 },
- { "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },
- { "LSR" , 0x0001, 0xf800, DATA_FORMAT4 },
- { "LSR" , 0x40c0, 0xffc0, DATA_FORMAT5 },
- { "LSRS", 0x0800, 0xf800, DATA_FORMAT4 }, // LSRS <Rd>, <Rm>, #<imm5>
-
- { "MOVS", 0x2000, 0xf800, DATA_FORMAT3 },
- { "MOV" , 0x1c00, 0xffc0, DATA_FORMAT3 },
- { "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },
-
- { "MUL" , 0x4340, 0xffc0, DATA_FORMAT5 },
- { "MVN" , 0x41c0, 0xffc0, DATA_FORMAT5 },
- { "NEG" , 0x4240, 0xffc0, DATA_FORMAT5 },
- { "ORR" , 0x4300, 0xffc0, DATA_FORMAT5 },
- { "POP" , 0xbc00, 0xfe00, POP_FORMAT },
- { "PUSH", 0xb400, 0xfe00, PUSH_FORMAT },
-
- { "REV" , 0xba00, 0xffc0, DATA_FORMAT5 },
- { "REV16" , 0xba40, 0xffc0, DATA_FORMAT5 },
- { "REVSH" , 0xbac0, 0xffc0, DATA_FORMAT5 },
-
- { "ROR" , 0x41c0, 0xffc0, DATA_FORMAT5 },
- { "SBC" , 0x4180, 0xffc0, DATA_FORMAT5 },
- { "SETEND" , 0xb650, 0xfff0, ENDIAN_FORMAT },
-
- { "STMIA" , 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
- { "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 }, // STR <Rt>, [<Rn> {,#<imm>}]
- { "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
- { "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 }, // STR <Rt>, [SP, #<imm>]
- { "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1_B }, // STRB <Rt>, [<Rn>, #<imm5>]
- { "STRB" , 0x5400, 0xfe00, LOAD_STORE_FORMAT2 }, // STRB <Rt>, [<Rn>, <Rm>]
- { "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1_H }, // STRH <Rt>, [<Rn>{,#<imm>}]
- { "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 }, // STRH <Rt>, [<Rn>, <Rm>]
-
- { "SUB" , 0x1e00, 0xfe00, DATA_FORMAT2 },
- { "SUB" , 0x3800, 0xf800, DATA_FORMAT3 },
- { "SUB" , 0x1a00, 0xfe00, DATA_FORMAT1 },
- { "SUB" , 0xb080, 0xff80, DATA_FORMAT7 },
-
- { "SBC" , 0x4180, 0xffc0, DATA_FORMAT5 },
-
- { "SWI" , 0xdf00, 0xff00, IMMED_8 },
- { "SXTB", 0xb240, 0xffc0, DATA_FORMAT5 },
- { "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },
- { "TST" , 0x4200, 0xffc0, DATA_FORMAT5 },
- { "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },
- { "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 },
-
- { "IT", 0xbf00, 0xff00, IT_BLOCK }
-
+THUMB_INSTRUCTIONS gOpThumb[] = {
+ // Thumb 16-bit instructions
+ // Op Mask Format
+ { "ADC", 0x4140, 0xffc0, DATA_FORMAT5 }, // ADC <Rndn>, <Rm>
+ { "ADR", 0xa000, 0xf800, ADR_FORMAT }, // ADR <Rd>, <label>
+ { "ADD", 0x1c00, 0xfe00, DATA_FORMAT2 },
+ { "ADD", 0x3000, 0xf800, DATA_FORMAT3 },
+ { "ADD", 0x1800, 0xfe00, DATA_FORMAT1 },
+ { "ADD", 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9
+ { "ADD", 0xa000, 0xf100, DATA_FORMAT6_PC },
+ { "ADD", 0xa800, 0xf800, DATA_FORMAT6_SP },
+ { "ADD", 0xb000, 0xff80, DATA_FORMAT7 },
+
+ { "AND", 0x4000, 0xffc0, DATA_FORMAT5 },
+
+ { "ASR", 0x1000, 0xf800, DATA_FORMAT4 },
+ { "ASR", 0x4100, 0xffc0, DATA_FORMAT5 },
+
+ { "B", 0xd000, 0xf000, CONDITIONAL_BRANCH },
+ { "B", 0xe000, 0xf800, UNCONDITIONAL_BRANCH_SHORT },
+ { "BLX", 0x4780, 0xff80, BRANCH_EXCHANGE },
+ { "BX", 0x4700, 0xff87, BRANCH_EXCHANGE },
+
+ { "BIC", 0x4380, 0xffc0, DATA_FORMAT5 },
+ { "BKPT", 0xdf00, 0xff00, IMMED_8 },
+ { "CBZ", 0xb100, 0xfd00, DATA_CBZ },
+ { "CBNZ", 0xb900, 0xfd00, DATA_CBZ },
+ { "CMN", 0x42c0, 0xffc0, DATA_FORMAT5 },
+
+ { "CMP", 0x2800, 0xf800, DATA_FORMAT3 },
+ { "CMP", 0x4280, 0xffc0, DATA_FORMAT5 },
+ { "CMP", 0x4500, 0xff00, DATA_FORMAT8 },
+
+ { "CPS", 0xb660, 0xffe8, CPS_FORMAT },
+ { "MOV", 0x4600, 0xff00, DATA_FORMAT8 },
+ { "EOR", 0x4040, 0xffc0, DATA_FORMAT5 },
+
+ { "LDMIA", 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
+ { "LDR", 0x6800, 0xf800, LOAD_STORE_FORMAT1 }, // LDR <Rt>, [<Rn> {,#<imm>}]
+ { "LDR", 0x5800, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
+ { "LDR", 0x4800, 0xf800, LOAD_STORE_FORMAT3 },
+ { "LDR", 0x9800, 0xf800, LOAD_STORE_FORMAT4 }, // LDR <Rt>, [SP, #<imm>]
+ { "LDRB", 0x7800, 0xf800, LOAD_STORE_FORMAT1_B },
+ { "LDRB", 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
+ { "LDRH", 0x8800, 0xf800, LOAD_STORE_FORMAT1_H },
+ { "LDRH", 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },
+ { "LDRSB", 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
+ { "LDRSH", 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },
+
+ { "MOVS", 0x0000, 0xffc0, DATA_FORMAT5 }, // LSL with imm5 == 0 is a MOVS, so this must go before LSL
+ { "LSL", 0x0000, 0xf800, DATA_FORMAT4 },
+ { "LSL", 0x4080, 0xffc0, DATA_FORMAT5 },
+ { "LSR", 0x0001, 0xf800, DATA_FORMAT4 },
+ { "LSR", 0x40c0, 0xffc0, DATA_FORMAT5 },
+ { "LSRS", 0x0800, 0xf800, DATA_FORMAT4 }, // LSRS <Rd>, <Rm>, #<imm5>
+
+ { "MOVS", 0x2000, 0xf800, DATA_FORMAT3 },
+ { "MOV", 0x1c00, 0xffc0, DATA_FORMAT3 },
+ { "MOV", 0x4600, 0xff00, DATA_FORMAT8 },
+
+ { "MUL", 0x4340, 0xffc0, DATA_FORMAT5 },
+ { "MVN", 0x41c0, 0xffc0, DATA_FORMAT5 },
+ { "NEG", 0x4240, 0xffc0, DATA_FORMAT5 },
+ { "ORR", 0x4300, 0xffc0, DATA_FORMAT5 },
+ { "POP", 0xbc00, 0xfe00, POP_FORMAT },
+ { "PUSH", 0xb400, 0xfe00, PUSH_FORMAT },
+
+ { "REV", 0xba00, 0xffc0, DATA_FORMAT5 },
+ { "REV16", 0xba40, 0xffc0, DATA_FORMAT5 },
+ { "REVSH", 0xbac0, 0xffc0, DATA_FORMAT5 },
+
+ { "ROR", 0x41c0, 0xffc0, DATA_FORMAT5 },
+ { "SBC", 0x4180, 0xffc0, DATA_FORMAT5 },
+ { "SETEND", 0xb650, 0xfff0, ENDIAN_FORMAT },
+
+ { "STMIA", 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
+ { "STR", 0x6000, 0xf800, LOAD_STORE_FORMAT1 }, // STR <Rt>, [<Rn> {,#<imm>}]
+ { "STR", 0x5000, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
+ { "STR", 0x9000, 0xf800, LOAD_STORE_FORMAT4 }, // STR <Rt>, [SP, #<imm>]
+ { "STRB", 0x7000, 0xf800, LOAD_STORE_FORMAT1_B }, // STRB <Rt>, [<Rn>, #<imm5>]
+ { "STRB", 0x5400, 0xfe00, LOAD_STORE_FORMAT2 }, // STRB <Rt>, [<Rn>, <Rm>]
+ { "STRH", 0x8000, 0xf800, LOAD_STORE_FORMAT1_H }, // STRH <Rt>, [<Rn>{,#<imm>}]
+ { "STRH", 0x5200, 0xfe00, LOAD_STORE_FORMAT2 }, // STRH <Rt>, [<Rn>, <Rm>]
+
+ { "SUB", 0x1e00, 0xfe00, DATA_FORMAT2 },
+ { "SUB", 0x3800, 0xf800, DATA_FORMAT3 },
+ { "SUB", 0x1a00, 0xfe00, DATA_FORMAT1 },
+ { "SUB", 0xb080, 0xff80, DATA_FORMAT7 },
+
+ { "SBC", 0x4180, 0xffc0, DATA_FORMAT5 },
+
+ { "SWI", 0xdf00, 0xff00, IMMED_8 },
+ { "SXTB", 0xb240, 0xffc0, DATA_FORMAT5 },
+ { "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },
+ { "TST", 0x4200, 0xffc0, DATA_FORMAT5 },
+ { "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },
+ { "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 },
+
+ { "IT", 0xbf00, 0xff00, IT_BLOCK }
};
-THUMB_INSTRUCTIONS gOpThumb2[] = {
-//Instruct OpCode OpCode Mask Addressig Mode
-
- { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW
- { "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2 }, // CMN <Rn>, #<const> ;Needs to go before ADD
- { "CMN", 0xeb100f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
- { "CMP", 0xf1a00f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
- { "TEQ", 0xf0900f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
- { "TEQ", 0xea900f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
- { "TST", 0xf0100f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
- { "TST", 0xea100f00, 0xfff08f00, ADD_IMM5_2REG }, // TST <Rn>, <Rm> {,<shift> #<const>}
-
- { "MOV", 0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV <Rd>, #<const>
- { "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 }, // MOVW <Rd>, #<const>
- { "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 }, // MOVT <Rd>, #<const>
-
- { "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>
- { "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>
- { "ADD", 0xeb000000, 0xffe08000, ADD_IMM5 }, // ADD{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "ADDW", 0xf2000000, 0xfbe08000, ADD_IMM12 }, // ADDW{S} <Rd>, <Rn>, #<const>
- { "AND", 0xf0000000, 0xfbe08000, ADD_IMM12 }, // AND{S} <Rd>, <Rn>, #<const>
- { "AND", 0xea000000, 0xffe08000, ADD_IMM5 }, // AND{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "BIC", 0xf0200000, 0xfbe08000, ADD_IMM12 }, // BIC{S} <Rd>, <Rn>, #<const>
- { "BIC", 0xea200000, 0xffe08000, ADD_IMM5 }, // BIC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "EOR", 0xf0800000, 0xfbe08000, ADD_IMM12 }, // EOR{S} <Rd>, <Rn>, #<const>
- { "EOR", 0xea800000, 0xffe08000, ADD_IMM5 }, // EOR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "ORN", 0xf0600000, 0xfbe08000, ADD_IMM12 }, // ORN{S} <Rd>, <Rn>, #<const>
- { "ORN", 0xea600000, 0xffe08000, ADD_IMM5 }, // ORN{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "ORR", 0xf0400000, 0xfbe08000, ADD_IMM12 }, // ORR{S} <Rd>, <Rn>, #<const>
- { "ORR", 0xea400000, 0xffe08000, ADD_IMM5 }, // ORR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "RSB", 0xf1c00000, 0xfbe08000, ADD_IMM12 }, // RSB{S} <Rd>, <Rn>, #<const>
- { "RSB", 0xebc00000, 0xffe08000, ADD_IMM5 }, // RSB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "SBC", 0xf1600000, 0xfbe08000, ADD_IMM12 }, // SBC{S} <Rd>, <Rn>, #<const>
- { "SBC", 0xeb600000, 0xffe08000, ADD_IMM5 }, // SBC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "SUB", 0xf1a00000, 0xfbe08000, ADD_IMM12 }, // SUB{S} <Rd>, <Rn>, #<const>
- { "SUB", 0xeba00000, 0xffe08000, ADD_IMM5 }, // SUB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
-
- { "ASR", 0xea4f0020, 0xffef8030, ASR_IMM5 }, // ARS <Rd>, <Rm> #<const>} imm3:imm2
- { "ASR", 0xfa40f000, 0xffe0f0f0, ASR_3REG }, // ARS <Rd>, <Rn>, <Rm>
- { "LSR", 0xea4f0010, 0xffef8030, ASR_IMM5 }, // LSR <Rd>, <Rm> #<const>} imm3:imm2
- { "LSR", 0xfa20f000, 0xffe0f0f0, ASR_3REG }, // LSR <Rd>, <Rn>, <Rm>
- { "ROR", 0xea4f0030, 0xffef8030, ASR_IMM5 }, // ROR <Rd>, <Rm> #<const>} imm3:imm2
- { "ROR", 0xfa60f000, 0xffe0f0f0, ASR_3REG }, // ROR <Rd>, <Rn>, <Rm>
-
- { "BFC", 0xf36f0000, 0xffff8010, BFC_THUMB2 }, // BFC <Rd>, #<lsb>, #<width>
- { "BIC", 0xf3600000, 0xfff08010, BFC_THUMB2 }, // BIC <Rn>, <Rd>, #<lsb>, #<width>
- { "SBFX", 0xf3400000, 0xfff08010, BFC_THUMB2 }, // SBFX <Rn>, <Rd>, #<lsb>, #<width>
- { "UBFX", 0xf3c00000, 0xfff08010, BFC_THUMB2 }, // UBFX <Rn>, <Rd>, #<lsb>, #<width>
-
- { "CPD", 0xee000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
- { "CPD2", 0xfe000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
-
- { "MRC", 0xee100000, 0xff100000, MRC_THUMB2 }, // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
- { "MRC2", 0xfe100000, 0xff100000, MRC_THUMB2 }, // MRC2 <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
- { "MRRC", 0xec500000, 0xfff00000, MRRC_THUMB2 }, // MRRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
- { "MRRC2", 0xfc500000, 0xfff00000, MRRC_THUMB2 }, // MRR2 <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
-
- { "MRS", 0xf3ef8000, 0xfffff0ff, THUMB2_MRS }, // MRS <Rd>, CPSR
- { "MSR", 0xf3808000, 0xfff0fcff, THUMB2_MSR }, // MSR CPSR_fs, <Rn>
-
- { "CLREX", 0xf3bf8f2f, 0xfffffff, THUMB2_NO_ARGS }, // CLREX
-
- { "CLZ", 0xfab0f080, 0xfff0f0f0, THUMB2_2REGS }, // CLZ <Rd>,<Rm>
- { "MOV", 0xec4f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOV <Rd>,<Rm>
- { "MOVS", 0xec5f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOVS <Rd>,<Rm>
- { "RBIT", 0xfb90f0a0, 0xfff0f0f0, THUMB2_2REGS }, // RBIT <Rd>,<Rm>
- { "REV", 0xfb90f080, 0xfff0f0f0, THUMB2_2REGS }, // REV <Rd>,<Rm>
- { "REV16", 0xfa90f090, 0xfff0f0f0, THUMB2_2REGS }, // REV16 <Rd>,<Rm>
- { "REVSH", 0xfa90f0b0, 0xfff0f0f0, THUMB2_2REGS }, // REVSH <Rd>,<Rm>
- { "RRX", 0xea4f0030, 0xfffff0f0, THUMB2_2REGS }, // RRX <Rd>,<Rm>
- { "RRXS", 0xea5f0030, 0xfffff0f0, THUMB2_2REGS }, // RRXS <Rd>,<Rm>
-
- { "MLA", 0xfb000000, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>
- { "MLS", 0xfb000010, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>
-
-
- { "SMLABB", 0xfb100000, 0xfff000f0, THUMB2_4REGS }, // SMLABB <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLABT", 0xfb100010, 0xfff000f0, THUMB2_4REGS }, // SMLABT <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLABB", 0xfb100020, 0xfff000f0, THUMB2_4REGS }, // SMLATB <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLATT", 0xfb100030, 0xfff000f0, THUMB2_4REGS }, // SMLATT <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLAWB", 0xfb300000, 0xfff000f0, THUMB2_4REGS }, // SMLAWB <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLAWT", 0xfb300010, 0xfff000f0, THUMB2_4REGS }, // SMLAWT <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLSD", 0xfb400000, 0xfff000f0, THUMB2_4REGS }, // SMLSD <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLSDX", 0xfb400010, 0xfff000f0, THUMB2_4REGS }, // SMLSDX <Rd>, <Rn>, <Rm>, <Ra>
- { "SMMLA", 0xfb500000, 0xfff000f0, THUMB2_4REGS }, // SMMLA <Rd>, <Rn>, <Rm>, <Ra>
- { "SMMLAR", 0xfb500010, 0xfff000f0, THUMB2_4REGS }, // SMMLAR <Rd>, <Rn>, <Rm>, <Ra>
- { "SMMLS", 0xfb600000, 0xfff000f0, THUMB2_4REGS }, // SMMLS <Rd>, <Rn>, <Rm>, <Ra>
- { "SMMLSR", 0xfb600010, 0xfff000f0, THUMB2_4REGS }, // SMMLSR <Rd>, <Rn>, <Rm>, <Ra>
- { "USADA8", 0xfb700000, 0xfff000f0, THUMB2_4REGS }, // USADA8 <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLAD", 0xfb200000, 0xfff000f0, THUMB2_4REGS }, // SMLAD <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLADX", 0xfb200010, 0xfff000f0, THUMB2_4REGS }, // SMLADX <Rd>, <Rn>, <Rm>, <Ra>
-
-
- { "B", 0xf0008000, 0xf800d000, B_T3 }, // B<c> <label>
- { "B", 0xf0009000, 0xf800d000, B_T4 }, // B<c> <label>
- { "BL", 0xf000d000, 0xf800d000, B_T4 }, // BL<c> <label>
- { "BLX", 0xf000c000, 0xf800d000, BL_T2 }, // BLX<c> <label>
-
- { "POP", 0xe8bd0000, 0xffff2000, POP_T2 }, // POP <registers>
- { "POP", 0xf85d0b04, 0xffff0fff, POP_T3 }, // POP <register>
- { "PUSH", 0xe8ad0000, 0xffffa000, POP_T2 }, // PUSH <registers>
- { "PUSH", 0xf84d0d04, 0xffff0fff, POP_T3 }, // PUSH <register>
- { "STM" , 0xe8800000, 0xffd0a000, STM_FORMAT }, // STM <Rn>{!},<registers>
- { "STMDB", 0xe9800000, 0xffd0a000, STM_FORMAT }, // STMDB <Rn>{!},<registers>
- { "LDM" , 0xe8900000, 0xffd02000, STM_FORMAT }, // LDM <Rn>{!},<registers>
- { "LDMDB", 0xe9100000, 0xffd02000, STM_FORMAT }, // LDMDB <Rn>{!},<registers>
-
- { "LDR", 0xf8d00000, 0xfff00000, LDM_REG_IMM12 }, // LDR <rt>, [<rn>, {, #<imm12>]}
- { "LDRB", 0xf8900000, 0xfff00000, LDM_REG_IMM12 }, // LDRB <rt>, [<rn>, {, #<imm12>]}
- { "LDRH", 0xf8b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRH <rt>, [<rn>, {, #<imm12>]}
- { "LDRSB", 0xf9900000, 0xfff00000, LDM_REG_IMM12 }, // LDRSB <rt>, [<rn>, {, #<imm12>]}
- { "LDRSH", 0xf9b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRSH <rt>, [<rn>, {, #<imm12>]}
-
- { "LDR", 0xf85f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDR <Rt>, <label>
- { "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label>
- { "LDRH", 0xf83f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRH <Rt>, <label>
- { "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
- { "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
-
- { "LDR", 0xf8500000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDR <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- { "LDRB", 0xf8100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- { "LDRH", 0xf8300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- { "LDRSB", 0xf9100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- { "LDRSH", 0xf9300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
-
- { "LDR", 0xf8500800, 0xfff00800, LDM_REG_IMM8 }, // LDR <rt>, [<rn>, {, #<imm8>]}
- { "LDRBT", 0xf8100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRBT <rt>, [<rn>, {, #<imm8>]}
- { "LDRHT", 0xf8300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]}
- { "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form?
- { "LDRSBT",0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form?
- { "LDRSH" ,0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]}
- { "LDRSHT",0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]}
- { "LDRT", 0xf8500e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRT <rt>, [<rn>, {, #<imm8>]}
-
- { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
- { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8 }, // LDRD <rt>, <rt2>, <label>
-
- { "LDREX", 0xe8500f00, 0xfff00f00, LDM_REG_IMM8 }, // LDREX <Rt>, [Rn, {#imm8}]]
- { "LDREXB", 0xe8d00f4f, 0xfff00fff, LDREXB }, // LDREXB <Rt>, [<Rn>]
- { "LDREXH", 0xe8d00f5f, 0xfff00fff, LDREXB }, // LDREXH <Rt>, [<Rn>]
-
- { "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>]
-
- { "STR", 0xf8c00000, 0xfff00000, LDM_REG_IMM12 }, // STR <rt>, [<rn>, {, #<imm12>]}
- { "STRB", 0xf8800000, 0xfff00000, LDM_REG_IMM12 }, // STRB <rt>, [<rn>, {, #<imm12>]}
- { "STRH", 0xf8a00000, 0xfff00000, LDM_REG_IMM12 }, // STRH <rt>, [<rn>, {, #<imm12>]}
-
- { "STR", 0xf8400000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STR <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- { "STRB", 0xf8000000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- { "STRH", 0xf8200000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
-
- { "STR", 0xf8400800, 0xfff00800, LDM_REG_IMM8 }, // STR <rt>, [<rn>, {, #<imm8>]}
- { "STRH", 0xf8200800, 0xfff00800, LDM_REG_IMM8 }, // STRH <rt>, [<rn>, {, #<imm8>]}
- { "STRBT", 0xf8000e00, 0xfff00f00, LDM_REG_IMM8 }, // STRBT <rt>, [<rn>, {, #<imm8>]}
- { "STRHT", 0xf8200e00, 0xfff00f00, LDM_REG_IMM8 }, // STRHT <rt>, [<rn>, {, #<imm8>]}
- { "STRT", 0xf8400e00, 0xfff00f00, LDM_REG_IMM8 }, // STRT <rt>, [<rn>, {, #<imm8>]}
-
- { "STRD", 0xe8400000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // STRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
-
- { "STREX", 0xe8400f00, 0xfff00f00, LDM_REG_IMM8 }, // STREX <Rt>, [Rn, {#imm8}]]
- { "STREXB", 0xe8c00f4f, 0xfff00fff, LDREXB }, // STREXB <Rd>, <Rt>, [<Rn>]
- { "STREXH", 0xe8c00f5f, 0xfff00fff, LDREXB }, // STREXH <Rd>, <Rt>, [<Rn>]
-
- { "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>]
-
- { "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>
- { "SRS" , 0xe98dc000, 0xffdffff0, SRS_FORMAT }, // SRS{IA}<c> SP{!},#<mode>
- { "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT }, // RFEDB<c> <Rn>{!}
- { "RFE" , 0xe990c000, 0xffd0ffff, RFE_FORMAT } // RFE{IA}<c> <Rn>{!}
+THUMB_INSTRUCTIONS gOpThumb2[] = {
+ // Instruct OpCode OpCode Mask Addressig Mode
+
+ { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW
+ { "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2 }, // CMN <Rn>, #<const> ;Needs to go before ADD
+ { "CMN", 0xeb100f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
+ { "CMP", 0xf1a00f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
+ { "TEQ", 0xf0900f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
+ { "TEQ", 0xea900f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
+ { "TST", 0xf0100f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
+ { "TST", 0xea100f00, 0xfff08f00, ADD_IMM5_2REG }, // TST <Rn>, <Rm> {,<shift> #<const>}
+
+ { "MOV", 0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV <Rd>, #<const>
+ { "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 }, // MOVW <Rd>, #<const>
+ { "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 }, // MOVT <Rd>, #<const>
+
+ { "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>
+ { "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>
+ { "ADD", 0xeb000000, 0xffe08000, ADD_IMM5 }, // ADD{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "ADDW", 0xf2000000, 0xfbe08000, ADD_IMM12 }, // ADDW{S} <Rd>, <Rn>, #<const>
+ { "AND", 0xf0000000, 0xfbe08000, ADD_IMM12 }, // AND{S} <Rd>, <Rn>, #<const>
+ { "AND", 0xea000000, 0xffe08000, ADD_IMM5 }, // AND{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "BIC", 0xf0200000, 0xfbe08000, ADD_IMM12 }, // BIC{S} <Rd>, <Rn>, #<const>
+ { "BIC", 0xea200000, 0xffe08000, ADD_IMM5 }, // BIC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "EOR", 0xf0800000, 0xfbe08000, ADD_IMM12 }, // EOR{S} <Rd>, <Rn>, #<const>
+ { "EOR", 0xea800000, 0xffe08000, ADD_IMM5 }, // EOR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "ORN", 0xf0600000, 0xfbe08000, ADD_IMM12 }, // ORN{S} <Rd>, <Rn>, #<const>
+ { "ORN", 0xea600000, 0xffe08000, ADD_IMM5 }, // ORN{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "ORR", 0xf0400000, 0xfbe08000, ADD_IMM12 }, // ORR{S} <Rd>, <Rn>, #<const>
+ { "ORR", 0xea400000, 0xffe08000, ADD_IMM5 }, // ORR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "RSB", 0xf1c00000, 0xfbe08000, ADD_IMM12 }, // RSB{S} <Rd>, <Rn>, #<const>
+ { "RSB", 0xebc00000, 0xffe08000, ADD_IMM5 }, // RSB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "SBC", 0xf1600000, 0xfbe08000, ADD_IMM12 }, // SBC{S} <Rd>, <Rn>, #<const>
+ { "SBC", 0xeb600000, 0xffe08000, ADD_IMM5 }, // SBC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "SUB", 0xf1a00000, 0xfbe08000, ADD_IMM12 }, // SUB{S} <Rd>, <Rn>, #<const>
+ { "SUB", 0xeba00000, 0xffe08000, ADD_IMM5 }, // SUB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+
+ { "ASR", 0xea4f0020, 0xffef8030, ASR_IMM5 }, // ARS <Rd>, <Rm> #<const>} imm3:imm2
+ { "ASR", 0xfa40f000, 0xffe0f0f0, ASR_3REG }, // ARS <Rd>, <Rn>, <Rm>
+ { "LSR", 0xea4f0010, 0xffef8030, ASR_IMM5 }, // LSR <Rd>, <Rm> #<const>} imm3:imm2
+ { "LSR", 0xfa20f000, 0xffe0f0f0, ASR_3REG }, // LSR <Rd>, <Rn>, <Rm>
+ { "ROR", 0xea4f0030, 0xffef8030, ASR_IMM5 }, // ROR <Rd>, <Rm> #<const>} imm3:imm2
+ { "ROR", 0xfa60f000, 0xffe0f0f0, ASR_3REG }, // ROR <Rd>, <Rn>, <Rm>
+
+ { "BFC", 0xf36f0000, 0xffff8010, BFC_THUMB2 }, // BFC <Rd>, #<lsb>, #<width>
+ { "BIC", 0xf3600000, 0xfff08010, BFC_THUMB2 }, // BIC <Rn>, <Rd>, #<lsb>, #<width>
+ { "SBFX", 0xf3400000, 0xfff08010, BFC_THUMB2 }, // SBFX <Rn>, <Rd>, #<lsb>, #<width>
+ { "UBFX", 0xf3c00000, 0xfff08010, BFC_THUMB2 }, // UBFX <Rn>, <Rd>, #<lsb>, #<width>
+
+ { "CPD", 0xee000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
+ { "CPD2", 0xfe000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
+
+ { "MRC", 0xee100000, 0xff100000, MRC_THUMB2 }, // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
+ { "MRC2", 0xfe100000, 0xff100000, MRC_THUMB2 }, // MRC2 <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
+ { "MRRC", 0xec500000, 0xfff00000, MRRC_THUMB2 }, // MRRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
+ { "MRRC2", 0xfc500000, 0xfff00000, MRRC_THUMB2 }, // MRR2 <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
+
+ { "MRS", 0xf3ef8000, 0xfffff0ff, THUMB2_MRS }, // MRS <Rd>, CPSR
+ { "MSR", 0xf3808000, 0xfff0fcff, THUMB2_MSR }, // MSR CPSR_fs, <Rn>
+
+ { "CLREX", 0xf3bf8f2f, 0xfffffff, THUMB2_NO_ARGS }, // CLREX
+
+ { "CLZ", 0xfab0f080, 0xfff0f0f0, THUMB2_2REGS }, // CLZ <Rd>,<Rm>
+ { "MOV", 0xec4f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOV <Rd>,<Rm>
+ { "MOVS", 0xec5f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOVS <Rd>,<Rm>
+ { "RBIT", 0xfb90f0a0, 0xfff0f0f0, THUMB2_2REGS }, // RBIT <Rd>,<Rm>
+ { "REV", 0xfb90f080, 0xfff0f0f0, THUMB2_2REGS }, // REV <Rd>,<Rm>
+ { "REV16", 0xfa90f090, 0xfff0f0f0, THUMB2_2REGS }, // REV16 <Rd>,<Rm>
+ { "REVSH", 0xfa90f0b0, 0xfff0f0f0, THUMB2_2REGS }, // REVSH <Rd>,<Rm>
+ { "RRX", 0xea4f0030, 0xfffff0f0, THUMB2_2REGS }, // RRX <Rd>,<Rm>
+ { "RRXS", 0xea5f0030, 0xfffff0f0, THUMB2_2REGS }, // RRXS <Rd>,<Rm>
+
+ { "MLA", 0xfb000000, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>
+ { "MLS", 0xfb000010, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>
+
+ { "SMLABB", 0xfb100000, 0xfff000f0, THUMB2_4REGS }, // SMLABB <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLABT", 0xfb100010, 0xfff000f0, THUMB2_4REGS }, // SMLABT <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLABB", 0xfb100020, 0xfff000f0, THUMB2_4REGS }, // SMLATB <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLATT", 0xfb100030, 0xfff000f0, THUMB2_4REGS }, // SMLATT <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLAWB", 0xfb300000, 0xfff000f0, THUMB2_4REGS }, // SMLAWB <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLAWT", 0xfb300010, 0xfff000f0, THUMB2_4REGS }, // SMLAWT <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLSD", 0xfb400000, 0xfff000f0, THUMB2_4REGS }, // SMLSD <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLSDX", 0xfb400010, 0xfff000f0, THUMB2_4REGS }, // SMLSDX <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMMLA", 0xfb500000, 0xfff000f0, THUMB2_4REGS }, // SMMLA <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMMLAR", 0xfb500010, 0xfff000f0, THUMB2_4REGS }, // SMMLAR <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMMLS", 0xfb600000, 0xfff000f0, THUMB2_4REGS }, // SMMLS <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMMLSR", 0xfb600010, 0xfff000f0, THUMB2_4REGS }, // SMMLSR <Rd>, <Rn>, <Rm>, <Ra>
+ { "USADA8", 0xfb700000, 0xfff000f0, THUMB2_4REGS }, // USADA8 <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLAD", 0xfb200000, 0xfff000f0, THUMB2_4REGS }, // SMLAD <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLADX", 0xfb200010, 0xfff000f0, THUMB2_4REGS }, // SMLADX <Rd>, <Rn>, <Rm>, <Ra>
+
+ { "B", 0xf0008000, 0xf800d000, B_T3 }, // B<c> <label>
+ { "B", 0xf0009000, 0xf800d000, B_T4 }, // B<c> <label>
+ { "BL", 0xf000d000, 0xf800d000, B_T4 }, // BL<c> <label>
+ { "BLX", 0xf000c000, 0xf800d000, BL_T2 }, // BLX<c> <label>
+
+ { "POP", 0xe8bd0000, 0xffff2000, POP_T2 }, // POP <registers>
+ { "POP", 0xf85d0b04, 0xffff0fff, POP_T3 }, // POP <register>
+ { "PUSH", 0xe8ad0000, 0xffffa000, POP_T2 }, // PUSH <registers>
+ { "PUSH", 0xf84d0d04, 0xffff0fff, POP_T3 }, // PUSH <register>
+ { "STM", 0xe8800000, 0xffd0a000, STM_FORMAT }, // STM <Rn>{!},<registers>
+ { "STMDB", 0xe9800000, 0xffd0a000, STM_FORMAT }, // STMDB <Rn>{!},<registers>
+ { "LDM", 0xe8900000, 0xffd02000, STM_FORMAT }, // LDM <Rn>{!},<registers>
+ { "LDMDB", 0xe9100000, 0xffd02000, STM_FORMAT }, // LDMDB <Rn>{!},<registers>
+
+ { "LDR", 0xf8d00000, 0xfff00000, LDM_REG_IMM12 }, // LDR <rt>, [<rn>, {, #<imm12>]}
+ { "LDRB", 0xf8900000, 0xfff00000, LDM_REG_IMM12 }, // LDRB <rt>, [<rn>, {, #<imm12>]}
+ { "LDRH", 0xf8b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRH <rt>, [<rn>, {, #<imm12>]}
+ { "LDRSB", 0xf9900000, 0xfff00000, LDM_REG_IMM12 }, // LDRSB <rt>, [<rn>, {, #<imm12>]}
+ { "LDRSH", 0xf9b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRSH <rt>, [<rn>, {, #<imm12>]}
+
+ { "LDR", 0xf85f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDR <Rt>, <label>
+ { "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label>
+ { "LDRH", 0xf83f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRH <Rt>, <label>
+ { "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
+ { "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
+
+ { "LDR", 0xf8500000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDR <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ { "LDRB", 0xf8100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ { "LDRH", 0xf8300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ { "LDRSB", 0xf9100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ { "LDRSH", 0xf9300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+
+ { "LDR", 0xf8500800, 0xfff00800, LDM_REG_IMM8 }, // LDR <rt>, [<rn>, {, #<imm8>]}
+ { "LDRBT", 0xf8100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRBT <rt>, [<rn>, {, #<imm8>]}
+ { "LDRHT", 0xf8300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]}
+ { "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form?
+ { "LDRSBT", 0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form?
+ { "LDRSH", 0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]}
+ { "LDRSHT", 0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]}
+ { "LDRT", 0xf8500e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRT <rt>, [<rn>, {, #<imm8>]}
+
+ { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
+ { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8 }, // LDRD <rt>, <rt2>, <label>
+
+ { "LDREX", 0xe8500f00, 0xfff00f00, LDM_REG_IMM8 }, // LDREX <Rt>, [Rn, {#imm8}]]
+ { "LDREXB", 0xe8d00f4f, 0xfff00fff, LDREXB }, // LDREXB <Rt>, [<Rn>]
+ { "LDREXH", 0xe8d00f5f, 0xfff00fff, LDREXB }, // LDREXH <Rt>, [<Rn>]
+
+ { "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>]
+
+ { "STR", 0xf8c00000, 0xfff00000, LDM_REG_IMM12 }, // STR <rt>, [<rn>, {, #<imm12>]}
+ { "STRB", 0xf8800000, 0xfff00000, LDM_REG_IMM12 }, // STRB <rt>, [<rn>, {, #<imm12>]}
+ { "STRH", 0xf8a00000, 0xfff00000, LDM_REG_IMM12 }, // STRH <rt>, [<rn>, {, #<imm12>]}
+
+ { "STR", 0xf8400000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STR <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ { "STRB", 0xf8000000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ { "STRH", 0xf8200000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+
+ { "STR", 0xf8400800, 0xfff00800, LDM_REG_IMM8 }, // STR <rt>, [<rn>, {, #<imm8>]}
+ { "STRH", 0xf8200800, 0xfff00800, LDM_REG_IMM8 }, // STRH <rt>, [<rn>, {, #<imm8>]}
+ { "STRBT", 0xf8000e00, 0xfff00f00, LDM_REG_IMM8 }, // STRBT <rt>, [<rn>, {, #<imm8>]}
+ { "STRHT", 0xf8200e00, 0xfff00f00, LDM_REG_IMM8 }, // STRHT <rt>, [<rn>, {, #<imm8>]}
+ { "STRT", 0xf8400e00, 0xfff00f00, LDM_REG_IMM8 }, // STRT <rt>, [<rn>, {, #<imm8>]}
+
+ { "STRD", 0xe8400000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // STRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
+
+ { "STREX", 0xe8400f00, 0xfff00f00, LDM_REG_IMM8 }, // STREX <Rt>, [Rn, {#imm8}]]
+ { "STREXB", 0xe8c00f4f, 0xfff00fff, LDREXB }, // STREXB <Rd>, <Rt>, [<Rn>]
+ { "STREXH", 0xe8c00f5f, 0xfff00fff, LDREXB }, // STREXH <Rd>, <Rt>, [<Rn>]
+
+ { "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>]
+
+ { "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>
+ { "SRS", 0xe98dc000, 0xffdffff0, SRS_FORMAT }, // SRS{IA}<c> SP{!},#<mode>
+ { "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT }, // RFEDB<c> <Rn>{!}
+ { "RFE", 0xe990c000, 0xffd0ffff, RFE_FORMAT } // RFE{IA}<c> <Rn>{!}
};
-CHAR8 *gShiftType[] = {
+CHAR8 *gShiftType[] = {
"LSL",
"LSR",
"ASR",
"ROR"
};
-CHAR8 mThumbMregListStr[4*15 + 1];
+CHAR8 mThumbMregListStr[4*15 + 1];
CHAR8 *
ThumbMRegList (
UINT32 RegBitMask
)
{
- UINTN Index, Start, End;
- BOOLEAN First;
+ UINTN Index, Start, End;
+ BOOLEAN First;
mThumbMregListStr[0] = '\0';
AsciiStrCatS (mThumbMregListStr, sizeof mThumbMregListStr, "{");
@@ -419,9 +413,11 @@ ThumbMRegList ( }
}
}
+
if (First) {
AsciiStrCatS (mThumbMregListStr, sizeof mThumbMregListStr, "ERROR");
}
+
AsciiStrCatS (mThumbMregListStr, sizeof mThumbMregListStr, "}");
// BugBug: Make caller pass in buffer it is cleaner
@@ -440,7 +436,7 @@ SignExtend32 ( do {
TopBit <<= 1;
- Data |= TopBit;
+ Data |= TopBit;
} while ((TopBit & BIT31) != BIT31);
return Data;
@@ -474,53 +470,54 @@ PcAlign4 ( **/
VOID
DisassembleThumbInstruction (
- IN UINT16 **OpCodePtrPtr,
- OUT CHAR8 *Buf,
- OUT UINTN Size,
- OUT UINT32 *ItBlock,
- IN BOOLEAN Extended
+ IN UINT16 **OpCodePtrPtr,
+ OUT CHAR8 *Buf,
+ OUT UINTN Size,
+ OUT UINT32 *ItBlock,
+ IN BOOLEAN Extended
)
{
- UINT16 *OpCodePtr;
- UINT16 OpCode;
- UINT32 OpCode32;
- UINT32 Index;
- UINT32 Offset;
- UINT16 Rd, Rn, Rm, Rt, Rt2;
- BOOLEAN H1Bit; // H1
- BOOLEAN H2Bit; // H2
- BOOLEAN IMod; // imod
- //BOOLEAN ItFlag;
- UINT32 Pc, Target, MsBit, LsBit;
- CHAR8 *Cond;
- BOOLEAN Sign; // S
- BOOLEAN J1Bit; // J1
- BOOLEAN J2Bit; // J2
- BOOLEAN Pre; // P
- BOOLEAN UAdd; // U
- BOOLEAN WriteBack; // W
- UINT32 Coproc, Opc1, Opc2, CRd, CRn, CRm;
- UINT32 Mask;
+ UINT16 *OpCodePtr;
+ UINT16 OpCode;
+ UINT32 OpCode32;
+ UINT32 Index;
+ UINT32 Offset;
+ UINT16 Rd, Rn, Rm, Rt, Rt2;
+ BOOLEAN H1Bit; // H1
+ BOOLEAN H2Bit; // H2
+ BOOLEAN IMod; // imod
+ // BOOLEAN ItFlag;
+ UINT32 Pc, Target, MsBit, LsBit;
+ CHAR8 *Cond;
+ BOOLEAN Sign; // S
+ BOOLEAN J1Bit; // J1
+ BOOLEAN J2Bit; // J2
+ BOOLEAN Pre; // P
+ BOOLEAN UAdd; // U
+ BOOLEAN WriteBack; // W
+ UINT32 Coproc, Opc1, Opc2, CRd, CRn, CRm;
+ UINT32 Mask;
OpCodePtr = *OpCodePtrPtr;
- OpCode = **OpCodePtrPtr;
+ OpCode = **OpCodePtrPtr;
// Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.
OpCode32 = (((UINT32)OpCode) << 16) | *(OpCodePtr + 1);
// These register names match branch form, but not others
- Rd = OpCode & 0x7;
- Rn = (OpCode >> 3) & 0x7;
- Rm = (OpCode >> 6) & 0x7;
+ Rd = OpCode & 0x7;
+ Rn = (OpCode >> 3) & 0x7;
+ Rm = (OpCode >> 6) & 0x7;
H1Bit = (OpCode & BIT7) != 0;
H2Bit = (OpCode & BIT6) != 0;
- IMod = (OpCode & BIT4) != 0;
- Pc = (UINT32)(UINTN)OpCodePtr;
+ IMod = (OpCode & BIT4) != 0;
+ Pc = (UINT32)(UINTN)OpCodePtr;
// Increment by the minimum instruction size, Thumb2 could be bigger
*OpCodePtrPtr += 1;
// Manage IT Block ItFlag TRUE means we are in an IT block
+
/*if (*ItBlock != 0) {
ItFlag = TRUE;
*ItBlock -= 1;
@@ -535,169 +532,169 @@ DisassembleThumbInstruction ( } else {
Offset = AsciiSPrint (Buf, Size, "%-6a", gOpThumb[Index].Start);
}
+
switch (gOpThumb[Index].AddressMode) {
- case LOAD_STORE_FORMAT1:
- // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);
- return;
- case LOAD_STORE_FORMAT1_H:
- // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e);
- return;
- case LOAD_STORE_FORMAT1_B:
- // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f);
- return;
-
- case LOAD_STORE_FORMAT2:
- // A6.5.1 <Rd>, [<Rn>, <Rm>]
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);
- return;
- case LOAD_STORE_FORMAT3:
- // A6.5.1 <Rd>, [PC, #<8_bit_offset>]
- Target = (OpCode & 0xff) << 2;
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);
- return;
- case LOAD_STORE_FORMAT4:
- // Rt, [SP, #imm8]
- Target = (OpCode & 0xff) << 2;
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target);
- return;
-
- case LOAD_STORE_MULTIPLE_FORMAT1:
- // <Rn>!, {r0-r7}
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));
- return;
-
- case POP_FORMAT:
- // POP {r0-r7,pc}
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));
- return;
-
- case PUSH_FORMAT:
- // PUSH {r0-r7,lr}
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));
- return;
-
-
- case IMMED_8:
- // A6.7 <immed_8>
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);
- return;
-
- case CONDITIONAL_BRANCH:
- // A6.3.1 B<cond> <target_address>
- // Patch in the condition code. A little hack but based on "%-6a"
- Cond = gCondition[(OpCode >> 8) & 0xf];
- Buf[Offset-5] = *Cond++;
- Buf[Offset-4] = *Cond;
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
- return;
- case UNCONDITIONAL_BRANCH_SHORT:
- // A6.3.2 B <target_address>
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
- return;
-
- case BRANCH_EXCHANGE:
- // A6.3.3 BX|BLX <Rm>
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8:0)]);
- return;
-
- case DATA_FORMAT1:
- // A6.4.3 <Rd>, <Rn>, <Rm>
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);
- return;
- case DATA_FORMAT2:
- // A6.4.3 <Rd>, <Rn>, #3_bit_immed
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);
- return;
- case DATA_FORMAT3:
- // A6.4.3 <Rd>|<Rn>, #imm8
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);
- return;
- case DATA_FORMAT4:
- // A6.4.3 <Rd>|<Rm>, #immed_5
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);
- return;
- case DATA_FORMAT5:
- // A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);
- return;
- case DATA_FORMAT6_SP:
- // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
- return;
- case DATA_FORMAT6_PC:
- // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
- return;
- case DATA_FORMAT7:
- // A6.4.3 SP, SP, #<7_Bit_immed>
- AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);
- return;
- case DATA_FORMAT8:
- // A6.4.3 <Rd>|<Rn>, <Rm>
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8:0)], gReg[Rn | (H2Bit ? 8:0)]);
- return;
-
- case CPS_FORMAT:
- // A7.1.24
- AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
- return;
-
- case ENDIAN_FORMAT:
- // A7.1.24
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");
- return;
-
- case DATA_CBZ:
- // CB{N}Z <Rn>, <Lable>
- Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);
- return;
-
- case ADR_FORMAT:
- // ADR <Rd>, <Label>
- Target = (OpCode & 0xff) << 2;
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);
- return;
-
- case IT_BLOCK:
- // ITSTATE = cond:mask OpCode[7:4]:OpCode[3:0]
- // ITSTATE[7:5] == cond[3:1]
- // ITSTATE[4] == 1st Instruction cond[0]
- // ITSTATE[3] == 2st Instruction cond[0]
- // ITSTATE[2] == 3st Instruction cond[0]
- // ITSTATE[1] == 4st Instruction cond[0]
- // ITSTATE[0] == 1 4 instruction IT block. 0 means 0,1,2 or 3 instructions
- // 1st one in ITSTATE low bits defines the number of instructions
- Mask = (OpCode & 0xf);
- if ((Mask & 0x1) == 0x1) {
- *ItBlock = 4;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a%a", (Mask & BIT3)?"T":"E", (Mask & BIT2)?"T":"E", (Mask & BIT1)?"T":"E");
- } else if ((OpCode & 0x3) == 0x2) {
- *ItBlock = 3;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a", (Mask & BIT3)?"T":"E", (Mask & BIT2)?"T":"E");
- } else if ((OpCode & 0x7) == 0x4) {
- *ItBlock = 2;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a", (Mask & BIT3)?"T":"E");
- } else if ((OpCode & 0xf) == 0x8) {
- *ItBlock = 1;
- }
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]);
- return;
+ case LOAD_STORE_FORMAT1:
+ // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);
+ return;
+ case LOAD_STORE_FORMAT1_H:
+ // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e);
+ return;
+ case LOAD_STORE_FORMAT1_B:
+ // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f);
+ return;
+
+ case LOAD_STORE_FORMAT2:
+ // A6.5.1 <Rd>, [<Rn>, <Rm>]
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);
+ return;
+ case LOAD_STORE_FORMAT3:
+ // A6.5.1 <Rd>, [PC, #<8_bit_offset>]
+ Target = (OpCode & 0xff) << 2;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);
+ return;
+ case LOAD_STORE_FORMAT4:
+ // Rt, [SP, #imm8]
+ Target = (OpCode & 0xff) << 2;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target);
+ return;
+
+ case LOAD_STORE_MULTIPLE_FORMAT1:
+ // <Rn>!, {r0-r7}
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));
+ return;
+
+ case POP_FORMAT:
+ // POP {r0-r7,pc}
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));
+ return;
+
+ case PUSH_FORMAT:
+ // PUSH {r0-r7,lr}
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));
+ return;
+
+ case IMMED_8:
+ // A6.7 <immed_8>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);
+ return;
+
+ case CONDITIONAL_BRANCH:
+ // A6.3.1 B<cond> <target_address>
+ // Patch in the condition code. A little hack but based on "%-6a"
+ Cond = gCondition[(OpCode >> 8) & 0xf];
+ Buf[Offset-5] = *Cond++;
+ Buf[Offset-4] = *Cond;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
+ return;
+ case UNCONDITIONAL_BRANCH_SHORT:
+ // A6.3.2 B <target_address>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
+ return;
+
+ case BRANCH_EXCHANGE:
+ // A6.3.3 BX|BLX <Rm>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8 : 0)]);
+ return;
+
+ case DATA_FORMAT1:
+ // A6.4.3 <Rd>, <Rn>, <Rm>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);
+ return;
+ case DATA_FORMAT2:
+ // A6.4.3 <Rd>, <Rn>, #3_bit_immed
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);
+ return;
+ case DATA_FORMAT3:
+ // A6.4.3 <Rd>|<Rn>, #imm8
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);
+ return;
+ case DATA_FORMAT4:
+ // A6.4.3 <Rd>|<Rm>, #immed_5
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);
+ return;
+ case DATA_FORMAT5:
+ // A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);
+ return;
+ case DATA_FORMAT6_SP:
+ // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
+ return;
+ case DATA_FORMAT6_PC:
+ // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
+ return;
+ case DATA_FORMAT7:
+ // A6.4.3 SP, SP, #<7_Bit_immed>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);
+ return;
+ case DATA_FORMAT8:
+ // A6.4.3 <Rd>|<Rn>, <Rm>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8 : 0)], gReg[Rn | (H2Bit ? 8 : 0)]);
+ return;
+
+ case CPS_FORMAT:
+ // A7.1.24
+ AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID" : "IE", ((OpCode & BIT2) == 0) ? "" : "a", ((OpCode & BIT1) == 0) ? "" : "i", ((OpCode & BIT0) == 0) ? "" : "f");
+ return;
+
+ case ENDIAN_FORMAT:
+ // A7.1.24
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE" : "BE");
+ return;
+
+ case DATA_CBZ:
+ // CB{N}Z <Rn>, <Lable>
+ Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);
+ return;
+
+ case ADR_FORMAT:
+ // ADR <Rd>, <Label>
+ Target = (OpCode & 0xff) << 2;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);
+ return;
+
+ case IT_BLOCK:
+ // ITSTATE = cond:mask OpCode[7:4]:OpCode[3:0]
+ // ITSTATE[7:5] == cond[3:1]
+ // ITSTATE[4] == 1st Instruction cond[0]
+ // ITSTATE[3] == 2st Instruction cond[0]
+ // ITSTATE[2] == 3st Instruction cond[0]
+ // ITSTATE[1] == 4st Instruction cond[0]
+ // ITSTATE[0] == 1 4 instruction IT block. 0 means 0,1,2 or 3 instructions
+ // 1st one in ITSTATE low bits defines the number of instructions
+ Mask = (OpCode & 0xf);
+ if ((Mask & 0x1) == 0x1) {
+ *ItBlock = 4;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a%a", (Mask & BIT3) ? "T" : "E", (Mask & BIT2) ? "T" : "E", (Mask & BIT1) ? "T" : "E");
+ } else if ((OpCode & 0x3) == 0x2) {
+ *ItBlock = 3;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a", (Mask & BIT3) ? "T" : "E", (Mask & BIT2) ? "T" : "E");
+ } else if ((OpCode & 0x7) == 0x4) {
+ *ItBlock = 2;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a", (Mask & BIT3) ? "T" : "E");
+ } else if ((OpCode & 0xf) == 0x8) {
+ *ItBlock = 1;
+ }
+
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]);
+ return;
}
}
}
-
// Thumb2 are 32-bit instructions
*OpCodePtrPtr += 1;
- Rt = (OpCode32 >> 12) & 0xf;
- Rt2 = (OpCode32 >> 8) & 0xf;
- Rd = (OpCode32 >> 8) & 0xf;
- Rm = (OpCode32 & 0xf);
- Rn = (OpCode32 >> 16) & 0xf;
+ Rt = (OpCode32 >> 12) & 0xf;
+ Rt2 = (OpCode32 >> 8) & 0xf;
+ Rd = (OpCode32 >> 8) & 0xf;
+ Rm = (OpCode32 & 0xf);
+ Rn = (OpCode32 >> 16) & 0xf;
for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {
if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {
if (Extended) {
@@ -705,313 +702,329 @@ DisassembleThumbInstruction ( } else {
Offset = AsciiSPrint (Buf, Size, " %-6a", gOpThumb2[Index].Start);
}
+
switch (gOpThumb2[Index].AddressMode) {
- case B_T3:
- Cond = gCondition[(OpCode32 >> 22) & 0xf];
- Buf[Offset-5] = *Cond++;
- Buf[Offset-4] = *Cond;
- // S:J2:J1:imm6:imm11:0
- Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3f000);
- Target |= ((OpCode32 & BIT11) == BIT11)? BIT19 : 0; // J2
- Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1
- Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S
- Target = SignExtend32 (Target, BIT20);
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
- return;
- case B_T4:
- // S:I1:I2:imm10:imm11:0
- Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);
- Sign = (OpCode32 & BIT26) == BIT26;
- J1Bit = (OpCode32 & BIT13) == BIT13;
- J2Bit = (OpCode32 & BIT11) == BIT11;
- Target |= (!(J2Bit ^ Sign) ? BIT22 : 0); // I2
- Target |= (!(J1Bit ^ Sign) ? BIT23 : 0); // I1
- Target |= (Sign ? BIT24 : 0); // S
- Target = SignExtend32 (Target, BIT24);
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
- return;
-
- case BL_T2:
- // BLX S:I1:I2:imm10:imm11:0
- Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);
- Sign = (OpCode32 & BIT26) == BIT26;
- J1Bit = (OpCode32 & BIT13) == BIT13;
- J2Bit = (OpCode32 & BIT11) == BIT11;
- Target |= (!(J2Bit ^ Sign) ? BIT23 : 0); // I2
- Target |= (!(J1Bit ^ Sign) ? BIT24 : 0); // I1
- Target |= (Sign ? BIT25 : 0); // S
- Target = SignExtend32 (Target, BIT25);
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);
- return;
-
- case POP_T2:
- // <reglist> some must be zero, handled in table
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList (OpCode32 & 0xffff));
- return;
-
- case POP_T3:
- // <register>
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[(OpCode32 >> 12) & 0xf]);
- return;
-
- case STM_FORMAT:
- // <Rn>{!}, <registers>
- WriteBack = (OpCode32 & BIT21) == BIT21;
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
- return;
-
- case LDM_REG_IMM12_SIGNED:
- // <rt>, <label>
- Target = OpCode32 & 0xfff;
- if ((OpCode32 & BIT23) == 0) {
- // U == 0 means subtrack, U == 1 means add
- Target = -Target;
- }
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);
- return;
-
- case LDM_REG_INDIRECT_LSL:
- // <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a, %a", gReg[Rt], gReg[Rn], gReg[Rm]);
- if (((OpCode32 >> 4) & 3) == 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, "]");
- } else {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL #%d]", (OpCode32 >> 4) & 3);
- }
- return;
-
- case LDM_REG_IMM12:
- // <rt>, [<rn>, {, #<imm12>]}
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
- if ((OpCode32 & 0xfff) == 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, "]");
- } else {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #0x%x]", OpCode32 & 0xfff);
- }
- return;
-
- case LDM_REG_IMM8:
- // <rt>, [<rn>, {, #<imm8>}]{!}
- WriteBack = (OpCode32 & BIT8) == BIT8;
- UAdd = (OpCode32 & BIT9) == BIT9;
- Pre = (OpCode32 & BIT10) == BIT10;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
- if (Pre) {
- if ((OpCode32 & 0xff) == 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack?"!":"");
+ case B_T3:
+ Cond = gCondition[(OpCode32 >> 22) & 0xf];
+ Buf[Offset-5] = *Cond++;
+ Buf[Offset-4] = *Cond;
+ // S:J2:J1:imm6:imm11:0
+ Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3f000);
+ Target |= ((OpCode32 & BIT11) == BIT11) ? BIT19 : 0; // J2
+ Target |= ((OpCode32 & BIT13) == BIT13) ? BIT18 : 0; // J1
+ Target |= ((OpCode32 & BIT26) == BIT26) ? BIT20 : 0; // S
+ Target = SignExtend32 (Target, BIT20);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
+ return;
+ case B_T4:
+ // S:I1:I2:imm10:imm11:0
+ Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);
+ Sign = (OpCode32 & BIT26) == BIT26;
+ J1Bit = (OpCode32 & BIT13) == BIT13;
+ J2Bit = (OpCode32 & BIT11) == BIT11;
+ Target |= (!(J2Bit ^ Sign) ? BIT22 : 0); // I2
+ Target |= (!(J1Bit ^ Sign) ? BIT23 : 0); // I1
+ Target |= (Sign ? BIT24 : 0); // S
+ Target = SignExtend32 (Target, BIT24);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
+ return;
+
+ case BL_T2:
+ // BLX S:I1:I2:imm10:imm11:0
+ Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);
+ Sign = (OpCode32 & BIT26) == BIT26;
+ J1Bit = (OpCode32 & BIT13) == BIT13;
+ J2Bit = (OpCode32 & BIT11) == BIT11;
+ Target |= (!(J2Bit ^ Sign) ? BIT23 : 0); // I2
+ Target |= (!(J1Bit ^ Sign) ? BIT24 : 0); // I1
+ Target |= (Sign ? BIT25 : 0); // S
+ Target = SignExtend32 (Target, BIT25);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);
+ return;
+
+ case POP_T2:
+ // <reglist> some must be zero, handled in table
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList (OpCode32 & 0xffff));
+ return;
+
+ case POP_T3:
+ // <register>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[(OpCode32 >> 12) & 0xf]);
+ return;
+
+ case STM_FORMAT:
+ // <Rn>{!}, <registers>
+ WriteBack = (OpCode32 & BIT21) == BIT21;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!" : "", ThumbMRegList (OpCode32 & 0xffff));
+ return;
+
+ case LDM_REG_IMM12_SIGNED:
+ // <rt>, <label>
+ Target = OpCode32 & 0xfff;
+ if ((OpCode32 & BIT23) == 0) {
+ // U == 0 means subtrack, U == 1 means add
+ Target = -Target;
+ }
+
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);
+ return;
+
+ case LDM_REG_INDIRECT_LSL:
+ // <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a, %a", gReg[Rt], gReg[Rn], gReg[Rm]);
+ if (((OpCode32 >> 4) & 3) == 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]");
} else {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-" , OpCode32 & 0xff, WriteBack?"!":"");
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL #%d]", (OpCode32 >> 4) & 3);
}
- } else {
- AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd?"":"-", OpCode32 & 0xff);
- }
- return;
-
- case LDRD_REG_IMM8_SIGNED:
- // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
- Pre = (OpCode32 & BIT24) == BIT24; // index = P
- UAdd = (OpCode32 & BIT23) == BIT23;
- WriteBack = (OpCode32 & BIT21) == BIT21;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);
- if (Pre) {
- if ((OpCode32 & 0xff) == 0) {
+
+ return;
+
+ case LDM_REG_IMM12:
+ // <rt>, [<rn>, {, #<imm12>]}
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
+ if ((OpCode32 & 0xfff) == 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, "]");
} else {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-", (OpCode32 & 0xff) << 2, WriteBack?"!":"");
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #0x%x]", OpCode32 & 0xfff);
+ }
+
+ return;
+
+ case LDM_REG_IMM8:
+ // <rt>, [<rn>, {, #<imm8>}]{!}
+ WriteBack = (OpCode32 & BIT8) == BIT8;
+ UAdd = (OpCode32 & BIT9) == BIT9;
+ Pre = (OpCode32 & BIT10) == BIT10;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
+ if (Pre) {
+ if ((OpCode32 & 0xff) == 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack ? "!" : "");
+ } else {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd ? "" : "-", OpCode32 & 0xff, WriteBack ? "!" : "");
+ }
+ } else {
+ AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd ? "" : "-", OpCode32 & 0xff);
}
- } else {
- if ((OpCode32 & 0xff) != 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd?"":"-", (OpCode32 & 0xff) << 2);
+
+ return;
+
+ case LDRD_REG_IMM8_SIGNED:
+ // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
+ Pre = (OpCode32 & BIT24) == BIT24; // index = P
+ UAdd = (OpCode32 & BIT23) == BIT23;
+ WriteBack = (OpCode32 & BIT21) == BIT21;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);
+ if (Pre) {
+ if ((OpCode32 & 0xff) == 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]");
+ } else {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd ? "" : "-", (OpCode32 & 0xff) << 2, WriteBack ? "!" : "");
+ }
+ } else {
+ if ((OpCode32 & 0xff) != 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd ? "" : "-", (OpCode32 & 0xff) << 2);
+ }
}
- }
- return;
-
- case LDRD_REG_IMM8:
- // LDRD <rt>, <rt2>, <label>
- Target = (OpCode32 & 0xff) << 2;
- if ((OpCode32 & BIT23) == 0) {
- // U == 0 means subtrack, U == 1 means add
- Target = -Target;
- }
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);
- return;
-
- case LDREXB:
- // LDREXB <Rt>, [Rn]
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a]", gReg[Rt], gReg[Rn]);
- return;
-
- case LDREXD:
- // LDREXD <Rt>, <Rt2>, [<Rn>]
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, [%a]", gReg[Rt], gReg[Rt2], gReg[Rn]);
- return;
-
- case SRS_FORMAT:
- // SP{!}, #<mode>
- WriteBack = (OpCode32 & BIT21) == BIT21;
- AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack?"!":"", OpCode32 & 0x1f);
- return;
-
- case RFE_FORMAT:
- // <Rn>{!}
- WriteBack = (OpCode32 & BIT21) == BIT21;
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack?"!":"");
- return;
-
- case ADD_IMM12:
- // ADD{S} <Rd>, <Rn>, #<const> i:imm3:imm8
- if ((OpCode32 & BIT20) == BIT20) {
- Buf[Offset - 3] = 'S'; // assume %-6a
- }
- Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target);
- return;
-
- case ADD_IMM12_1REG:
- // MOV{S} <Rd>, #<const> i:imm3:imm8
- if ((OpCode32 & BIT20) == BIT20) {
- Buf[Offset - 3] = 'S'; // assume %-6a
- }
- Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
- return;
-
- case THUMB2_IMM16:
- // MOVW <Rd>, #<const> i:imm3:imm8
- Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
- Target |= ((OpCode32 >> 4) & 0xf0000);
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
- return;
-
- case ADD_IMM5:
- // ADC{S} <Rd>, <Rn>, <Rm> {,LSL #<const>} imm3:imm2
- if ((OpCode32 & BIT20) == BIT20) {
- Buf[Offset - 3] = 'S'; // assume %-6a
- }
- Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm]);
- if (Target != 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
- }
- return;
-
- case ADD_IMM5_2REG:
- // CMP <Rn>, <Rm> {,LSL #<const>} imm3:imm2
- Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rn], gReg[Rm]);
- if (Target != 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
- }
-
-
- case ASR_IMM5:
- // ARS <Rd>, <Rm> #<const>} imm3:imm2
- if ((OpCode32 & BIT20) == BIT20) {
- Buf[Offset - 3] = 'S'; // assume %-6a
- }
- Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a #%d", gReg[Rd], gReg[Rm], Target);
- return;
-
- case ASR_3REG:
- // ARS <Rd>, <Rn>, <Rm>
- if ((OpCode32 & BIT20) == BIT20) {
- Buf[Offset - 3] = 'S'; // assume %-6a
- }
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a %a", gReg[Rd], gReg[Rn], gReg[Rm]);
- return;
-
- case ADR_THUMB2:
- // ADDR <Rd>, <label>
- Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
- if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {
- Target = PcAlign4 (Pc) - Target;
- } else {
- Target = PcAlign4 (Pc) + Target;
- }
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
- return;
-
- case CMN_THUMB2:
- // CMN <Rn>, #<const>}
- Target = (OpCode32 & 0xff) | ((OpCode >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rn], Target);
- return;
-
- case BFC_THUMB2:
- // BFI <Rd>, <Rn>, #<lsb>, #<width>
- MsBit = OpCode32 & 0x1f;
- LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
- if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){
- // BFC <Rd>, #<lsb>, #<width>
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);
- } else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);
- } else {
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);
- }
- return;
-
- case CPD_THUMB2:
- // <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
- Coproc = (OpCode32 >> 8) & 0xf;
- Opc1 = (OpCode32 >> 20) & 0xf;
- Opc2 = (OpCode32 >> 5) & 0x7;
- CRd = (OpCode32 >> 12) & 0xf;
- CRn = (OpCode32 >> 16) & 0xf;
- CRm = OpCode32 & 0xf;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);
- if (Opc2 != 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
- }
- return;
-
- case MRC_THUMB2:
- // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
- Coproc = (OpCode32 >> 8) & 0xf;
- Opc1 = (OpCode32 >> 20) & 0xf;
- Opc2 = (OpCode32 >> 5) & 0x7;
- CRn = (OpCode32 >> 16) & 0xf;
- CRm = OpCode32 & 0xf;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);
- if (Opc2 != 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
- }
- return;
-
- case MRRC_THUMB2:
- // MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
- Coproc = (OpCode32 >> 8) & 0xf;
- Opc1 = (OpCode32 >> 20) & 0xf;
- CRn = (OpCode32 >> 16) & 0xf;
- CRm = OpCode32 & 0xf;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);
- return;
-
- case THUMB2_2REGS:
- // <Rd>, <Rm>
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd], gReg[Rm]);
- return;
-
- case THUMB2_4REGS:
- // <Rd>, <Rn>, <Rm>, <Ra>
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm], gReg[Rt]);
- return;
-
- case THUMB2_MRS:
- // MRS <Rd>, CPSR
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, CPSR", gReg[Rd]);
- return;
-
- case THUMB2_MSR:
- // MRS CPSR_<fields>, <Rd>
- Target = (OpCode32 >> 10) & 3;
- AsciiSPrint (&Buf[Offset], Size - Offset, " CPSR_%a%a, %a", (Target & 2) == 0 ? "":"f", (Target & 1) == 0 ? "":"s", gReg[Rd]);
- return;
-
- case THUMB2_NO_ARGS:
- default:
- break;
+
+ return;
+
+ case LDRD_REG_IMM8:
+ // LDRD <rt>, <rt2>, <label>
+ Target = (OpCode32 & 0xff) << 2;
+ if ((OpCode32 & BIT23) == 0) {
+ // U == 0 means subtrack, U == 1 means add
+ Target = -Target;
+ }
+
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);
+ return;
+
+ case LDREXB:
+ // LDREXB <Rt>, [Rn]
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a]", gReg[Rt], gReg[Rn]);
+ return;
+
+ case LDREXD:
+ // LDREXD <Rt>, <Rt2>, [<Rn>]
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, [%a]", gReg[Rt], gReg[Rt2], gReg[Rn]);
+ return;
+
+ case SRS_FORMAT:
+ // SP{!}, #<mode>
+ WriteBack = (OpCode32 & BIT21) == BIT21;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack ? "!" : "", OpCode32 & 0x1f);
+ return;
+
+ case RFE_FORMAT:
+ // <Rn>{!}
+ WriteBack = (OpCode32 & BIT21) == BIT21;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack ? "!" : "");
+ return;
+
+ case ADD_IMM12:
+ // ADD{S} <Rd>, <Rn>, #<const> i:imm3:imm8
+ if ((OpCode32 & BIT20) == BIT20) {
+ Buf[Offset - 3] = 'S'; // assume %-6a
+ }
+
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target);
+ return;
+
+ case ADD_IMM12_1REG:
+ // MOV{S} <Rd>, #<const> i:imm3:imm8
+ if ((OpCode32 & BIT20) == BIT20) {
+ Buf[Offset - 3] = 'S'; // assume %-6a
+ }
+
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
+ return;
+
+ case THUMB2_IMM16:
+ // MOVW <Rd>, #<const> i:imm3:imm8
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
+ Target |= ((OpCode32 >> 4) & 0xf0000);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
+ return;
+
+ case ADD_IMM5:
+ // ADC{S} <Rd>, <Rn>, <Rm> {,LSL #<const>} imm3:imm2
+ if ((OpCode32 & BIT20) == BIT20) {
+ Buf[Offset - 3] = 'S'; // assume %-6a
+ }
+
+ Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm]);
+ if (Target != 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
+ }
+
+ return;
+
+ case ADD_IMM5_2REG:
+ // CMP <Rn>, <Rm> {,LSL #<const>} imm3:imm2
+ Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rn], gReg[Rm]);
+ if (Target != 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
+ }
+
+ case ASR_IMM5:
+ // ARS <Rd>, <Rm> #<const>} imm3:imm2
+ if ((OpCode32 & BIT20) == BIT20) {
+ Buf[Offset - 3] = 'S'; // assume %-6a
+ }
+
+ Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a #%d", gReg[Rd], gReg[Rm], Target);
+ return;
+
+ case ASR_3REG:
+ // ARS <Rd>, <Rn>, <Rm>
+ if ((OpCode32 & BIT20) == BIT20) {
+ Buf[Offset - 3] = 'S'; // assume %-6a
+ }
+
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a %a", gReg[Rd], gReg[Rn], gReg[Rm]);
+ return;
+
+ case ADR_THUMB2:
+ // ADDR <Rd>, <label>
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
+ if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {
+ Target = PcAlign4 (Pc) - Target;
+ } else {
+ Target = PcAlign4 (Pc) + Target;
+ }
+
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
+ return;
+
+ case CMN_THUMB2:
+ // CMN <Rn>, #<const>}
+ Target = (OpCode32 & 0xff) | ((OpCode >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rn], Target);
+ return;
+
+ case BFC_THUMB2:
+ // BFI <Rd>, <Rn>, #<lsb>, #<width>
+ MsBit = OpCode32 & 0x1f;
+ LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
+ if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)) {
+ // BFC <Rd>, #<lsb>, #<width>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);
+ } else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);
+ } else {
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);
+ }
+
+ return;
+
+ case CPD_THUMB2:
+ // <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
+ Coproc = (OpCode32 >> 8) & 0xf;
+ Opc1 = (OpCode32 >> 20) & 0xf;
+ Opc2 = (OpCode32 >> 5) & 0x7;
+ CRd = (OpCode32 >> 12) & 0xf;
+ CRn = (OpCode32 >> 16) & 0xf;
+ CRm = OpCode32 & 0xf;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);
+ if (Opc2 != 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
+ }
+
+ return;
+
+ case MRC_THUMB2:
+ // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
+ Coproc = (OpCode32 >> 8) & 0xf;
+ Opc1 = (OpCode32 >> 20) & 0xf;
+ Opc2 = (OpCode32 >> 5) & 0x7;
+ CRn = (OpCode32 >> 16) & 0xf;
+ CRm = OpCode32 & 0xf;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);
+ if (Opc2 != 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
+ }
+
+ return;
+
+ case MRRC_THUMB2:
+ // MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
+ Coproc = (OpCode32 >> 8) & 0xf;
+ Opc1 = (OpCode32 >> 20) & 0xf;
+ CRn = (OpCode32 >> 16) & 0xf;
+ CRm = OpCode32 & 0xf;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);
+ return;
+
+ case THUMB2_2REGS:
+ // <Rd>, <Rm>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd], gReg[Rm]);
+ return;
+
+ case THUMB2_4REGS:
+ // <Rd>, <Rn>, <Rm>, <Ra>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm], gReg[Rt]);
+ return;
+
+ case THUMB2_MRS:
+ // MRS <Rd>, CPSR
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, CPSR", gReg[Rd]);
+ return;
+
+ case THUMB2_MSR:
+ // MRS CPSR_<fields>, <Rd>
+ Target = (OpCode32 >> 10) & 3;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " CPSR_%a%a, %a", (Target & 2) == 0 ? "" : "f", (Target & 1) == 0 ? "" : "s", gReg[Rd]);
+ return;
+
+ case THUMB2_NO_ARGS:
+ default:
+ break;
}
}
}
@@ -1019,17 +1032,14 @@ DisassembleThumbInstruction ( AsciiSPrint (Buf, Size, "0x%08x", OpCode32);
}
-
-
VOID
DisassembleArmInstruction (
- IN UINT32 **OpCodePtr,
- OUT CHAR8 *Buf,
- OUT UINTN Size,
- IN BOOLEAN Extended
+ IN UINT32 **OpCodePtr,
+ OUT CHAR8 *Buf,
+ OUT UINTN Size,
+ IN BOOLEAN Extended
);
-
/**
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
point to next instruction.
@@ -1047,12 +1057,12 @@ DisassembleArmInstruction ( **/
VOID
DisassembleInstruction (
- IN UINT8 **OpCodePtr,
- IN BOOLEAN Thumb,
- IN BOOLEAN Extended,
- IN OUT UINT32 *ItBlock,
- OUT CHAR8 *Buf,
- OUT UINTN Size
+ IN UINT8 **OpCodePtr,
+ IN BOOLEAN Thumb,
+ IN BOOLEAN Extended,
+ IN OUT UINT32 *ItBlock,
+ OUT CHAR8 *Buf,
+ OUT UINTN Size
)
{
if (Thumb) {
@@ -1061,4 +1071,3 @@ DisassembleInstruction ( DisassembleArmInstruction ((UINT32 **)OpCodePtr, Buf, Size, Extended);
}
}
-
diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c b/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c index fcf3dd1644..ef6a132b8d 100644 --- a/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c +++ b/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c @@ -14,39 +14,39 @@ #include <Library/MemoryAllocationLib.h>
#include <Protocol/DebugSupport.h> // for MAX_AARCH64_EXCEPTION
-UINTN gMaxExceptionNumber = MAX_AARCH64_EXCEPTION;
-EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };
+UINTN gMaxExceptionNumber = MAX_AARCH64_EXCEPTION;
+EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };
EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };
-PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
-UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64
+PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
+UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64
#define EL0_STACK_SIZE EFI_PAGES_TO_SIZE(2)
-STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)];
+STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)];
VOID
RegisterEl0Stack (
- IN VOID *Stack
+ IN VOID *Stack
);
RETURN_STATUS
ArchVectorConfig (
- IN UINTN VectorBaseAddress
+ IN UINTN VectorBaseAddress
)
{
- UINTN HcrReg;
+ UINTN HcrReg;
// Round down sp by 16 bytes alignment
RegisterEl0Stack (
(VOID *)(((UINTN)mNewStackBase + EL0_STACK_SIZE) & ~0xFUL)
);
- if (ArmReadCurrentEL() == AARCH64_EL2) {
- HcrReg = ArmReadHcr();
+ if (ArmReadCurrentEL () == AARCH64_EL2) {
+ HcrReg = ArmReadHcr ();
// Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2
HcrReg |= ARM_HCR_TGE;
- ArmWriteHcr(HcrReg);
+ ArmWriteHcr (HcrReg);
}
return RETURN_SUCCESS;
diff --git a/ArmPkg/Library/ArmExceptionLib/Arm/ArmException.c b/ArmPkg/Library/ArmExceptionLib/Arm/ArmException.c index 40857c7f1f..fc411b845d 100644 --- a/ArmPkg/Library/ArmExceptionLib/Arm/ArmException.c +++ b/ArmPkg/Library/ArmExceptionLib/Arm/ArmException.c @@ -17,28 +17,27 @@ #include <Protocol/DebugSupport.h> // for MAX_ARM_EXCEPTION
-UINTN gMaxExceptionNumber = MAX_ARM_EXCEPTION;
-EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };
+UINTN gMaxExceptionNumber = MAX_ARM_EXCEPTION;
+EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };
EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };
-PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
+PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
// Exception handler contains branch to vector location (jmp $) so no handler
// NOTE: This code assumes vectors are ARM and not Thumb code
-UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE;
+UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE;
RETURN_STATUS
ArchVectorConfig (
- IN UINTN VectorBaseAddress
+ IN UINTN VectorBaseAddress
)
{
// if the vector address corresponds to high vectors
if (VectorBaseAddress == 0xFFFF0000) {
// set SCTLR.V to enable high vectors
- ArmSetHighVectors();
- }
- else {
+ ArmSetHighVectors ();
+ } else {
// Set SCTLR.V to 0 to enable VBAR to be used
- ArmSetLowVectors();
+ ArmSetLowVectors ();
}
return RETURN_SUCCESS;
diff --git a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c index 245e848e3f..1904816c16 100644 --- a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c +++ b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c @@ -22,37 +22,38 @@ STATIC
RETURN_STATUS
-CopyExceptionHandlers(
- IN PHYSICAL_ADDRESS BaseAddress
+CopyExceptionHandlers (
+ IN PHYSICAL_ADDRESS BaseAddress
);
EFI_STATUS
EFIAPI
-RegisterExceptionHandler(
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+RegisterExceptionHandler (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
VOID
-ExceptionHandlersStart(
+ExceptionHandlersStart (
VOID
);
VOID
-ExceptionHandlersEnd(
+ExceptionHandlersEnd (
VOID
);
-RETURN_STATUS ArchVectorConfig(
- IN UINTN VectorBaseAddress
+RETURN_STATUS
+ArchVectorConfig (
+ IN UINTN VectorBaseAddress
);
// these globals are provided by the architecture specific source (Arm or AArch64)
-extern UINTN gMaxExceptionNumber;
-extern EFI_EXCEPTION_CALLBACK gExceptionHandlers[];
-extern EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[];
-extern PHYSICAL_ADDRESS gExceptionVectorAlignmentMask;
-extern UINTN gDebuggerNoHandlerValue;
+extern UINTN gMaxExceptionNumber;
+extern EFI_EXCEPTION_CALLBACK gExceptionHandlers[];
+extern EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[];
+extern PHYSICAL_ADDRESS gExceptionVectorAlignmentMask;
+extern UINTN gDebuggerNoHandlerValue;
// A compiler flag adjusts the compilation of this library to a variant where
// the vectors are relocated (copied) to another location versus using the
@@ -60,13 +61,12 @@ extern UINTN gDebuggerNoHandlerValue; // address this at library build time. Since this affects the build of the
// library we cannot represent this in a PCD since PCDs are evaluated on
// a per-module basis.
-#if defined(ARM_RELOCATE_VECTORS)
-STATIC CONST BOOLEAN gArmRelocateVectorTable = TRUE;
+#if defined (ARM_RELOCATE_VECTORS)
+STATIC CONST BOOLEAN gArmRelocateVectorTable = TRUE;
#else
-STATIC CONST BOOLEAN gArmRelocateVectorTable = FALSE;
+STATIC CONST BOOLEAN gArmRelocateVectorTable = FALSE;
#endif
-
/**
Initializes all CPU exceptions entries and provides the default exception handlers.
@@ -85,23 +85,21 @@ with default exception handlers. **/
EFI_STATUS
EFIAPI
-InitializeCpuExceptionHandlers(
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+InitializeCpuExceptionHandlers (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
- RETURN_STATUS Status;
- UINTN VectorBase;
+ RETURN_STATUS Status;
+ UINTN VectorBase;
Status = EFI_SUCCESS;
// if we are requested to copy exception handlers to another location
if (gArmRelocateVectorTable) {
-
- VectorBase = PcdGet64(PcdCpuVectorBaseAddress);
- Status = CopyExceptionHandlers(VectorBase);
-
- }
- else { // use VBAR to point to where our exception handlers are
+ VectorBase = PcdGet64 (PcdCpuVectorBaseAddress);
+ Status = CopyExceptionHandlers (VectorBase);
+ } else {
+ // use VBAR to point to where our exception handlers are
// The vector table must be aligned for the architecture. If this
// assertion fails ensure the appropriate FFS alignment is in effect,
@@ -110,7 +108,7 @@ InitializeCpuExceptionHandlers( // for AArch64 Align=4K is required. Align=Auto can be used but this
// is known to cause an issue with populating the reset vector area
// for encapsulated FVs.
- ASSERT(((UINTN)ExceptionHandlersStart & gExceptionVectorAlignmentMask) == 0);
+ ASSERT (((UINTN)ExceptionHandlersStart & gExceptionVectorAlignmentMask) == 0);
// We do not copy the Exception Table at PcdGet64(PcdCpuVectorBaseAddress). We just set Vector
// Base Address to point into CpuDxe code.
@@ -119,12 +117,12 @@ InitializeCpuExceptionHandlers( Status = RETURN_SUCCESS;
}
- if (!RETURN_ERROR(Status)) {
+ if (!RETURN_ERROR (Status)) {
// call the architecture-specific routine to prepare for the new vector
// configuration to take effect
- ArchVectorConfig(VectorBase);
+ ArchVectorConfig (VectorBase);
- ArmWriteVBar(VectorBase);
+ ArmWriteVBar (VectorBase);
}
return RETURN_SUCCESS;
@@ -148,14 +146,14 @@ with default exception handlers. **/
STATIC
RETURN_STATUS
-CopyExceptionHandlers(
- IN PHYSICAL_ADDRESS BaseAddress
+CopyExceptionHandlers (
+ IN PHYSICAL_ADDRESS BaseAddress
)
{
- RETURN_STATUS Status;
- UINTN Length;
- UINTN Index;
- UINT32 *VectorBase;
+ RETURN_STATUS Status;
+ UINTN Length;
+ UINTN Index;
+ UINT32 *VectorBase;
// ensure that the destination value specifies an address meeting the vector alignment requirements
ASSERT ((BaseAddress & gExceptionVectorAlignmentMask) == 0);
@@ -167,37 +165,35 @@ CopyExceptionHandlers( VectorBase = (UINT32 *)(UINTN)BaseAddress;
- if (FeaturePcdGet(PcdDebuggerExceptionSupport) == TRUE) {
+ if (FeaturePcdGet (PcdDebuggerExceptionSupport) == TRUE) {
// Save existing vector table, in case debugger is already hooked in
- CopyMem((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (EFI_EXCEPTION_CALLBACK)* (gMaxExceptionNumber+1));
+ CopyMem ((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (EFI_EXCEPTION_CALLBACK)* (gMaxExceptionNumber+1));
}
// Copy our assembly code into the page that contains the exception vectors.
- CopyMem((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);
+ CopyMem ((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);
//
// Initialize the C entry points for interrupts
//
for (Index = 0; Index <= gMaxExceptionNumber; Index++) {
- if (!FeaturePcdGet(PcdDebuggerExceptionSupport) ||
- (gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)gDebuggerNoHandlerValue)) {
-
- Status = RegisterExceptionHandler(Index, NULL);
- ASSERT_EFI_ERROR(Status);
- }
- else {
+ if (!FeaturePcdGet (PcdDebuggerExceptionSupport) ||
+ (gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)gDebuggerNoHandlerValue))
+ {
+ Status = RegisterExceptionHandler (Index, NULL);
+ ASSERT_EFI_ERROR (Status);
+ } else {
// If the debugger has already hooked put its vector back
VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index];
}
}
// Flush Caches since we updated executable stuff
- InvalidateInstructionCacheRange((VOID *)(UINTN)BaseAddress, Length);
+ InvalidateInstructionCacheRange ((VOID *)(UINTN)BaseAddress, Length);
return RETURN_SUCCESS;
}
-
/**
Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
@@ -216,9 +212,9 @@ with default interrupt/exception handlers. **/
EFI_STATUS
EFIAPI
-InitializeCpuInterruptHandlers(
-IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
-)
+InitializeCpuInterruptHandlers (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ )
{
// not needed, this is what the CPU driver is for
return EFI_UNSUPPORTED;
@@ -250,9 +246,9 @@ previously installed. or this function is not supported.
**/
RETURN_STATUS
-RegisterCpuInterruptHandler(
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_CPU_INTERRUPT_HANDLER ExceptionHandler
+RegisterCpuInterruptHandler (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_CPU_INTERRUPT_HANDLER ExceptionHandler
)
{
if (ExceptionType > gMaxExceptionNumber) {
@@ -287,19 +283,19 @@ If this parameter is NULL, then the handler will be uninstalled. **/
EFI_STATUS
EFIAPI
-RegisterExceptionHandler(
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+RegisterExceptionHandler (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
- return RegisterCpuInterruptHandler(ExceptionType, InterruptHandler);
+ return RegisterCpuInterruptHandler (ExceptionType, InterruptHandler);
}
VOID
EFIAPI
-CommonCExceptionHandler(
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN OUT EFI_SYSTEM_CONTEXT SystemContext
+CommonCExceptionHandler (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
)
{
if (ExceptionType <= gMaxExceptionNumber) {
@@ -307,13 +303,12 @@ CommonCExceptionHandler( gExceptionHandlers[ExceptionType](ExceptionType, SystemContext);
return;
}
- }
- else {
- DEBUG((DEBUG_ERROR, "Unknown exception type %d\n", ExceptionType));
- ASSERT(FALSE);
+ } else {
+ DEBUG ((DEBUG_ERROR, "Unknown exception type %d\n", ExceptionType));
+ ASSERT (FALSE);
}
- DefaultExceptionHandler(ExceptionType, SystemContext);
+ DefaultExceptionHandler (ExceptionType, SystemContext);
}
/**
@@ -341,8 +336,8 @@ CommonCExceptionHandler( EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlersEx (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
- IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
)
{
return InitializeCpuExceptionHandlers (VectorInfo);
diff --git a/ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.c b/ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.c index a65113fada..fbbecdc528 100644 --- a/ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.c +++ b/ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.c @@ -16,9 +16,9 @@ ArmGenericTimerEnableTimer ( VOID
)
{
- UINTN TimerCtrlReg;
+ UINTN TimerCtrlReg;
- TimerCtrlReg = ArmReadCntpCtl ();
+ TimerCtrlReg = ArmReadCntpCtl ();
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
ArmWriteCntpCtl (TimerCtrlReg);
}
@@ -37,9 +37,9 @@ ArmGenericTimerDisableTimer ( VOID
)
{
- UINTN TimerCtrlReg;
+ UINTN TimerCtrlReg;
- TimerCtrlReg = ArmReadCntpCtl ();
+ TimerCtrlReg = ArmReadCntpCtl ();
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
ArmWriteCntpCtl (TimerCtrlReg);
}
@@ -71,11 +71,10 @@ ArmGenericTimerGetTimerVal ( return ArmReadCntpTval ();
}
-
VOID
EFIAPI
ArmGenericTimerSetTimerVal (
- IN UINTN Value
+ IN UINTN Value
)
{
ArmWriteCntpTval (Value);
@@ -102,7 +101,7 @@ ArmGenericTimerGetTimerCtrlReg ( VOID
EFIAPI
ArmGenericTimerSetTimerCtrlReg (
- UINTN Value
+ UINTN Value
)
{
ArmWriteCntpCtl (Value);
@@ -120,7 +119,7 @@ ArmGenericTimerGetCompareVal ( VOID
EFIAPI
ArmGenericTimerSetCompareVal (
- IN UINT64 Value
+ IN UINT64 Value
)
{
ArmWriteCntpCval (Value);
diff --git a/ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c b/ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c index 74c85dd756..893125a111 100644 --- a/ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c +++ b/ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c @@ -16,9 +16,9 @@ ArmGenericTimerEnableTimer ( VOID
)
{
- UINTN TimerCtrlReg;
+ UINTN TimerCtrlReg;
- TimerCtrlReg = ArmReadCntvCtl ();
+ TimerCtrlReg = ArmReadCntvCtl ();
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
ArmWriteCntvCtl (TimerCtrlReg);
}
@@ -37,9 +37,9 @@ ArmGenericTimerDisableTimer ( VOID
)
{
- UINTN TimerCtrlReg;
+ UINTN TimerCtrlReg;
- TimerCtrlReg = ArmReadCntvCtl ();
+ TimerCtrlReg = ArmReadCntvCtl ();
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
ArmWriteCntvCtl (TimerCtrlReg);
}
@@ -71,11 +71,10 @@ ArmGenericTimerGetTimerVal ( return ArmReadCntvTval ();
}
-
VOID
EFIAPI
ArmGenericTimerSetTimerVal (
- IN UINTN Value
+ IN UINTN Value
)
{
ArmWriteCntvTval (Value);
@@ -102,7 +101,7 @@ ArmGenericTimerGetTimerCtrlReg ( VOID
EFIAPI
ArmGenericTimerSetTimerCtrlReg (
- UINTN Value
+ UINTN Value
)
{
ArmWriteCntvCtl (Value);
@@ -120,7 +119,7 @@ ArmGenericTimerGetCompareVal ( VOID
EFIAPI
ArmGenericTimerSetCompareVal (
- IN UINT64 Value
+ IN UINT64 Value
)
{
ArmWriteCntvCval (Value);
diff --git a/ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.c b/ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.c index 6fd69658e0..f017eb5c47 100644 --- a/ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.c +++ b/ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.c @@ -9,7 +9,7 @@ #include <Library/ArmLib.h>
#include <Library/ArmGicLib.h>
-STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;
+STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;
RETURN_STATUS
EFIAPI
@@ -17,7 +17,7 @@ ArmGicArchLibInitialize ( VOID
)
{
- UINT32 IccSre;
+ UINT32 IccSre;
// Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily
@@ -38,6 +38,7 @@ ArmGicArchLibInitialize ( ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
}
+
if (IccSre & ICC_SRE_EL2_SRE) {
mGicArchRevision = ARM_GIC_ARCH_REVISION_3;
goto Done;
diff --git a/ArmPkg/Library/ArmGicArchSecLib/ArmGicArchLib.c b/ArmPkg/Library/ArmGicArchSecLib/ArmGicArchLib.c index ca81951b2b..3c791a245c 100644 --- a/ArmPkg/Library/ArmGicArchSecLib/ArmGicArchLib.c +++ b/ArmPkg/Library/ArmGicArchSecLib/ArmGicArchLib.c @@ -15,7 +15,7 @@ ArmGicGetSupportedArchRevision ( VOID
)
{
- UINT32 IccSre;
+ UINT32 IccSre;
// Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily
@@ -36,6 +36,7 @@ ArmGicGetSupportedArchRevision ( ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
}
+
if (IccSre & ICC_SRE_EL2_SRE) {
return ARM_GIC_ARCH_REVISION_3;
}
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c index 191a5fea31..7ab28e3e05 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c @@ -23,10 +23,10 @@ AArch64DataCacheOperation ( IN AARCH64_CACHE_OPERATION DataCacheOperation
)
{
- UINTN SavedInterruptState;
+ UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState ();
- ArmDisableInterrupts();
+ ArmDisableInterrupts ();
AArch64AllDataCachesOperation (DataCacheOperation);
@@ -99,7 +99,7 @@ ArmHasCcidx ( VOID
)
{
- UINTN Mmfr2;
+ UINTN Mmfr2;
Mmfr2 = ArmReadIdAA64Mmfr2 ();
return (((Mmfr2 >> 20) & 0xF) == 1) ? TRUE : FALSE;
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h index 318020277b..330481fc50 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h @@ -11,7 +11,9 @@ #ifndef AARCH64_LIB_H_
#define AARCH64_LIB_H_
-typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);
+typedef VOID (*AARCH64_CACHE_OPERATION)(
+ UINTN
+ );
VOID
AArch64AllDataCachesOperation (
@@ -33,7 +35,7 @@ ArmCleanDataCacheEntryBySetWay ( VOID
EFIAPI
ArmCleanInvalidateDataCacheEntryBySetWay (
- IN UINTN SetWayFormat
+ IN UINTN SetWayFormat
);
UINTN
@@ -53,4 +55,3 @@ ArmReadIdAA64Mmfr2 ( );
#endif // AARCH64_LIB_H_
-
diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c index c5dd3f8b2f..521d5be0de 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c @@ -23,7 +23,7 @@ ArmV7DataCacheOperation ( IN ARM_V7_CACHE_OPERATION DataCacheOperation
)
{
- UINTN SavedInterruptState;
+ UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState ();
ArmDisableInterrupts ();
@@ -114,7 +114,7 @@ ArmHasCcidx ( VOID
)
{
- UINTN Mmfr4;
+ UINTN Mmfr4;
Mmfr4 = ArmReadIdMmfr4 ();
return (((Mmfr4 >> 24) & 0xF) == 1) ? TRUE : FALSE;
diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h index 5a92ade2b3..404ff92c4e 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h @@ -9,21 +9,23 @@ #ifndef ARM_V7_LIB_H_
#define ARM_V7_LIB_H_
-#define ID_MMFR0_SHARELVL_SHIFT 12
-#define ID_MMFR0_SHARELVL_MASK 0xf
-#define ID_MMFR0_SHARELVL_ONE 0
-#define ID_MMFR0_SHARELVL_TWO 1
-
-#define ID_MMFR0_INNERSHR_SHIFT 28
-#define ID_MMFR0_INNERSHR_MASK 0xf
-#define ID_MMFR0_OUTERSHR_SHIFT 8
-#define ID_MMFR0_OUTERSHR_MASK 0xf
-
-#define ID_MMFR0_SHR_IMP_UNCACHED 0
-#define ID_MMFR0_SHR_IMP_HW_COHERENT 1
-#define ID_MMFR0_SHR_IGNORED 0xf
-
-typedef VOID (*ARM_V7_CACHE_OPERATION)(UINT32);
+#define ID_MMFR0_SHARELVL_SHIFT 12
+#define ID_MMFR0_SHARELVL_MASK 0xf
+#define ID_MMFR0_SHARELVL_ONE 0
+#define ID_MMFR0_SHARELVL_TWO 1
+
+#define ID_MMFR0_INNERSHR_SHIFT 28
+#define ID_MMFR0_INNERSHR_MASK 0xf
+#define ID_MMFR0_OUTERSHR_SHIFT 8
+#define ID_MMFR0_OUTERSHR_MASK 0xf
+
+#define ID_MMFR0_SHR_IMP_UNCACHED 0
+#define ID_MMFR0_SHR_IMP_HW_COHERENT 1
+#define ID_MMFR0_SHR_IGNORED 0xf
+
+typedef VOID (*ARM_V7_CACHE_OPERATION)(
+ UINT32
+ );
VOID
ArmV7AllDataCachesOperation (
@@ -45,7 +47,7 @@ ArmCleanDataCacheEntryBySetWay ( VOID
EFIAPI
ArmCleanInvalidateDataCacheEntryBySetWay (
- IN UINTN SetWayFormat
+ IN UINTN SetWayFormat
);
/** Reads the ID_MMFR4 register.
@@ -65,4 +67,3 @@ ArmReadIdPfr1 ( );
#endif // ARM_V7_LIB_H_
-
diff --git a/ArmPkg/Library/ArmLib/ArmLib.c b/ArmPkg/Library/ArmLib/ArmLib.c index c8622f1794..30849564fc 100644 --- a/ArmPkg/Library/ArmLib/ArmLib.c +++ b/ArmPkg/Library/ArmLib/ArmLib.c @@ -16,19 +16,19 @@ VOID
EFIAPI
ArmSetAuxCrBit (
- IN UINT32 Bits
+ IN UINT32 Bits
)
{
- ArmWriteAuxCr(ArmReadAuxCr() | Bits);
+ ArmWriteAuxCr (ArmReadAuxCr () | Bits);
}
VOID
EFIAPI
ArmUnsetAuxCrBit (
- IN UINT32 Bits
+ IN UINT32 Bits
)
{
- ArmWriteAuxCr(ArmReadAuxCr() & ~Bits);
+ ArmWriteAuxCr (ArmReadAuxCr () & ~Bits);
}
//
@@ -38,7 +38,7 @@ ArmUnsetAuxCrBit ( VOID
EFIAPI
ArmSetCpuActlrBit (
- IN UINTN Bits
+ IN UINTN Bits
)
{
ArmWriteCpuActlr (ArmReadCpuActlr () | Bits);
@@ -47,7 +47,7 @@ ArmSetCpuActlrBit ( VOID
EFIAPI
ArmUnsetCpuActlrBit (
- IN UINTN Bits
+ IN UINTN Bits
)
{
ArmWriteCpuActlr (ArmReadCpuActlr () & ~Bits);
@@ -77,7 +77,7 @@ ArmCacheWritebackGranule ( VOID
)
{
- UINTN CWG;
+ UINTN CWG;
CWG = (ArmCacheInfo () >> 24) & 0xf; // CTR_EL0.CWG
diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h index 668aefd6a0..7fb27068ce 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -11,19 +11,19 @@ #ifndef ARM_LIB_PRIVATE_H_
#define ARM_LIB_PRIVATE_H_
-#define CACHE_SIZE_4_KB (3UL)
-#define CACHE_SIZE_8_KB (4UL)
-#define CACHE_SIZE_16_KB (5UL)
-#define CACHE_SIZE_32_KB (6UL)
-#define CACHE_SIZE_64_KB (7UL)
-#define CACHE_SIZE_128_KB (8UL)
+#define CACHE_SIZE_4_KB (3UL)
+#define CACHE_SIZE_8_KB (4UL)
+#define CACHE_SIZE_16_KB (5UL)
+#define CACHE_SIZE_32_KB (6UL)
+#define CACHE_SIZE_64_KB (7UL)
+#define CACHE_SIZE_128_KB (8UL)
#define CACHE_ASSOCIATIVITY_DIRECT (0UL)
#define CACHE_ASSOCIATIVITY_4_WAY (2UL)
#define CACHE_ASSOCIATIVITY_8_WAY (3UL)
-#define CACHE_PRESENT (0UL)
-#define CACHE_NOT_PRESENT (1UL)
+#define CACHE_PRESENT (0UL)
+#define CACHE_NOT_PRESENT (1UL)
#define CACHE_LINE_LENGTH_32_BYTES (2UL)
@@ -32,25 +32,25 @@ #define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)
#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)
-#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)
-#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)
+#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)
+#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)
-#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))
-#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))
-#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))
-#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))
+#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))
+#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))
+#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))
+#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))
-#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
-#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))
-#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
-#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))
+#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
+#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))
+#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
+#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))
-#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)
-#define CACHE_TYPE_WRITE_BACK (0x0EUL)
+#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)
+#define CACHE_TYPE_WRITE_BACK (0x0EUL)
-#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)
-#define CACHE_ARCHITECTURE_UNIFIED (0UL)
-#define CACHE_ARCHITECTURE_SEPARATE (1UL)
+#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)
+#define CACHE_ARCHITECTURE_UNIFIED (0UL)
+#define CACHE_ARCHITECTURE_SEPARATE (1UL)
VOID
CPSRMaskInsert (
diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 8c736d25bb..89da40fd8e 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -26,31 +26,32 @@ ArmMemoryAttributeToPageAttribute ( )
{
switch (Attributes) {
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
- return TT_ATTR_INDX_MEMORY_WRITE_BACK;
-
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
- return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
-
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
- return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
-
- // Uncached and device mappings are treated as outer shareable by default,
- case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
- return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
-
- default:
- ASSERT (0);
- case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
- if (ArmReadCurrentEL () == AARCH64_EL2)
- return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
- else
- return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
+ return TT_ATTR_INDX_MEMORY_WRITE_BACK;
+
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
+ return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
+
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
+ return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
+
+ // Uncached and device mappings are treated as outer shareable by default,
+ case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
+ return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
+
+ default:
+ ASSERT (0);
+ case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
+ if (ArmReadCurrentEL () == AARCH64_EL2) {
+ return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
+ } else {
+ return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
+ }
}
}
@@ -61,7 +62,7 @@ ArmMemoryAttributeToPageAttribute ( STATIC
UINTN
GetRootTableEntryCount (
- IN UINTN T0SZ
+ IN UINTN T0SZ
)
{
return TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
@@ -70,7 +71,7 @@ GetRootTableEntryCount ( STATIC
UINTN
GetRootTableLevel (
- IN UINTN T0SZ
+ IN UINTN T0SZ
)
{
return (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
@@ -79,10 +80,10 @@ GetRootTableLevel ( STATIC
VOID
ReplaceTableEntry (
- IN UINT64 *Entry,
- IN UINT64 Value,
- IN UINT64 RegionStart,
- IN BOOLEAN IsLiveBlockMapping
+ IN UINT64 *Entry,
+ IN UINT64 Value,
+ IN UINT64 RegionStart,
+ IN BOOLEAN IsLiveBlockMapping
)
{
if (!ArmMmuEnabled () || !IsLiveBlockMapping) {
@@ -100,19 +101,22 @@ FreePageTablesRecursive ( IN UINTN Level
)
{
- UINTN Index;
+ UINTN Index;
ASSERT (Level <= 3);
if (Level < 3) {
for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
if ((TranslationTable[Index] & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
- FreePageTablesRecursive ((VOID *)(UINTN)(TranslationTable[Index] &
- TT_ADDRESS_MASK_BLOCK_ENTRY),
- Level + 1);
+ FreePageTablesRecursive (
+ (VOID *)(UINTN)(TranslationTable[Index] &
+ TT_ADDRESS_MASK_BLOCK_ENTRY),
+ Level + 1
+ );
}
}
}
+
FreePages (TranslationTable, 1);
}
@@ -126,6 +130,7 @@ IsBlockEntry ( if (Level == 3) {
return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3;
}
+
return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY;
}
@@ -143,39 +148,48 @@ IsTableEntry ( //
return FALSE;
}
+
return (Entry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY;
}
STATIC
EFI_STATUS
UpdateRegionMappingRecursive (
- IN UINT64 RegionStart,
- IN UINT64 RegionEnd,
- IN UINT64 AttributeSetMask,
- IN UINT64 AttributeClearMask,
- IN UINT64 *PageTable,
- IN UINTN Level
+ IN UINT64 RegionStart,
+ IN UINT64 RegionEnd,
+ IN UINT64 AttributeSetMask,
+ IN UINT64 AttributeClearMask,
+ IN UINT64 *PageTable,
+ IN UINTN Level
)
{
- UINTN BlockShift;
- UINT64 BlockMask;
- UINT64 BlockEnd;
- UINT64 *Entry;
- UINT64 EntryValue;
- VOID *TranslationTable;
- EFI_STATUS Status;
+ UINTN BlockShift;
+ UINT64 BlockMask;
+ UINT64 BlockEnd;
+ UINT64 *Entry;
+ UINT64 EntryValue;
+ VOID *TranslationTable;
+ EFI_STATUS Status;
ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0);
BlockShift = (Level + 1) * BITS_PER_LEVEL + MIN_T0SZ;
- BlockMask = MAX_UINT64 >> BlockShift;
-
- DEBUG ((DEBUG_VERBOSE, "%a(%d): %llx - %llx set %lx clr %lx\n", __FUNCTION__,
- Level, RegionStart, RegionEnd, AttributeSetMask, AttributeClearMask));
-
- for (; RegionStart < RegionEnd; RegionStart = BlockEnd) {
+ BlockMask = MAX_UINT64 >> BlockShift;
+
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a(%d): %llx - %llx set %lx clr %lx\n",
+ __FUNCTION__,
+ Level,
+ RegionStart,
+ RegionEnd,
+ AttributeSetMask,
+ AttributeClearMask
+ ));
+
+ for ( ; RegionStart < RegionEnd; RegionStart = BlockEnd) {
BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1);
- Entry = &PageTable[(RegionStart >> (64 - BlockShift)) & (TT_ENTRY_COUNT - 1)];
+ Entry = &PageTable[(RegionStart >> (64 - BlockShift)) & (TT_ENTRY_COUNT - 1)];
//
// If RegionStart or BlockEnd is not aligned to the block size at this
@@ -187,8 +201,9 @@ UpdateRegionMappingRecursive ( // we cannot replace it with a block entry without potentially losing
// attribute information, so keep the table entry in that case.
//
- if (Level == 0 || ((RegionStart | BlockEnd) & BlockMask) != 0 ||
- (IsTableEntry (*Entry, Level) && AttributeClearMask != 0)) {
+ if ((Level == 0) || (((RegionStart | BlockEnd) & BlockMask) != 0) ||
+ (IsTableEntry (*Entry, Level) && (AttributeClearMask != 0)))
+ {
ASSERT (Level < 3);
if (!IsTableEntry (*Entry, Level)) {
@@ -216,9 +231,14 @@ UpdateRegionMappingRecursive ( // We are splitting an existing block entry, so we have to populate
// the new table with the attributes of the block entry it replaces.
//
- Status = UpdateRegionMappingRecursive (RegionStart & ~BlockMask,
- (RegionStart | BlockMask) + 1, *Entry & TT_ATTRIBUTES_MASK,
- 0, TranslationTable, Level + 1);
+ Status = UpdateRegionMappingRecursive (
+ RegionStart & ~BlockMask,
+ (RegionStart | BlockMask) + 1,
+ *Entry & TT_ATTRIBUTES_MASK,
+ 0,
+ TranslationTable,
+ Level + 1
+ );
if (EFI_ERROR (Status)) {
//
// The range we passed to UpdateRegionMappingRecursive () is block
@@ -236,9 +256,14 @@ UpdateRegionMappingRecursive ( //
// Recurse to the next level
//
- Status = UpdateRegionMappingRecursive (RegionStart, BlockEnd,
- AttributeSetMask, AttributeClearMask, TranslationTable,
- Level + 1);
+ Status = UpdateRegionMappingRecursive (
+ RegionStart,
+ BlockEnd,
+ AttributeSetMask,
+ AttributeClearMask,
+ TranslationTable,
+ Level + 1
+ );
if (EFI_ERROR (Status)) {
if (!IsTableEntry (*Entry, Level)) {
//
@@ -250,16 +275,21 @@ UpdateRegionMappingRecursive ( //
FreePageTablesRecursive (TranslationTable, Level + 1);
}
+
return Status;
}
if (!IsTableEntry (*Entry, Level)) {
EntryValue = (UINTN)TranslationTable | TT_TYPE_TABLE_ENTRY;
- ReplaceTableEntry (Entry, EntryValue, RegionStart,
- IsBlockEntry (*Entry, Level));
+ ReplaceTableEntry (
+ Entry,
+ EntryValue,
+ RegionStart,
+ IsBlockEntry (*Entry, Level)
+ );
}
} else {
- EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;
+ EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;
EntryValue |= RegionStart;
EntryValue |= (Level == 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3
: TT_TYPE_BLOCK_ENTRY;
@@ -280,6 +310,7 @@ UpdateRegionMappingRecursive ( }
}
}
+
return EFI_SUCCESS;
}
@@ -292,7 +323,7 @@ UpdateRegionMapping ( IN UINT64 AttributeClearMask
)
{
- UINTN T0SZ;
+ UINTN T0SZ;
if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) {
return EFI_INVALID_PARAMETER;
@@ -300,9 +331,14 @@ UpdateRegionMapping ( T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;
- return UpdateRegionMappingRecursive (RegionStart, RegionStart + RegionLength,
- AttributeSetMask, AttributeClearMask, ArmGetTTBR0BaseAddress (),
- GetRootTableLevel (T0SZ));
+ return UpdateRegionMappingRecursive (
+ RegionStart,
+ RegionStart + RegionLength,
+ AttributeSetMask,
+ AttributeClearMask,
+ ArmGetTTBR0BaseAddress (),
+ GetRootTableLevel (T0SZ)
+ );
}
STATIC
@@ -323,31 +359,32 @@ FillTranslationTable ( STATIC
UINT64
GcdAttributeToPageAttribute (
- IN UINT64 GcdAttributes
+ IN UINT64 GcdAttributes
)
{
- UINT64 PageAttributes;
+ UINT64 PageAttributes;
switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {
- case EFI_MEMORY_UC:
- PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
- break;
- case EFI_MEMORY_WC:
- PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
- break;
- case EFI_MEMORY_WT:
- PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
- break;
- case EFI_MEMORY_WB:
- PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
- break;
- default:
- PageAttributes = TT_ATTR_INDX_MASK;
- break;
+ case EFI_MEMORY_UC:
+ PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
+ break;
+ case EFI_MEMORY_WC:
+ PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
+ break;
+ case EFI_MEMORY_WT:
+ PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
+ break;
+ case EFI_MEMORY_WB:
+ PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
+ break;
+ default:
+ PageAttributes = TT_ATTR_INDX_MASK;
+ break;
}
- if ((GcdAttributes & EFI_MEMORY_XP) != 0 ||
- (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC) {
+ if (((GcdAttributes & EFI_MEMORY_XP) != 0) ||
+ ((GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC))
+ {
if (ArmReadCurrentEL () == AARCH64_EL2) {
PageAttributes |= TT_XN_MASK;
} else {
@@ -364,15 +401,15 @@ GcdAttributeToPageAttribute ( EFI_STATUS
ArmSetMemoryAttributes (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
- UINT64 PageAttributes;
- UINT64 PageAttributeMask;
+ UINT64 PageAttributes;
+ UINT64 PageAttributeMask;
- PageAttributes = GcdAttributeToPageAttribute (Attributes);
+ PageAttributes = GcdAttributeToPageAttribute (Attributes);
PageAttributeMask = 0;
if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) {
@@ -380,22 +417,26 @@ ArmSetMemoryAttributes ( // No memory type was set in Attributes, so we are going to update the
// permissions only.
//
- PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK;
+ PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK;
PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK |
TT_PXN_MASK | TT_XN_MASK);
}
- return UpdateRegionMapping (BaseAddress, Length, PageAttributes,
- PageAttributeMask);
+ return UpdateRegionMapping (
+ BaseAddress,
+ Length,
+ PageAttributes,
+ PageAttributeMask
+ );
}
STATIC
EFI_STATUS
SetMemoryRegionAttribute (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes,
- IN UINT64 BlockEntryMask
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes,
+ IN UINT64 BlockEntryMask
)
{
return UpdateRegionMapping (BaseAddress, Length, Attributes, BlockEntryMask);
@@ -403,11 +444,11 @@ SetMemoryRegionAttribute ( EFI_STATUS
ArmSetMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- UINT64 Val;
+ UINT64 Val;
if (ArmReadCurrentEL () == AARCH64_EL1) {
Val = TT_PXN_MASK | TT_UXN_MASK;
@@ -419,16 +460,17 @@ ArmSetMemoryRegionNoExec ( BaseAddress,
Length,
Val,
- ~TT_ADDRESS_MASK_BLOCK_ENTRY);
+ ~TT_ADDRESS_MASK_BLOCK_ENTRY
+ );
}
EFI_STATUS
ArmClearMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- UINT64 Mask;
+ UINT64 Mask;
// XN maps to UXN in the EL1&0 translation regime
Mask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_PXN_MASK | TT_XN_MASK);
@@ -437,50 +479,53 @@ ArmClearMemoryRegionNoExec ( BaseAddress,
Length,
0,
- Mask);
+ Mask
+ );
}
EFI_STATUS
ArmSetMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return SetMemoryRegionAttribute (
BaseAddress,
Length,
TT_AP_RO_RO,
- ~TT_ADDRESS_MASK_BLOCK_ENTRY);
+ ~TT_ADDRESS_MASK_BLOCK_ENTRY
+ );
}
EFI_STATUS
ArmClearMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return SetMemoryRegionAttribute (
BaseAddress,
Length,
TT_AP_RW_RW,
- ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK));
+ ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK)
+ );
}
EFI_STATUS
EFIAPI
ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
- OUT VOID **TranslationTableBase OPTIONAL,
+ OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL
)
{
- VOID* TranslationTable;
- UINTN MaxAddressBits;
- UINT64 MaxAddress;
- UINTN T0SZ;
- UINTN RootTableEntryCount;
- UINT64 TCR;
- EFI_STATUS Status;
+ VOID *TranslationTable;
+ UINTN MaxAddressBits;
+ UINT64 MaxAddress;
+ UINTN T0SZ;
+ UINTN RootTableEntryCount;
+ UINT64 TCR;
+ EFI_STATUS Status;
if (MemoryTable == NULL) {
ASSERT (MemoryTable != NULL);
@@ -495,9 +540,9 @@ ArmConfigureMmu ( // use of 4 KB pages.
//
MaxAddressBits = MIN (ArmGetPhysicalAddressBits (), MAX_VA_BITS);
- MaxAddress = LShiftU64 (1ULL, MaxAddressBits) - 1;
+ MaxAddress = LShiftU64 (1ULL, MaxAddressBits) - 1;
- T0SZ = 64 - MaxAddressBits;
+ T0SZ = 64 - MaxAddressBits;
RootTableEntryCount = GetRootTableEntryCount (T0SZ);
//
@@ -506,7 +551,7 @@ ArmConfigureMmu ( // Ideally we will be running at EL2, but should support EL1 as well.
// UEFI should not run at EL3.
if (ArmReadCurrentEL () == AARCH64_EL2) {
- //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
+ // Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
// Set the Physical Address Size using MaxAddress
@@ -523,9 +568,11 @@ ArmConfigureMmu ( } else if (MaxAddress < SIZE_256TB) {
TCR |= TCR_PS_256TB;
} else {
- DEBUG ((DEBUG_ERROR,
+ DEBUG ((
+ DEBUG_ERROR,
"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
- MaxAddress));
+ MaxAddress
+ ));
ASSERT (0); // Bigger than 48-bit memory space are not supported
return EFI_UNSUPPORTED;
}
@@ -547,9 +594,11 @@ ArmConfigureMmu ( } else if (MaxAddress < SIZE_256TB) {
TCR |= TCR_IPS_256TB;
} else {
- DEBUG ((DEBUG_ERROR,
+ DEBUG ((
+ DEBUG_ERROR,
"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
- MaxAddress));
+ MaxAddress
+ ));
ASSERT (0); // Bigger than 48-bit memory space are not supported
return EFI_UNSUPPORTED;
}
@@ -579,6 +628,7 @@ ArmConfigureMmu ( if (TranslationTable == NULL) {
return EFI_OUT_OF_RESOURCES;
}
+
//
// We set TTBR0 just after allocating the table to retrieve its location from
// the subsequent functions without needing to pass this value across the
@@ -599,8 +649,10 @@ ArmConfigureMmu ( // Make sure we are not inadvertently hitting in the caches
// when populating the page tables.
//
- InvalidateDataCacheRange (TranslationTable,
- RootTableEntryCount * sizeof (UINT64));
+ InvalidateDataCacheRange (
+ TranslationTable,
+ RootTableEntryCount * sizeof (UINT64)
+ );
ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64));
while (MemoryTable->Length != 0) {
@@ -608,6 +660,7 @@ ArmConfigureMmu ( if (EFI_ERROR (Status)) {
goto FreeTranslationTable;
}
+
MemoryTable++;
}
@@ -618,10 +671,10 @@ ArmConfigureMmu ( // EFI_MEMORY_WB ==> MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK
//
ArmSetMAIR (
- MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |
+ MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |
MAIR_ATTR (TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) |
MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) |
- MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)
+ MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)
);
ArmDisableAlignmentCheck ();
@@ -643,14 +696,16 @@ ArmMmuBaseLibConstructor ( VOID
)
{
- extern UINT32 ArmReplaceLiveTranslationEntrySize;
+ extern UINT32 ArmReplaceLiveTranslationEntrySize;
//
// The ArmReplaceLiveTranslationEntry () helper function may be invoked
// with the MMU off so we have to ensure that it gets cleaned to the PoC
//
- WriteBackDataCacheRange ((VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
- ArmReplaceLiveTranslationEntrySize);
+ WriteBackDataCacheRange (
+ (VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
+ ArmReplaceLiveTranslationEntrySize
+ );
return RETURN_SUCCESS;
}
diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuPeiLibConstructor.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuPeiLibConstructor.c index 843b5d2781..caace2c17c 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuPeiLibConstructor.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuPeiLibConstructor.c @@ -16,14 +16,14 @@ EFI_STATUS
EFIAPI
ArmMmuPeiLibConstructor (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- extern UINT32 ArmReplaceLiveTranslationEntrySize;
+ extern UINT32 ArmReplaceLiveTranslationEntrySize;
- EFI_FV_FILE_INFO FileInfo;
- EFI_STATUS Status;
+ EFI_FV_FILE_INFO FileInfo;
+ EFI_STATUS Status;
ASSERT (FileHandle != NULL);
@@ -37,9 +37,10 @@ ArmMmuPeiLibConstructor ( // is executing from DRAM, we only need to perform the cache maintenance
// when not executing in place.
//
- if ((UINTN)FileInfo.Buffer <= (UINTN)ArmReplaceLiveTranslationEntry &&
+ if (((UINTN)FileInfo.Buffer <= (UINTN)ArmReplaceLiveTranslationEntry) &&
((UINTN)FileInfo.Buffer + FileInfo.BufferSize >=
- (UINTN)ArmReplaceLiveTranslationEntry + ArmReplaceLiveTranslationEntrySize)) {
+ (UINTN)ArmReplaceLiveTranslationEntry + ArmReplaceLiveTranslationEntrySize))
+ {
DEBUG ((DEBUG_INFO, "ArmMmuLib: skipping cache maintenance on XIP PEIM\n"));
} else {
DEBUG ((DEBUG_INFO, "ArmMmuLib: performing cache maintenance on shadowed PEIM\n"));
@@ -47,8 +48,10 @@ ArmMmuPeiLibConstructor ( // The ArmReplaceLiveTranslationEntry () helper function may be invoked
// with the MMU off so we have to ensure that it gets cleaned to the PoC
//
- WriteBackDataCacheRange ((VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
- ArmReplaceLiveTranslationEntrySize);
+ WriteBackDataCacheRange (
+ (VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
+ ArmReplaceLiveTranslationEntrySize
+ );
}
return RETURN_SUCCESS;
diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c index e3b02a9fba..bee8ad7028 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c @@ -19,9 +19,9 @@ ConvertSectionAttributesToPageAttributes ( IN BOOLEAN IsLargePage
)
{
- UINT32 PageAttributes;
+ UINT32 PageAttributes;
- PageAttributes = 0;
+ PageAttributes = 0;
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes, IsLargePage);
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes);
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes, IsLargePage);
diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c index b4fffed9ae..9e304ea05e 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -17,19 +17,19 @@ #include <Library/DebugLib.h>
#include <Library/PcdLib.h>
-#define ID_MMFR0_SHARELVL_SHIFT 12
-#define ID_MMFR0_SHARELVL_MASK 0xf
-#define ID_MMFR0_SHARELVL_ONE 0
-#define ID_MMFR0_SHARELVL_TWO 1
+#define ID_MMFR0_SHARELVL_SHIFT 12
+#define ID_MMFR0_SHARELVL_MASK 0xf
+#define ID_MMFR0_SHARELVL_ONE 0
+#define ID_MMFR0_SHARELVL_TWO 1
-#define ID_MMFR0_INNERSHR_SHIFT 28
-#define ID_MMFR0_INNERSHR_MASK 0xf
-#define ID_MMFR0_OUTERSHR_SHIFT 8
-#define ID_MMFR0_OUTERSHR_MASK 0xf
+#define ID_MMFR0_INNERSHR_SHIFT 28
+#define ID_MMFR0_INNERSHR_MASK 0xf
+#define ID_MMFR0_OUTERSHR_SHIFT 8
+#define ID_MMFR0_OUTERSHR_MASK 0xf
-#define ID_MMFR0_SHR_IMP_UNCACHED 0
-#define ID_MMFR0_SHR_IMP_HW_COHERENT 1
-#define ID_MMFR0_SHR_IGNORED 0xf
+#define ID_MMFR0_SHR_IMP_UNCACHED 0
+#define ID_MMFR0_SHR_IMP_HW_COHERENT 1
+#define ID_MMFR0_SHR_IGNORED 0xf
UINTN
EFIAPI
@@ -49,8 +49,8 @@ PreferNonshareableMemory ( VOID
)
{
- UINTN Mmfr;
- UINTN Val;
+ UINTN Mmfr;
+ UINTN Val;
if (FeaturePcdGet (PcdNormalMemoryNonshareableOverride)) {
return TRUE;
@@ -63,32 +63,33 @@ PreferNonshareableMemory ( //
Mmfr = ArmReadIdMmfr0 ();
switch ((Mmfr >> ID_MMFR0_SHARELVL_SHIFT) & ID_MMFR0_SHARELVL_MASK) {
- case ID_MMFR0_SHARELVL_ONE:
- // one level of shareability
- Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;
- break;
- case ID_MMFR0_SHARELVL_TWO:
- // two levels of shareability
- Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;
- break;
- default:
- // unexpected value -> shareable is the safe option
- ASSERT (FALSE);
- return FALSE;
+ case ID_MMFR0_SHARELVL_ONE:
+ // one level of shareability
+ Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;
+ break;
+ case ID_MMFR0_SHARELVL_TWO:
+ // two levels of shareability
+ Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;
+ break;
+ default:
+ // unexpected value -> shareable is the safe option
+ ASSERT (FALSE);
+ return FALSE;
}
+
return Val != ID_MMFR0_SHR_IMP_HW_COHERENT;
}
STATIC
VOID
PopulateLevel2PageTable (
- IN UINT32 *SectionEntry,
- IN UINT32 PhysicalBase,
- IN UINT32 RemainLength,
- IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
+ IN UINT32 *SectionEntry,
+ IN UINT32 PhysicalBase,
+ IN UINT32 RemainLength,
+ IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
)
{
- UINT32* PageEntry;
+ UINT32 *PageEntry;
UINT32 Pages;
UINT32 Index;
UINT32 PageAttributes;
@@ -104,7 +105,7 @@ PopulateLevel2PageTable ( break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
- PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
+ PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
@@ -132,7 +133,7 @@ PopulateLevel2PageTable ( // Level 2 Translation Table to it
if (*SectionEntry != 0) {
// The entry must be a page table. Otherwise it exists an overlapping in the memory map
- if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) {
+ if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (*SectionEntry)) {
TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;
} else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
// Case where a virtual memory map descriptor overlapped a section entry
@@ -140,60 +141,66 @@ PopulateLevel2PageTable ( // Allocate a Level2 Page Table for this Section
TranslationTable = (UINTN)AllocateAlignedPages (
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE),
- TRANSLATION_TABLE_PAGE_ALIGNMENT);
+ TRANSLATION_TABLE_PAGE_ALIGNMENT
+ );
// Translate the Section Descriptor into Page Descriptor
SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE);
- BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);
+ BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (*SectionEntry);
//
// Make sure we are not inadvertently hitting in the caches
// when populating the page tables
//
- InvalidateDataCacheRange ((VOID *)TranslationTable,
- TRANSLATION_TABLE_PAGE_SIZE);
+ InvalidateDataCacheRange (
+ (VOID *)TranslationTable,
+ TRANSLATION_TABLE_PAGE_SIZE
+ );
// Populate the new Level2 Page Table for the section
- PageEntry = (UINT32*)TranslationTable;
+ PageEntry = (UINT32 *)TranslationTable;
for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
- PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor;
+ PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (BaseSectionAddress + (Index << 12)) | SectionDescriptor;
}
// Overwrite the section entry to point to the new Level2 Translation Table
*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
- (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
- TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
+ (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE (Attributes) ? (1 << 3) : 0) |
+ TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
} else {
// We do not support the other section type (16MB Section)
- ASSERT(0);
+ ASSERT (0);
return;
}
} else {
TranslationTable = (UINTN)AllocateAlignedPages (
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE),
- TRANSLATION_TABLE_PAGE_ALIGNMENT);
+ TRANSLATION_TABLE_PAGE_ALIGNMENT
+ );
//
// Make sure we are not inadvertently hitting in the caches
// when populating the page tables
//
- InvalidateDataCacheRange ((VOID *)TranslationTable,
- TRANSLATION_TABLE_PAGE_SIZE);
+ InvalidateDataCacheRange (
+ (VOID *)TranslationTable,
+ TRANSLATION_TABLE_PAGE_SIZE
+ );
ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);
*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
- (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
- TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
+ (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE (Attributes) ? (1 << 3) : 0) |
+ TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
}
FirstPageOffset = (PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
- PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;
- Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;
+ PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;
+ Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;
ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT);
for (Index = 0; Index < Pages; Index++) {
- *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;
+ *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (PhysicalBase) | PageAttributes;
PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;
}
@@ -202,8 +209,10 @@ PopulateLevel2PageTable ( // [speculatively] since the previous invalidate are evicted again.
//
ArmDataMemoryBarrier ();
- InvalidateDataCacheRange ((UINT32 *)TranslationTable + FirstPageOffset,
- RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry));
+ InvalidateDataCacheRange (
+ (UINT32 *)TranslationTable + FirstPageOffset,
+ RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry)
+ );
}
STATIC
@@ -219,50 +228,50 @@ FillTranslationTable ( UINT64 RemainLength;
UINT32 PageMapLength;
- ASSERT(MemoryRegion->Length > 0);
+ ASSERT (MemoryRegion->Length > 0);
if (MemoryRegion->PhysicalBase >= SIZE_4GB) {
return;
}
PhysicalBase = (UINT32)MemoryRegion->PhysicalBase;
- RemainLength = MIN(MemoryRegion->Length, SIZE_4GB - PhysicalBase);
+ RemainLength = MIN (MemoryRegion->Length, SIZE_4GB - PhysicalBase);
switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (0);
Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH (0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
- Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0);
+ Attributes = TT_DESCRIPTOR_SECTION_DEVICE (0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (1);
Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH (1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
- Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);
+ Attributes = TT_DESCRIPTOR_SECTION_DEVICE (1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (1);
break;
default:
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (0);
break;
}
@@ -271,14 +280,15 @@ FillTranslationTable ( }
// Get the first section entry for this mapping
- SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
+ SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS (TranslationTable, MemoryRegion->VirtualBase);
while (RemainLength != 0) {
- if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0 &&
- RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {
+ if ((PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0) &&
+ (RemainLength >= TT_DESCRIPTOR_SECTION_SIZE))
+ {
// Case: Physical address aligned on the Section Size (1MB) && the length
// is greater than the Section Size
- *SectionEntry = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
+ *SectionEntry = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (PhysicalBase) | Attributes;
//
// Issue a DMB to ensure that the page table entry update made it to
@@ -291,14 +301,21 @@ FillTranslationTable ( PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;
} else {
- PageMapLength = MIN ((UINT32)RemainLength, TT_DESCRIPTOR_SECTION_SIZE -
- (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE));
+ PageMapLength = MIN (
+ (UINT32)RemainLength,
+ TT_DESCRIPTOR_SECTION_SIZE -
+ (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE)
+ );
// Case: Physical address aligned on the Section Size (1MB) && the length
// does not fill a section
// Case: Physical address NOT aligned on the Section Size (1MB)
- PopulateLevel2PageTable (SectionEntry, PhysicalBase, PageMapLength,
- MemoryRegion->Attributes);
+ PopulateLevel2PageTable (
+ SectionEntry,
+ PhysicalBase,
+ PageMapLength,
+ MemoryRegion->Attributes
+ );
//
// Issue a DMB to ensure that the page table entry update made it to
@@ -323,16 +340,17 @@ RETURN_STATUS EFIAPI
ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
- OUT VOID **TranslationTableBase OPTIONAL,
+ OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL
)
{
- VOID *TranslationTable;
- UINT32 TTBRAttributes;
+ VOID *TranslationTable;
+ UINT32 TTBRAttributes;
TranslationTable = AllocateAlignedPages (
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE),
- TRANSLATION_TABLE_SECTION_ALIGNMENT);
+ TRANSLATION_TABLE_SECTION_ALIGNMENT
+ );
if (TranslationTable == NULL) {
return RETURN_OUT_OF_RESOURCES;
}
@@ -389,25 +407,27 @@ ArmConfigureMmu ( //
ArmSetTTBCR (0);
- ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
- DOMAIN_ACCESS_CONTROL_NONE(14) |
- DOMAIN_ACCESS_CONTROL_NONE(13) |
- DOMAIN_ACCESS_CONTROL_NONE(12) |
- DOMAIN_ACCESS_CONTROL_NONE(11) |
- DOMAIN_ACCESS_CONTROL_NONE(10) |
- DOMAIN_ACCESS_CONTROL_NONE( 9) |
- DOMAIN_ACCESS_CONTROL_NONE( 8) |
- DOMAIN_ACCESS_CONTROL_NONE( 7) |
- DOMAIN_ACCESS_CONTROL_NONE( 6) |
- DOMAIN_ACCESS_CONTROL_NONE( 5) |
- DOMAIN_ACCESS_CONTROL_NONE( 4) |
- DOMAIN_ACCESS_CONTROL_NONE( 3) |
- DOMAIN_ACCESS_CONTROL_NONE( 2) |
- DOMAIN_ACCESS_CONTROL_NONE( 1) |
- DOMAIN_ACCESS_CONTROL_CLIENT(0));
-
- ArmEnableInstructionCache();
- ArmEnableDataCache();
- ArmEnableMmu();
+ ArmSetDomainAccessControl (
+ DOMAIN_ACCESS_CONTROL_NONE (15) |
+ DOMAIN_ACCESS_CONTROL_NONE (14) |
+ DOMAIN_ACCESS_CONTROL_NONE (13) |
+ DOMAIN_ACCESS_CONTROL_NONE (12) |
+ DOMAIN_ACCESS_CONTROL_NONE (11) |
+ DOMAIN_ACCESS_CONTROL_NONE (10) |
+ DOMAIN_ACCESS_CONTROL_NONE (9) |
+ DOMAIN_ACCESS_CONTROL_NONE (8) |
+ DOMAIN_ACCESS_CONTROL_NONE (7) |
+ DOMAIN_ACCESS_CONTROL_NONE (6) |
+ DOMAIN_ACCESS_CONTROL_NONE (5) |
+ DOMAIN_ACCESS_CONTROL_NONE (4) |
+ DOMAIN_ACCESS_CONTROL_NONE (3) |
+ DOMAIN_ACCESS_CONTROL_NONE (2) |
+ DOMAIN_ACCESS_CONTROL_NONE (1) |
+ DOMAIN_ACCESS_CONTROL_CLIENT (0)
+ );
+
+ ArmEnableInstructionCache ();
+ ArmEnableDataCache ();
+ ArmEnableMmu ();
return RETURN_SUCCESS;
}
diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c index 6b9d7eba90..b402197ade 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c @@ -18,9 +18,9 @@ #include <Chipset/ArmV7.h>
-#define __EFI_MEMORY_RWX 0 // no restrictions
+#define __EFI_MEMORY_RWX 0 // no restrictions
-#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \
+#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \
EFI_MEMORY_WC | \
EFI_MEMORY_WT | \
EFI_MEMORY_WB | \
@@ -33,14 +33,14 @@ ConvertSectionToPages ( IN EFI_PHYSICAL_ADDRESS BaseAddress
)
{
- UINT32 FirstLevelIdx;
- UINT32 SectionDescriptor;
- UINT32 PageTableDescriptor;
- UINT32 PageDescriptor;
- UINT32 Index;
+ UINT32 FirstLevelIdx;
+ UINT32 SectionDescriptor;
+ UINT32 PageTableDescriptor;
+ UINT32 PageDescriptor;
+ UINT32 Index;
- volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
- volatile ARM_PAGE_TABLE_ENTRY *PageTable;
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
+ volatile ARM_PAGE_TABLE_ENTRY *PageTable;
DEBUG ((DEBUG_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
@@ -48,12 +48,12 @@ ConvertSectionToPages ( FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
// Calculate index into first level translation table for start of modification
- FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
+ FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
// Get section attributes and convert to page attributes
SectionDescriptor = FirstLevelTable[FirstLevelIdx];
- PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (SectionDescriptor, FALSE);
+ PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (SectionDescriptor, FALSE);
// Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1);
@@ -63,7 +63,7 @@ ConvertSectionToPages ( // Write the page table entries out
for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
- PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;
+ PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (BaseAddress + (Index << 12)) | PageDescriptor;
}
// Formulate page table entry, Domain=0, NS=0
@@ -78,27 +78,27 @@ ConvertSectionToPages ( STATIC
EFI_STATUS
UpdatePageEntries (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes,
- OUT BOOLEAN *FlushTlbs OPTIONAL
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes,
+ OUT BOOLEAN *FlushTlbs OPTIONAL
)
{
- EFI_STATUS Status;
- UINT32 EntryValue;
- UINT32 EntryMask;
- UINT32 FirstLevelIdx;
- UINT32 Offset;
- UINT32 NumPageEntries;
- UINT32 Descriptor;
- UINT32 p;
- UINT32 PageTableIndex;
- UINT32 PageTableEntry;
- UINT32 CurrentPageTableEntry;
- VOID *Mva;
-
- volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
- volatile ARM_PAGE_TABLE_ENTRY *PageTable;
+ EFI_STATUS Status;
+ UINT32 EntryValue;
+ UINT32 EntryMask;
+ UINT32 FirstLevelIdx;
+ UINT32 Offset;
+ UINT32 NumPageEntries;
+ UINT32 Descriptor;
+ UINT32 p;
+ UINT32 PageTableIndex;
+ UINT32 PageTableEntry;
+ UINT32 CurrentPageTableEntry;
+ VOID *Mva;
+
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
+ volatile ARM_PAGE_TABLE_ENTRY *PageTable;
Status = EFI_SUCCESS;
@@ -156,19 +156,19 @@ UpdatePageEntries ( // Iterate for the number of 4KB pages to change
Offset = 0;
- for(p = 0; p < NumPageEntries; p++) {
+ for (p = 0; p < NumPageEntries; p++) {
// Calculate index into first level translation table for page table value
- FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
+ FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
// Read the descriptor from the first level page table
Descriptor = FirstLevelTable[FirstLevelIdx];
// Does this descriptor need to be converted from section entry to 4K pages?
- if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {
+ if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (Descriptor)) {
Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
// Exit for loop
break;
}
@@ -181,7 +181,7 @@ UpdatePageEntries ( }
// Obtain page table base address
- PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);
+ PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS (Descriptor);
// Calculate index into the page table
PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
@@ -204,9 +204,8 @@ UpdatePageEntries ( ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);
}
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
Offset += TT_DESCRIPTOR_PAGE_SIZE;
-
} // End first level translation table loop
return Status;
@@ -215,21 +214,21 @@ UpdatePageEntries ( STATIC
EFI_STATUS
UpdateSectionEntries (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
- EFI_STATUS Status;
- UINT32 EntryMask;
- UINT32 EntryValue;
- UINT32 FirstLevelIdx;
- UINT32 NumSections;
- UINT32 i;
- UINT32 CurrentDescriptor;
- UINT32 Descriptor;
- VOID *Mva;
- volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
+ EFI_STATUS Status;
+ UINT32 EntryMask;
+ UINT32 EntryValue;
+ UINT32 FirstLevelIdx;
+ UINT32 NumSections;
+ UINT32 i;
+ UINT32 CurrentDescriptor;
+ UINT32 Descriptor;
+ VOID *Mva;
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
Status = EFI_SUCCESS;
@@ -286,24 +285,25 @@ UpdateSectionEntries ( FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
// calculate index into first level translation table for start of modification
- FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
+ FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
// calculate number of 1MB first level entries this applies to
NumSections = (UINT32)(Length / TT_DESCRIPTOR_SECTION_SIZE);
// iterate through each descriptor
- for(i=0; i<NumSections; i++) {
+ for (i = 0; i < NumSections; i++) {
CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
// has this descriptor already been converted to pages?
- if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {
+ if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (CurrentDescriptor)) {
// forward this 1MB range to page table function instead
Status = UpdatePageEntries (
(FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT,
TT_DESCRIPTOR_SECTION_SIZE,
Attributes,
- NULL);
+ NULL
+ );
} else {
// still a section entry
@@ -334,14 +334,14 @@ UpdateSectionEntries ( EFI_STATUS
ArmSetMemoryAttributes (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
- EFI_STATUS Status;
- UINT64 ChunkLength;
- BOOLEAN FlushTlbs;
+ EFI_STATUS Status;
+ UINT64 ChunkLength;
+ BOOLEAN FlushTlbs;
if (BaseAddress > (UINT64)MAX_ADDRESS) {
return EFI_UNSUPPORTED;
@@ -355,19 +355,22 @@ ArmSetMemoryAttributes ( FlushTlbs = FALSE;
while (Length > 0) {
if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) &&
- Length >= TT_DESCRIPTOR_SECTION_SIZE) {
-
+ (Length >= TT_DESCRIPTOR_SECTION_SIZE))
+ {
ChunkLength = Length - Length % TT_DESCRIPTOR_SECTION_SIZE;
- DEBUG ((DEBUG_PAGE,
+ DEBUG ((
+ DEBUG_PAGE,
"SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n",
- BaseAddress, ChunkLength, Attributes));
+ BaseAddress,
+ ChunkLength,
+ Attributes
+ ));
Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes);
FlushTlbs = TRUE;
} else {
-
//
// Process page by page until the next section boundary, but only if
// we have more than a section's worth of area to deal with after that.
@@ -378,12 +381,20 @@ ArmSetMemoryAttributes ( ChunkLength = Length;
}
- DEBUG ((DEBUG_PAGE,
+ DEBUG ((
+ DEBUG_PAGE,
"SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n",
- BaseAddress, ChunkLength, Attributes));
+ BaseAddress,
+ ChunkLength,
+ Attributes
+ ));
- Status = UpdatePageEntries (BaseAddress, ChunkLength, Attributes,
- &FlushTlbs);
+ Status = UpdatePageEntries (
+ BaseAddress,
+ ChunkLength,
+ Attributes,
+ &FlushTlbs
+ );
}
if (EFI_ERROR (Status)) {
@@ -391,19 +402,20 @@ ArmSetMemoryAttributes ( }
BaseAddress += ChunkLength;
- Length -= ChunkLength;
+ Length -= ChunkLength;
}
if (FlushTlbs) {
ArmInvalidateTlb ();
}
+
return Status;
}
EFI_STATUS
ArmSetMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP);
@@ -411,8 +423,8 @@ ArmSetMemoryRegionNoExec ( EFI_STATUS
ArmClearMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);
@@ -420,8 +432,8 @@ ArmClearMemoryRegionNoExec ( EFI_STATUS
ArmSetMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);
@@ -429,8 +441,8 @@ ArmSetMemoryRegionReadOnly ( EFI_STATUS
ArmClearMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);
diff --git a/ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.c b/ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.c index 8dc2d07e39..8d5d37e7ae 100644 --- a/ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.c +++ b/ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.c @@ -34,7 +34,7 @@ MtlWaitUntilChannelFree ( @retval UINT32* Pointer to the payload.
**/
-UINT32*
+UINT32 *
MtlGetChannelPayload (
IN MTL_CHANNEL *Channel
)
diff --git a/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c b/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c index 97d49816aa..7bcd348495 100644 --- a/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c +++ b/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c @@ -36,30 +36,30 @@ EFI_STATUS
EFIAPI
LibResetSystem (
- IN EFI_RESET_TYPE ResetType,
- IN EFI_STATUS ResetStatus,
- IN UINTN DataSize,
- IN CHAR16 *ResetData OPTIONAL
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN CHAR16 *ResetData OPTIONAL
)
{
- ARM_SMC_ARGS ArmSmcArgs;
+ ARM_SMC_ARGS ArmSmcArgs;
switch (ResetType) {
- case EfiResetPlatformSpecific:
+ case EfiResetPlatformSpecific:
// Map the platform specific reset as reboot
- case EfiResetWarm:
+ case EfiResetWarm:
// Map a warm reset into a cold reset
- case EfiResetCold:
- // Send a PSCI 0.2 SYSTEM_RESET command
- ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
- break;
- case EfiResetShutdown:
- // Send a PSCI 0.2 SYSTEM_OFF command
- ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;
- break;
- default:
- ASSERT (FALSE);
- return EFI_UNSUPPORTED;
+ case EfiResetCold:
+ // Send a PSCI 0.2 SYSTEM_RESET command
+ ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
+ break;
+ case EfiResetShutdown:
+ // Send a PSCI 0.2 SYSTEM_OFF command
+ ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;
+ break;
+ default:
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
}
ArmCallSmc (&ArmSmcArgs);
diff --git a/ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.c b/ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.c index 2d79aadaf1..3c1adef8eb 100644 --- a/ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.c +++ b/ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.c @@ -10,7 +10,7 @@ VOID
ArmCallSmc (
- IN OUT ARM_SMC_ARGS *Args
+ IN OUT ARM_SMC_ARGS *Args
)
{
}
diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c index 8b5ff5c27e..6688fca37a 100644 --- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c +++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c @@ -31,7 +31,7 @@ ResetCold ( VOID
)
{
- ARM_SMC_ARGS ArmSmcArgs;
+ ARM_SMC_ARGS ArmSmcArgs;
// Send a PSCI 0.2 SYSTEM_RESET command
ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
@@ -66,7 +66,7 @@ ResetShutdown ( VOID
)
{
- ARM_SMC_ARGS ArmSmcArgs;
+ ARM_SMC_ARGS ArmSmcArgs;
// Send a PSCI 0.2 SYSTEM_OFF command
ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;
@@ -87,8 +87,8 @@ ResetShutdown ( VOID
EFIAPI
ResetPlatformSpecific (
- IN UINTN DataSize,
- IN VOID *ResetData
+ IN UINTN DataSize,
+ IN VOID *ResetData
)
{
// Map the platform specific reset as reboot
@@ -110,30 +110,30 @@ ResetPlatformSpecific ( VOID
EFIAPI
ResetSystem (
- IN EFI_RESET_TYPE ResetType,
- IN EFI_STATUS ResetStatus,
- IN UINTN DataSize,
- IN VOID *ResetData OPTIONAL
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN VOID *ResetData OPTIONAL
)
{
switch (ResetType) {
- case EfiResetWarm:
- ResetWarm ();
- break;
+ case EfiResetWarm:
+ ResetWarm ();
+ break;
- case EfiResetCold:
- ResetCold ();
- break;
+ case EfiResetCold:
+ ResetCold ();
+ break;
- case EfiResetShutdown:
- ResetShutdown ();
- return;
+ case EfiResetShutdown:
+ ResetShutdown ();
+ return;
- case EfiResetPlatformSpecific:
- ResetPlatformSpecific (DataSize, ResetData);
- return;
+ case EfiResetPlatformSpecific:
+ ResetPlatformSpecific (DataSize, ResetData);
+ return;
- default:
- return;
+ default:
+ return;
}
}
diff --git a/ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.c b/ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.c index 77e2473678..55ec564309 100644 --- a/ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.c +++ b/ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.c @@ -18,35 +18,47 @@ * have been expected we use aeabi_float_t and aeabi_double_t respectively
* instead.
*/
-typedef uint32_t aeabi_float_t;
-typedef uint64_t aeabi_double_t;
+typedef uint32_t aeabi_float_t;
+typedef uint64_t aeabi_double_t;
/*
* Helpers to convert between float32 and aeabi_float_t, and float64 and
* aeabi_double_t used by the AEABI functions below.
*/
-static aeabi_float_t f32_to_f(float32_t val)
+static aeabi_float_t
+f32_to_f (
+ float32_t val
+ )
{
return val.v;
}
-static float32_t f32_from_f(aeabi_float_t val)
+static float32_t
+f32_from_f (
+ aeabi_float_t val
+ )
{
- float32_t res;
+ float32_t res;
res.v = val;
return res;
}
-static aeabi_double_t f64_to_d(float64_t val)
+static aeabi_double_t
+f64_to_d (
+ float64_t val
+ )
{
return val.v;
}
-static float64_t f64_from_d(aeabi_double_t val)
+static float64_t
+f64_from_d (
+ aeabi_double_t val
+ )
{
- float64_t res;
+ float64_t res;
res.v = val;
@@ -64,220 +76,346 @@ static float64_t f64_from_d(aeabi_double_t val) * Table 2, Standard aeabi_double_t precision floating-point arithmetic helper
* functions
*/
-
-aeabi_double_t __aeabi_dadd(aeabi_double_t a, aeabi_double_t b)
+aeabi_double_t
+__aeabi_dadd (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_to_d(f64_add(f64_from_d(a), f64_from_d(b)));
+ return f64_to_d (f64_add (f64_from_d (a), f64_from_d (b)));
}
-aeabi_double_t __aeabi_ddiv(aeabi_double_t a, aeabi_double_t b)
+aeabi_double_t
+__aeabi_ddiv (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_to_d(f64_div(f64_from_d(a), f64_from_d(b)));
+ return f64_to_d (f64_div (f64_from_d (a), f64_from_d (b)));
}
-aeabi_double_t __aeabi_dmul(aeabi_double_t a, aeabi_double_t b)
+aeabi_double_t
+__aeabi_dmul (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_to_d(f64_mul(f64_from_d(a), f64_from_d(b)));
+ return f64_to_d (f64_mul (f64_from_d (a), f64_from_d (b)));
}
-
-aeabi_double_t __aeabi_drsub(aeabi_double_t a, aeabi_double_t b)
+aeabi_double_t
+__aeabi_drsub (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_to_d(f64_sub(f64_from_d(b), f64_from_d(a)));
+ return f64_to_d (f64_sub (f64_from_d (b), f64_from_d (a)));
}
-aeabi_double_t __aeabi_dsub(aeabi_double_t a, aeabi_double_t b)
+aeabi_double_t
+__aeabi_dsub (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_to_d(f64_sub(f64_from_d(a), f64_from_d(b)));
+ return f64_to_d (f64_sub (f64_from_d (a), f64_from_d (b)));
}
/*
* Table 3, double precision floating-point comparison helper functions
*/
-
-int __aeabi_dcmpeq(aeabi_double_t a, aeabi_double_t b)
+int
+__aeabi_dcmpeq (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_eq(f64_from_d(a), f64_from_d(b));
+ return f64_eq (f64_from_d (a), f64_from_d (b));
}
-int __aeabi_dcmplt(aeabi_double_t a, aeabi_double_t b)
+int
+__aeabi_dcmplt (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_lt(f64_from_d(a), f64_from_d(b));
+ return f64_lt (f64_from_d (a), f64_from_d (b));
}
-int __aeabi_dcmple(aeabi_double_t a, aeabi_double_t b)
+int
+__aeabi_dcmple (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_le(f64_from_d(a), f64_from_d(b));
+ return f64_le (f64_from_d (a), f64_from_d (b));
}
-int __aeabi_dcmpge(aeabi_double_t a, aeabi_double_t b)
+int
+__aeabi_dcmpge (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_le(f64_from_d(b), f64_from_d(a));
+ return f64_le (f64_from_d (b), f64_from_d (a));
}
-int __aeabi_dcmpgt(aeabi_double_t a, aeabi_double_t b)
+int
+__aeabi_dcmpgt (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_lt(f64_from_d(b), f64_from_d(a));
+ return f64_lt (f64_from_d (b), f64_from_d (a));
}
/*
* Table 4, Standard single precision floating-point arithmetic helper
* functions
*/
-
-aeabi_float_t __aeabi_fadd(aeabi_float_t a, aeabi_float_t b)
+aeabi_float_t
+__aeabi_fadd (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_to_f(f32_add(f32_from_f(a), f32_from_f(b)));
+ return f32_to_f (f32_add (f32_from_f (a), f32_from_f (b)));
}
-aeabi_float_t __aeabi_fdiv(aeabi_float_t a, aeabi_float_t b)
+aeabi_float_t
+__aeabi_fdiv (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_to_f(f32_div(f32_from_f(a), f32_from_f(b)));
+ return f32_to_f (f32_div (f32_from_f (a), f32_from_f (b)));
}
-aeabi_float_t __aeabi_fmul(aeabi_float_t a, aeabi_float_t b)
+aeabi_float_t
+__aeabi_fmul (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_to_f(f32_mul(f32_from_f(a), f32_from_f(b)));
+ return f32_to_f (f32_mul (f32_from_f (a), f32_from_f (b)));
}
-aeabi_float_t __aeabi_frsub(aeabi_float_t a, aeabi_float_t b)
+aeabi_float_t
+__aeabi_frsub (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_to_f(f32_sub(f32_from_f(b), f32_from_f(a)));
+ return f32_to_f (f32_sub (f32_from_f (b), f32_from_f (a)));
}
-aeabi_float_t __aeabi_fsub(aeabi_float_t a, aeabi_float_t b)
+aeabi_float_t
+__aeabi_fsub (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_to_f(f32_sub(f32_from_f(a), f32_from_f(b)));
+ return f32_to_f (f32_sub (f32_from_f (a), f32_from_f (b)));
}
/*
* Table 5, Standard single precision floating-point comparison helper
* functions
*/
-
-int __aeabi_fcmpeq(aeabi_float_t a, aeabi_float_t b)
+int
+__aeabi_fcmpeq (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_eq(f32_from_f(a), f32_from_f(b));
+ return f32_eq (f32_from_f (a), f32_from_f (b));
}
-int __aeabi_fcmplt(aeabi_float_t a, aeabi_float_t b)
+int
+__aeabi_fcmplt (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_lt(f32_from_f(a), f32_from_f(b));
+ return f32_lt (f32_from_f (a), f32_from_f (b));
}
-int __aeabi_fcmple(aeabi_float_t a, aeabi_float_t b)
+int
+__aeabi_fcmple (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_le(f32_from_f(a), f32_from_f(b));
+ return f32_le (f32_from_f (a), f32_from_f (b));
}
-int __aeabi_fcmpge(aeabi_float_t a, aeabi_float_t b)
+int
+__aeabi_fcmpge (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_le(f32_from_f(b), f32_from_f(a));
+ return f32_le (f32_from_f (b), f32_from_f (a));
}
-int __aeabi_fcmpgt(aeabi_float_t a, aeabi_float_t b)
+int
+__aeabi_fcmpgt (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_lt(f32_from_f(b), f32_from_f(a));
+ return f32_lt (f32_from_f (b), f32_from_f (a));
}
/*
* Table 6, Standard floating-point to integer conversions
*/
-
-int __aeabi_d2iz(aeabi_double_t a)
+int
+__aeabi_d2iz (
+ aeabi_double_t a
+ )
{
- return f64_to_i32_r_minMag(f64_from_d(a), false);
+ return f64_to_i32_r_minMag (f64_from_d (a), false);
}
-unsigned __aeabi_d2uiz(aeabi_double_t a)
+unsigned
+__aeabi_d2uiz (
+ aeabi_double_t a
+ )
{
- return f64_to_ui32_r_minMag(f64_from_d(a), false);
+ return f64_to_ui32_r_minMag (f64_from_d (a), false);
}
-long long __aeabi_d2lz(aeabi_double_t a)
+long long
+__aeabi_d2lz (
+ aeabi_double_t a
+ )
{
- return f64_to_i64_r_minMag(f64_from_d(a), false);
+ return f64_to_i64_r_minMag (f64_from_d (a), false);
}
-unsigned long long __aeabi_d2ulz(aeabi_double_t a)
+unsigned long long
+__aeabi_d2ulz (
+ aeabi_double_t a
+ )
{
- return f64_to_ui64_r_minMag(f64_from_d(a), false);
+ return f64_to_ui64_r_minMag (f64_from_d (a), false);
}
-int __aeabi_f2iz(aeabi_float_t a)
+int
+__aeabi_f2iz (
+ aeabi_float_t a
+ )
{
- return f32_to_i32_r_minMag(f32_from_f(a), false);
+ return f32_to_i32_r_minMag (f32_from_f (a), false);
}
-unsigned __aeabi_f2uiz(aeabi_float_t a)
+unsigned
+__aeabi_f2uiz (
+ aeabi_float_t a
+ )
{
- return f32_to_ui32_r_minMag(f32_from_f(a), false);
+ return f32_to_ui32_r_minMag (f32_from_f (a), false);
}
-long long __aeabi_f2lz(aeabi_float_t a)
+long long
+__aeabi_f2lz (
+ aeabi_float_t a
+ )
{
- return f32_to_i64_r_minMag(f32_from_f(a), false);
+ return f32_to_i64_r_minMag (f32_from_f (a), false);
}
-unsigned long long __aeabi_f2ulz(aeabi_float_t a)
+unsigned long long
+__aeabi_f2ulz (
+ aeabi_float_t a
+ )
{
- return f32_to_ui64_r_minMag(f32_from_f(a), false);
+ return f32_to_ui64_r_minMag (f32_from_f (a), false);
}
/*
* Table 7, Standard conversions between floating types
*/
-
-aeabi_float_t __aeabi_d2f(aeabi_double_t a)
+aeabi_float_t
+__aeabi_d2f (
+ aeabi_double_t a
+ )
{
- return f32_to_f(f64_to_f32(f64_from_d(a)));
+ return f32_to_f (f64_to_f32 (f64_from_d (a)));
}
-aeabi_double_t __aeabi_f2d(aeabi_float_t a)
+aeabi_double_t
+__aeabi_f2d (
+ aeabi_float_t a
+ )
{
- return f64_to_d(f32_to_f64(f32_from_f(a)));
+ return f64_to_d (f32_to_f64 (f32_from_f (a)));
}
/*
* Table 8, Standard integer to floating-point conversions
*/
-
-aeabi_double_t __aeabi_i2d(int a)
+aeabi_double_t
+__aeabi_i2d (
+ int a
+ )
{
- return f64_to_d(i32_to_f64(a));
+ return f64_to_d (i32_to_f64 (a));
}
-aeabi_double_t __aeabi_ui2d(unsigned a)
+aeabi_double_t
+__aeabi_ui2d (
+ unsigned a
+ )
{
- return f64_to_d(ui32_to_f64(a));
+ return f64_to_d (ui32_to_f64 (a));
}
-aeabi_double_t __aeabi_l2d(long long a)
+aeabi_double_t
+__aeabi_l2d (
+ long long a
+ )
{
- return f64_to_d(i64_to_f64(a));
+ return f64_to_d (i64_to_f64 (a));
}
-aeabi_double_t __aeabi_ul2d(unsigned long long a)
+aeabi_double_t
+__aeabi_ul2d (
+ unsigned long long a
+ )
{
- return f64_to_d(ui64_to_f64(a));
+ return f64_to_d (ui64_to_f64 (a));
}
-aeabi_float_t __aeabi_i2f(int a)
+aeabi_float_t
+__aeabi_i2f (
+ int a
+ )
{
- return f32_to_f(i32_to_f32(a));
+ return f32_to_f (i32_to_f32 (a));
}
-aeabi_float_t __aeabi_ui2f(unsigned a)
+aeabi_float_t
+__aeabi_ui2f (
+ unsigned a
+ )
{
- return f32_to_f(ui32_to_f32(a));
+ return f32_to_f (ui32_to_f32 (a));
}
-aeabi_float_t __aeabi_l2f(long long a)
+aeabi_float_t
+__aeabi_l2f (
+ long long a
+ )
{
- return f32_to_f(i64_to_f32(a));
+ return f32_to_f (i64_to_f32 (a));
}
-aeabi_float_t __aeabi_ul2f(unsigned long long a)
+aeabi_float_t
+__aeabi_ul2f (
+ unsigned long long a
+ )
{
- return f32_to_f(ui64_to_f32(a));
+ return f32_to_f (ui64_to_f32 (a));
}
diff --git a/ArmPkg/Library/ArmSoftFloatLib/platform.h b/ArmPkg/Library/ArmSoftFloatLib/platform.h index fddf9de04d..3b70360568 100644 --- a/ArmPkg/Library/ArmSoftFloatLib/platform.h +++ b/ArmPkg/Library/ArmSoftFloatLib/platform.h @@ -8,9 +8,9 @@ #ifndef ARM_SOFT_FLOAT_LIB_H_
#define ARM_SOFT_FLOAT_LIB_H_
-#define LITTLEENDIAN 1
-#define INLINE static inline
-#define SOFTFLOAT_BUILTIN_CLZ 1
+#define LITTLEENDIAN 1
+#define INLINE static inline
+#define SOFTFLOAT_BUILTIN_CLZ 1
#define SOFTFLOAT_FAST_INT64
#include "opts-GCC.h"
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memcmp_ms.c b/ArmPkg/Library/CompilerIntrinsicsLib/memcmp_ms.c index b0e0322951..cedbfca471 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/memcmp_ms.c +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memcmp_ms.c @@ -1,32 +1,45 @@ -//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
//
// Copyright (c) 2019, Pete Batard. All rights reserved.
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
-//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
-#if defined(_M_ARM64)
-typedef unsigned __int64 size_t;
+#if defined (_M_ARM64)
+typedef unsigned __int64 size_t;
#else
-typedef unsigned __int32 size_t;
+typedef unsigned __int32 size_t;
#endif
-int memcmp(void *, void *, size_t);
+int
+memcmp (
+ void *,
+ void *,
+ size_t
+ );
+
#pragma intrinsic(memcmp)
#pragma function(memcmp)
-int memcmp(const void *s1, const void *s2, size_t n)
+int
+memcmp (
+ const void *s1,
+ const void *s2,
+ size_t n
+ )
{
- unsigned char const *t1;
- unsigned char const *t2;
+ unsigned char const *t1;
+ unsigned char const *t2;
t1 = s1;
t2 = s2;
while (n-- != 0) {
- if (*t1 != *t2)
+ if (*t1 != *t2) {
return (int)*t1 - (int)*t2;
+ }
+
t1++;
t2++;
}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memcpy.c b/ArmPkg/Library/CompilerIntrinsicsLib/memcpy.c index e1d0b72782..415146f7f2 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/memcpy.c +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memcpy.c @@ -1,18 +1,23 @@ -//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
//
// Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
-//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
typedef __SIZE_TYPE__ size_t;
-static void __memcpy(void *dest, const void *src, size_t n)
+static void
+__memcpy (
+ void *dest,
+ const void *src,
+ size_t n
+ )
{
- unsigned char *d;
- unsigned char const *s;
+ unsigned char *d;
+ unsigned char const *s;
d = dest;
s = src;
@@ -22,21 +27,41 @@ static void __memcpy(void *dest, const void *src, size_t n) }
}
-void *memcpy(void *dest, const void *src, size_t n)
+void *
+memcpy (
+ void *dest,
+ const void *src,
+ size_t n
+ )
{
- __memcpy(dest, src, n);
+ __memcpy (dest, src, n);
return dest;
}
#ifdef __arm__
-__attribute__((__alias__("__memcpy")))
-void __aeabi_memcpy(void *dest, const void *src, size_t n);
+__attribute__ ((__alias__ ("__memcpy")))
+void
+__aeabi_memcpy (
+ void *dest,
+ const void *src,
+ size_t n
+ );
-__attribute__((__alias__("__memcpy")))
-void __aeabi_memcpy4(void *dest, const void *src, size_t n);
+__attribute__ ((__alias__ ("__memcpy")))
+void
+__aeabi_memcpy4 (
+ void *dest,
+ const void *src,
+ size_t n
+ );
-__attribute__((__alias__("__memcpy")))
-void __aeabi_memcpy8(void *dest, const void *src, size_t n);
+__attribute__ ((__alias__ ("__memcpy")))
+void
+__aeabi_memcpy8 (
+ void *dest,
+ const void *src,
+ size_t n
+ );
#endif
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c b/ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c index a52fd8deef..0eafa83ed4 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c @@ -1,25 +1,36 @@ -//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
//
// Copyright (c) 2017, Pete Batard. All rights reserved.<BR>
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
-//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
-#if defined(_M_ARM64)
-typedef unsigned __int64 size_t;
+#if defined (_M_ARM64)
+typedef unsigned __int64 size_t;
#else
-typedef unsigned __int32 size_t;
+typedef unsigned __int32 size_t;
#endif
-void* memcpy(void *, const void *, size_t);
+void *
+memcpy (
+ void *,
+ const void *,
+ size_t
+ );
+
#pragma intrinsic(memcpy)
#pragma function(memcpy)
-void* memcpy(void *dest, const void *src, size_t n)
+void *
+memcpy (
+ void *dest,
+ const void *src,
+ size_t n
+ )
{
- unsigned char *d;
- unsigned char const *s;
+ unsigned char *d;
+ unsigned char const *s;
d = dest;
s = src;
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memmove_ms.c b/ArmPkg/Library/CompilerIntrinsicsLib/memmove_ms.c index ebc9e385aa..f68eb52a6c 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/memmove_ms.c +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memmove_ms.c @@ -1,25 +1,36 @@ -//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
//
// Copyright (c) 2019, Pete Batard. All rights reserved.
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
-//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
-#if defined(_M_ARM64)
-typedef unsigned __int64 size_t;
+#if defined (_M_ARM64)
+typedef unsigned __int64 size_t;
#else
-typedef unsigned __int32 size_t;
+typedef unsigned __int32 size_t;
#endif
-void* memmove(void *, const void *, size_t);
+void *
+memmove (
+ void *,
+ const void *,
+ size_t
+ );
+
#pragma intrinsic(memmove)
#pragma function(memmove)
-void* memmove(void *dest, const void *src, size_t n)
+void *
+memmove (
+ void *dest,
+ const void *src,
+ size_t n
+ )
{
- unsigned char *d;
- unsigned char const *s;
+ unsigned char *d;
+ unsigned char const *s;
d = dest;
s = src;
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memset.c b/ArmPkg/Library/CompilerIntrinsicsLib/memset.c index 63f6cf68a6..3e45302fe6 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/memset.c +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memset.c @@ -1,18 +1,23 @@ -//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
//
// Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
-//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
typedef __SIZE_TYPE__ size_t;
-static __attribute__((__used__))
-void *__memset(void *s, int c, size_t n)
+static __attribute__ ((__used__))
+void *
+__memset (
+ void *s,
+ int c,
+ size_t n
+ )
{
- unsigned char *d;
+ unsigned char *d;
d = s;
@@ -29,31 +34,63 @@ void *__memset(void *s, int c, size_t n) // object was pulled into the link due to the definitions below. So make
// our memset() 'weak' to let the other implementation take precedence.
//
-__attribute__((__weak__, __alias__("__memset")))
-void *memset(void *dest, int c, size_t n);
+__attribute__ ((__weak__, __alias__ ("__memset")))
+void *
+memset (
+ void *dest,
+ int c,
+ size_t n
+ );
#ifdef __arm__
-void __aeabi_memset(void *dest, size_t n, int c)
+void
+__aeabi_memset (
+ void *dest,
+ size_t n,
+ int c
+ )
{
- __memset(dest, c, n);
+ __memset (dest, c, n);
}
-__attribute__((__alias__("__aeabi_memset")))
-void __aeabi_memset4(void *dest, size_t n, int c);
+__attribute__ ((__alias__ ("__aeabi_memset")))
+void
+__aeabi_memset4 (
+ void *dest,
+ size_t n,
+ int c
+ );
-__attribute__((__alias__("__aeabi_memset")))
-void __aeabi_memset8(void *dest, size_t n, int c);
+__attribute__ ((__alias__ ("__aeabi_memset")))
+void
+__aeabi_memset8 (
+ void *dest,
+ size_t n,
+ int c
+ );
-void __aeabi_memclr(void *dest, size_t n)
+void
+__aeabi_memclr (
+ void *dest,
+ size_t n
+ )
{
- __memset(dest, 0, n);
+ __memset (dest, 0, n);
}
-__attribute__((__alias__("__aeabi_memclr")))
-void __aeabi_memclr4(void *dest, size_t n);
+__attribute__ ((__alias__ ("__aeabi_memclr")))
+void
+__aeabi_memclr4 (
+ void *dest,
+ size_t n
+ );
-__attribute__((__alias__("__aeabi_memclr")))
-void __aeabi_memclr8(void *dest, size_t n);
+__attribute__ ((__alias__ ("__aeabi_memclr")))
+void
+__aeabi_memclr8 (
+ void *dest,
+ size_t n
+ );
#endif
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c b/ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c index b88a5f2c5f..5882cd28b0 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c @@ -1,24 +1,35 @@ -//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
//
// Copyright (c) 2017, Pete Batard. All rights reserved.<BR>
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
-//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
-#if defined(_M_ARM64)
-typedef unsigned __int64 size_t;
+#if defined (_M_ARM64)
+typedef unsigned __int64 size_t;
#else
-typedef unsigned __int32 size_t;
+typedef unsigned __int32 size_t;
#endif
-void* memset(void *, int, size_t);
+void *
+memset (
+ void *,
+ int,
+ size_t
+ );
+
#pragma intrinsic(memset)
#pragma function(memset)
-void *memset(void *s, int c, size_t n)
+void *
+memset (
+ void *s,
+ int c,
+ size_t n
+ )
{
- unsigned char *d;
+ unsigned char *d;
d = s;
diff --git a/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c b/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c index c8edc4f5cf..77c92f9ecc 100644 --- a/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c +++ b/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c @@ -22,7 +22,6 @@ #define GET_OCCUPIED_SIZE(ActualSize, Alignment) \
(ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((Alignment) - 1))
-
// Vector Table for Sec Phase
VOID
DebugAgentVectorTable (
@@ -53,7 +52,7 @@ GetFileState ( FileState = FfsHeader->State;
if (ErasePolarity != 0) {
- FileState = (EFI_FFS_FILE_STATE)~FileState;
+ FileState = (EFI_FFS_FILE_STATE) ~FileState;
}
HighestBit = 0x80;
@@ -79,10 +78,10 @@ CalculateHeaderChecksum ( IN EFI_FFS_FILE_HEADER *FileHeader
)
{
- UINT8 Sum;
+ UINT8 Sum;
// Calculate the sum of the header
- Sum = CalculateSum8 ((CONST VOID*)FileHeader,sizeof(EFI_FFS_FILE_HEADER));
+ Sum = CalculateSum8 ((CONST VOID *)FileHeader, sizeof (EFI_FFS_FILE_HEADER));
// State field (since this indicates the different state of file).
Sum = (UINT8)(Sum - FileHeader->State);
@@ -95,24 +94,24 @@ CalculateHeaderChecksum ( EFI_STATUS
GetFfsFile (
- IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader,
- IN EFI_FV_FILETYPE FileType,
- OUT EFI_FFS_FILE_HEADER **FileHeader
+ IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader,
+ IN EFI_FV_FILETYPE FileType,
+ OUT EFI_FFS_FILE_HEADER **FileHeader
)
{
- UINT64 FvLength;
- UINTN FileOffset;
- EFI_FFS_FILE_HEADER *FfsFileHeader;
- UINT8 ErasePolarity;
- UINT8 FileState;
- UINT32 FileLength;
- UINT32 FileOccupiedSize;
+ UINT64 FvLength;
+ UINTN FileOffset;
+ EFI_FFS_FILE_HEADER *FfsFileHeader;
+ UINT8 ErasePolarity;
+ UINT8 FileState;
+ UINT32 FileLength;
+ UINT32 FileOccupiedSize;
ASSERT (FwVolHeader->Signature == EFI_FVH_SIGNATURE);
- FvLength = FwVolHeader->FvLength;
+ FvLength = FwVolHeader->FvLength;
FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FwVolHeader + FwVolHeader->HeaderLength);
- FileOffset = FwVolHeader->HeaderLength;
+ FileOffset = FwVolHeader->HeaderLength;
if (FwVolHeader->Attributes & EFI_FVB2_ERASE_POLARITY) {
ErasePolarity = 1;
@@ -125,42 +124,42 @@ GetFfsFile ( FileState = GetFileState (ErasePolarity, FfsFileHeader);
switch (FileState) {
+ case EFI_FILE_HEADER_INVALID:
+ FileOffset += sizeof (EFI_FFS_FILE_HEADER);
+ FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + sizeof (EFI_FFS_FILE_HEADER));
+ break;
- case EFI_FILE_HEADER_INVALID:
- FileOffset += sizeof(EFI_FFS_FILE_HEADER);
- FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + sizeof(EFI_FFS_FILE_HEADER));
- break;
-
- case EFI_FILE_DATA_VALID:
- case EFI_FILE_MARKED_FOR_UPDATE:
- if (CalculateHeaderChecksum (FfsFileHeader) != 0) {
- ASSERT (FALSE);
- return EFI_NOT_FOUND;
- }
+ case EFI_FILE_DATA_VALID:
+ case EFI_FILE_MARKED_FOR_UPDATE:
+ if (CalculateHeaderChecksum (FfsFileHeader) != 0) {
+ ASSERT (FALSE);
+ return EFI_NOT_FOUND;
+ }
- if (FfsFileHeader->Type == FileType) {
- *FileHeader = FfsFileHeader;
- return EFI_SUCCESS;
- }
+ if (FfsFileHeader->Type == FileType) {
+ *FileHeader = FfsFileHeader;
+ return EFI_SUCCESS;
+ }
- FileLength = *(UINT32 *)(FfsFileHeader->Size) & 0x00FFFFFF;
- FileOccupiedSize = GET_OCCUPIED_SIZE(FileLength, 8);
+ FileLength = *(UINT32 *)(FfsFileHeader->Size) & 0x00FFFFFF;
+ FileOccupiedSize = GET_OCCUPIED_SIZE (FileLength, 8);
- FileOffset += FileOccupiedSize;
- FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + FileOccupiedSize);
- break;
+ FileOffset += FileOccupiedSize;
+ FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + FileOccupiedSize);
+ break;
- case EFI_FILE_DELETED:
- FileLength = *(UINT32 *)(FfsFileHeader->Size) & 0x00FFFFFF;
- FileOccupiedSize = GET_OCCUPIED_SIZE(FileLength, 8);
- FileOffset += FileOccupiedSize;
- FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + FileOccupiedSize);
- break;
+ case EFI_FILE_DELETED:
+ FileLength = *(UINT32 *)(FfsFileHeader->Size) & 0x00FFFFFF;
+ FileOccupiedSize = GET_OCCUPIED_SIZE (FileLength, 8);
+ FileOffset += FileOccupiedSize;
+ FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + FileOccupiedSize);
+ break;
- default:
- return EFI_NOT_FOUND;
+ default:
+ return EFI_NOT_FOUND;
}
}
+
return EFI_NOT_FOUND;
}
@@ -170,25 +169,25 @@ GetImageContext ( OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
- EFI_STATUS Status;
- UINTN ParsedLength;
- UINTN SectionSize;
- UINTN SectionLength;
- EFI_COMMON_SECTION_HEADER *Section;
- VOID *EfiImage;
- UINTN ImageAddress;
- EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *DebugEntry;
- VOID *CodeViewEntryPointer;
-
- Section = (EFI_COMMON_SECTION_HEADER *)(FfsHeader + 1);
- SectionSize = *(UINT32 *)(FfsHeader->Size) & 0x00FFFFFF;
+ EFI_STATUS Status;
+ UINTN ParsedLength;
+ UINTN SectionSize;
+ UINTN SectionLength;
+ EFI_COMMON_SECTION_HEADER *Section;
+ VOID *EfiImage;
+ UINTN ImageAddress;
+ EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *DebugEntry;
+ VOID *CodeViewEntryPointer;
+
+ Section = (EFI_COMMON_SECTION_HEADER *)(FfsHeader + 1);
+ SectionSize = *(UINT32 *)(FfsHeader->Size) & 0x00FFFFFF;
SectionSize -= sizeof (EFI_FFS_FILE_HEADER);
ParsedLength = 0;
- EfiImage = NULL;
+ EfiImage = NULL;
while (ParsedLength < SectionSize) {
if ((Section->Type == EFI_SECTION_PE32) || (Section->Type == EFI_SECTION_TE)) {
- EfiImage = (EFI_IMAGE_OPTIONAL_HEADER_UNION*)(Section + 1);
+ EfiImage = (EFI_IMAGE_OPTIONAL_HEADER_UNION *)(Section + 1);
break;
}
@@ -201,7 +200,7 @@ GetImageContext ( SectionLength = GET_OCCUPIED_SIZE (SectionLength, 4);
ASSERT (SectionLength != 0);
ParsedLength += SectionLength;
- Section = (EFI_COMMON_SECTION_HEADER *)((UINT8 *)Section + SectionLength);
+ Section = (EFI_COMMON_SECTION_HEADER *)((UINT8 *)Section + SectionLength);
}
if (EfiImage == NULL) {
@@ -214,27 +213,27 @@ GetImageContext ( ImageContext->ImageRead = PeCoffLoaderImageReadFromMemory;
Status = PeCoffLoaderGetImageInfo (ImageContext);
- if (!EFI_ERROR(Status) && ((VOID*)(UINTN)ImageContext->DebugDirectoryEntryRva != NULL)) {
+ if (!EFI_ERROR (Status) && ((VOID *)(UINTN)ImageContext->DebugDirectoryEntryRva != NULL)) {
ImageAddress = ImageContext->ImageAddress;
if (ImageContext->IsTeImage) {
- ImageAddress += sizeof (EFI_TE_IMAGE_HEADER) - ((EFI_TE_IMAGE_HEADER*)EfiImage)->StrippedSize;
+ ImageAddress += sizeof (EFI_TE_IMAGE_HEADER) - ((EFI_TE_IMAGE_HEADER *)EfiImage)->StrippedSize;
}
- DebugEntry = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY*)(ImageAddress + ImageContext->DebugDirectoryEntryRva);
+ DebugEntry = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *)(ImageAddress + ImageContext->DebugDirectoryEntryRva);
if (DebugEntry->Type == EFI_IMAGE_DEBUG_TYPE_CODEVIEW) {
- CodeViewEntryPointer = (VOID *) (ImageAddress + (UINTN) DebugEntry->RVA);
- switch (* (UINT32 *) CodeViewEntryPointer) {
- case CODEVIEW_SIGNATURE_NB10:
- ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY);
- break;
- case CODEVIEW_SIGNATURE_RSDS:
- ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY);
- break;
- case CODEVIEW_SIGNATURE_MTOC:
- ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY);
- break;
- default:
- break;
+ CodeViewEntryPointer = (VOID *)(ImageAddress + (UINTN)DebugEntry->RVA);
+ switch (*(UINT32 *)CodeViewEntryPointer) {
+ case CODEVIEW_SIGNATURE_NB10:
+ ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY);
+ break;
+ case CODEVIEW_SIGNATURE_RSDS:
+ ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY);
+ break;
+ case CODEVIEW_SIGNATURE_MTOC:
+ ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY);
+ break;
+ default:
+ break;
}
}
}
@@ -272,8 +271,8 @@ InitializeDebugAgent ( IN DEBUG_AGENT_CONTINUE Function OPTIONAL
)
{
- EFI_STATUS Status;
- EFI_FFS_FILE_HEADER *FfsHeader;
+ EFI_STATUS Status;
+ EFI_FFS_FILE_HEADER *FfsHeader;
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
// We use InitFlag to know if DebugAgent has been initialized from
@@ -283,10 +282,10 @@ InitializeDebugAgent ( //
// Get the Sec or PrePeiCore module (defined as SEC type module)
//
- Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet64 (PcdSecureFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);
- if (!EFI_ERROR(Status)) {
- Status = GetImageContext (FfsHeader,&ImageContext);
- if (!EFI_ERROR(Status)) {
+ Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet64 (PcdSecureFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);
+ if (!EFI_ERROR (Status)) {
+ Status = GetImageContext (FfsHeader, &ImageContext);
+ if (!EFI_ERROR (Status)) {
PeCoffLoaderRelocateImageExtraAction (&ImageContext);
}
}
@@ -294,10 +293,10 @@ InitializeDebugAgent ( //
// Get the PrePi or PrePeiCore module (defined as SEC type module)
//
- Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);
- if (!EFI_ERROR(Status)) {
- Status = GetImageContext (FfsHeader,&ImageContext);
- if (!EFI_ERROR(Status)) {
+ Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);
+ if (!EFI_ERROR (Status)) {
+ Status = GetImageContext (FfsHeader, &ImageContext);
+ if (!EFI_ERROR (Status)) {
PeCoffLoaderRelocateImageExtraAction (&ImageContext);
}
}
@@ -305,10 +304,10 @@ InitializeDebugAgent ( //
// Get the PeiCore module (defined as PEI_CORE type module)
//
- Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_PEI_CORE, &FfsHeader);
- if (!EFI_ERROR(Status)) {
- Status = GetImageContext (FfsHeader,&ImageContext);
- if (!EFI_ERROR(Status)) {
+ Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_PEI_CORE, &FfsHeader);
+ if (!EFI_ERROR (Status)) {
+ Status = GetImageContext (FfsHeader, &ImageContext);
+ if (!EFI_ERROR (Status)) {
PeCoffLoaderRelocateImageExtraAction (&ImageContext);
}
}
@@ -330,7 +329,7 @@ InitializeDebugAgent ( BOOLEAN
EFIAPI
SaveAndSetDebugTimerInterrupt (
- IN BOOLEAN EnableStatus
+ IN BOOLEAN EnableStatus
)
{
return FALSE;
diff --git a/ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.c b/ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.c index 2e8afc051e..3827122a96 100644 --- a/ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.c +++ b/ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.c @@ -17,7 +17,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/PeCoffExtraActionLib.h>
#include <Library/PrintLib.h>
-
/**
If the build is done on cygwin the paths are cygpaths.
/cygdrive/c/tmp.txt vs c:\tmp.txt so we need to convert
@@ -28,14 +27,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
CHAR8 *
DeCygwinPathIfNeeded (
- IN CHAR8 *Name,
- IN CHAR8 *Temp,
- IN UINTN Size
+ IN CHAR8 *Name,
+ IN CHAR8 *Temp,
+ IN UINTN Size
)
{
- CHAR8 *Ptr;
- UINTN Index;
- UINTN Index2;
+ CHAR8 *Ptr;
+ UINTN Index;
+ UINTN Index2;
Ptr = AsciiStrStr (Name, "/cygdrive/");
if (Ptr == NULL) {
@@ -45,19 +44,18 @@ DeCygwinPathIfNeeded ( for (Index = 9, Index2 = 0; (Index < (Size + 9)) && (Ptr[Index] != '\0'); Index++, Index2++) {
Temp[Index2] = Ptr[Index];
if (Temp[Index2] == '/') {
- Temp[Index2] = '\\' ;
- }
+ Temp[Index2] = '\\';
+ }
if (Index2 == 1) {
Temp[Index2 - 1] = Ptr[Index];
- Temp[Index2] = ':';
+ Temp[Index2] = ':';
}
}
return Temp;
}
-
/**
Performs additional actions after a PE/COFF image has been loaded and relocated.
@@ -73,32 +71,30 @@ PeCoffLoaderRelocateImageExtraAction ( IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
-#if !defined(MDEPKG_NDEBUG)
- CHAR8 Temp[512];
-#endif
+ #if !defined (MDEPKG_NDEBUG)
+ CHAR8 Temp[512];
+ #endif
if (ImageContext->PdbPointer) {
-#ifdef __CC_ARM
-#if (__ARMCC_VERSION < 500000)
+ #ifdef __CC_ARM
+ #if (__ARMCC_VERSION < 500000)
// Print out the command for the RVD debugger to load symbols for this image
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "load /a /ni /np %a &0x%p\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
-#else
+ #else
// Print out the command for the DS-5 to load symbols for this image
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "add-symbol-file %a 0x%p\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
-#endif
-#elif __GNUC__
+ #endif
+ #elif __GNUC__
// This may not work correctly if you generate PE/COFF directly as then the Offset would not be required
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "add-symbol-file %a 0x%p\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
-#else
- DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Loading driver at 0x%11p EntryPoint=0x%11p\n", (VOID *)(UINTN) ImageContext->ImageAddress, FUNCTION_ENTRY_POINT (ImageContext->EntryPoint)));
-#endif
+ #else
+ DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Loading driver at 0x%11p EntryPoint=0x%11p\n", (VOID *)(UINTN)ImageContext->ImageAddress, FUNCTION_ENTRY_POINT (ImageContext->EntryPoint)));
+ #endif
} else {
- DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Loading driver at 0x%11p EntryPoint=0x%11p\n", (VOID *)(UINTN) ImageContext->ImageAddress, FUNCTION_ENTRY_POINT (ImageContext->EntryPoint)));
+ DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Loading driver at 0x%11p EntryPoint=0x%11p\n", (VOID *)(UINTN)ImageContext->ImageAddress, FUNCTION_ENTRY_POINT (ImageContext->EntryPoint)));
}
}
-
-
/**
Performs additional actions just before a PE/COFF image is unloaded. Any resources
that were allocated by PeCoffLoaderRelocateImageExtraAction() must be freed.
@@ -115,21 +111,21 @@ PeCoffLoaderUnloadImageExtraAction ( IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
-#if !defined(MDEPKG_NDEBUG)
- CHAR8 Temp[512];
-#endif
+ #if !defined (MDEPKG_NDEBUG)
+ CHAR8 Temp[512];
+ #endif
if (ImageContext->PdbPointer) {
-#ifdef __CC_ARM
+ #ifdef __CC_ARM
// Print out the command for the RVD debugger to load symbols for this image
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "unload symbols_only %a\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp))));
-#elif __GNUC__
+ #elif __GNUC__
// This may not work correctly if you generate PE/COFF directly as then the Offset would not be required
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "remove-symbol-file %a 0x%08x\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
-#else
+ #else
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Unloading %a\n", ImageContext->PdbPointer));
-#endif
+ #endif
} else {
- DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Unloading driver at 0x%11p\n", (VOID *)(UINTN) ImageContext->ImageAddress));
+ DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Unloading driver at 0x%11p\n", (VOID *)(UINTN)ImageContext->ImageAddress));
}
}
diff --git a/ArmPkg/Library/DefaultExceptionHandlerLib/AArch64/DefaultExceptionHandler.c b/ArmPkg/Library/DefaultExceptionHandlerLib/AArch64/DefaultExceptionHandler.c index 2bb0888b43..f2bca5d740 100644 --- a/ArmPkg/Library/DefaultExceptionHandlerLib/AArch64/DefaultExceptionHandler.c +++ b/ArmPkg/Library/DefaultExceptionHandlerLib/AArch64/DefaultExceptionHandler.c @@ -22,14 +22,14 @@ #include <Protocol/DebugSupport.h>
#include <Protocol/LoadedImage.h>
-STATIC CHAR8 *gExceptionTypeString[] = {
+STATIC CHAR8 *gExceptionTypeString[] = {
"Synchronous",
"IRQ",
"FIQ",
"SError"
};
-STATIC BOOLEAN mRecursiveException;
+STATIC BOOLEAN mRecursiveException;
CHAR8 *
GetImageName (
@@ -41,47 +41,79 @@ GetImageName ( STATIC
VOID
DescribeInstructionOrDataAbort (
- IN CHAR8 *AbortType,
- IN UINTN Iss
+ IN CHAR8 *AbortType,
+ IN UINTN Iss
)
{
- CHAR8 *AbortCause;
+ CHAR8 *AbortCause;
switch (Iss & 0x3f) {
- case 0x0: AbortCause = "Address size fault, zeroth level of translation or translation table base register"; break;
- case 0x1: AbortCause = "Address size fault, first level"; break;
- case 0x2: AbortCause = "Address size fault, second level"; break;
- case 0x3: AbortCause = "Address size fault, third level"; break;
- case 0x4: AbortCause = "Translation fault, zeroth level"; break;
- case 0x5: AbortCause = "Translation fault, first level"; break;
- case 0x6: AbortCause = "Translation fault, second level"; break;
- case 0x7: AbortCause = "Translation fault, third level"; break;
- case 0x9: AbortCause = "Access flag fault, first level"; break;
- case 0xa: AbortCause = "Access flag fault, second level"; break;
- case 0xb: AbortCause = "Access flag fault, third level"; break;
- case 0xd: AbortCause = "Permission fault, first level"; break;
- case 0xe: AbortCause = "Permission fault, second level"; break;
- case 0xf: AbortCause = "Permission fault, third level"; break;
- case 0x10: AbortCause = "Synchronous external abort"; break;
- case 0x18: AbortCause = "Synchronous parity error on memory access"; break;
- case 0x11: AbortCause = "Asynchronous external abort"; break;
- case 0x19: AbortCause = "Asynchronous parity error on memory access"; break;
- case 0x14: AbortCause = "Synchronous external abort on translation table walk, zeroth level"; break;
- case 0x15: AbortCause = "Synchronous external abort on translation table walk, first level"; break;
- case 0x16: AbortCause = "Synchronous external abort on translation table walk, second level"; break;
- case 0x17: AbortCause = "Synchronous external abort on translation table walk, third level"; break;
- case 0x1c: AbortCause = "Synchronous parity error on memory access on translation table walk, zeroth level"; break;
- case 0x1d: AbortCause = "Synchronous parity error on memory access on translation table walk, first level"; break;
- case 0x1e: AbortCause = "Synchronous parity error on memory access on translation table walk, second level"; break;
- case 0x1f: AbortCause = "Synchronous parity error on memory access on translation table walk, third level"; break;
- case 0x21: AbortCause = "Alignment fault"; break;
- case 0x22: AbortCause = "Debug event"; break;
- case 0x30: AbortCause = "TLB conflict abort"; break;
+ case 0x0: AbortCause = "Address size fault, zeroth level of translation or translation table base register";
+ break;
+ case 0x1: AbortCause = "Address size fault, first level";
+ break;
+ case 0x2: AbortCause = "Address size fault, second level";
+ break;
+ case 0x3: AbortCause = "Address size fault, third level";
+ break;
+ case 0x4: AbortCause = "Translation fault, zeroth level";
+ break;
+ case 0x5: AbortCause = "Translation fault, first level";
+ break;
+ case 0x6: AbortCause = "Translation fault, second level";
+ break;
+ case 0x7: AbortCause = "Translation fault, third level";
+ break;
+ case 0x9: AbortCause = "Access flag fault, first level";
+ break;
+ case 0xa: AbortCause = "Access flag fault, second level";
+ break;
+ case 0xb: AbortCause = "Access flag fault, third level";
+ break;
+ case 0xd: AbortCause = "Permission fault, first level";
+ break;
+ case 0xe: AbortCause = "Permission fault, second level";
+ break;
+ case 0xf: AbortCause = "Permission fault, third level";
+ break;
+ case 0x10: AbortCause = "Synchronous external abort";
+ break;
+ case 0x18: AbortCause = "Synchronous parity error on memory access";
+ break;
+ case 0x11: AbortCause = "Asynchronous external abort";
+ break;
+ case 0x19: AbortCause = "Asynchronous parity error on memory access";
+ break;
+ case 0x14: AbortCause = "Synchronous external abort on translation table walk, zeroth level";
+ break;
+ case 0x15: AbortCause = "Synchronous external abort on translation table walk, first level";
+ break;
+ case 0x16: AbortCause = "Synchronous external abort on translation table walk, second level";
+ break;
+ case 0x17: AbortCause = "Synchronous external abort on translation table walk, third level";
+ break;
+ case 0x1c: AbortCause = "Synchronous parity error on memory access on translation table walk, zeroth level";
+ break;
+ case 0x1d: AbortCause = "Synchronous parity error on memory access on translation table walk, first level";
+ break;
+ case 0x1e: AbortCause = "Synchronous parity error on memory access on translation table walk, second level";
+ break;
+ case 0x1f: AbortCause = "Synchronous parity error on memory access on translation table walk, third level";
+ break;
+ case 0x21: AbortCause = "Alignment fault";
+ break;
+ case 0x22: AbortCause = "Debug event";
+ break;
+ case 0x30: AbortCause = "TLB conflict abort";
+ break;
case 0x33:
- case 0x34: AbortCause = "IMPLEMENTATION DEFINED"; break;
+ case 0x34: AbortCause = "IMPLEMENTATION DEFINED";
+ break;
case 0x35:
- case 0x36: AbortCause = "Domain fault"; break;
- default: AbortCause = ""; break;
+ case 0x36: AbortCause = "Domain fault";
+ break;
+ default: AbortCause = "";
+ break;
}
DEBUG ((DEBUG_ERROR, "\n%a: %a\n", AbortType, AbortCause));
@@ -90,24 +122,29 @@ DescribeInstructionOrDataAbort ( STATIC
VOID
DescribeExceptionSyndrome (
- IN UINT32 Esr
+ IN UINT32 Esr
)
{
- CHAR8 *Message;
- UINTN Ec;
- UINTN Iss;
+ CHAR8 *Message;
+ UINTN Ec;
+ UINTN Iss;
- Ec = Esr >> 26;
+ Ec = Esr >> 26;
Iss = Esr & 0x00ffffff;
switch (Ec) {
- case 0x15: Message = "SVC executed in AArch64"; break;
+ case 0x15: Message = "SVC executed in AArch64";
+ break;
case 0x20:
- case 0x21: DescribeInstructionOrDataAbort ("Instruction abort", Iss); return;
- case 0x22: Message = "PC alignment fault"; break;
- case 0x23: Message = "SP alignment fault"; break;
+ case 0x21: DescribeInstructionOrDataAbort ("Instruction abort", Iss);
+ return;
+ case 0x22: Message = "PC alignment fault";
+ break;
+ case 0x23: Message = "SP alignment fault";
+ break;
case 0x24:
- case 0x25: DescribeInstructionOrDataAbort ("Data abort", Iss); return;
+ case 0x25: DescribeInstructionOrDataAbort ("Data abort", Iss);
+ return;
default: return;
}
@@ -118,20 +155,22 @@ DescribeExceptionSyndrome ( STATIC
CONST CHAR8 *
BaseName (
- IN CONST CHAR8 *FullName
+ IN CONST CHAR8 *FullName
)
{
- CONST CHAR8 *Str;
+ CONST CHAR8 *Str;
Str = FullName + AsciiStrLen (FullName);
while (--Str > FullName) {
- if (*Str == '/' || *Str == '\\') {
+ if ((*Str == '/') || (*Str == '\\')) {
return Str + 1;
}
}
+
return Str;
}
+
#endif
/**
@@ -145,8 +184,8 @@ BaseName ( **/
VOID
DefaultExceptionHandler (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN OUT EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
)
{
CHAR8 Buffer[100];
@@ -154,75 +193,93 @@ DefaultExceptionHandler ( INT32 Offset;
if (mRecursiveException) {
- STATIC CHAR8 CONST Message[] = "\nRecursive exception occurred while dumping the CPU state\n";
+ STATIC CHAR8 CONST Message[] = "\nRecursive exception occurred while dumping the CPU state\n";
SerialPortWrite ((UINT8 *)Message, sizeof Message - 1);
if (gST->ConOut != NULL) {
AsciiPrint (Message);
}
+
CpuDeadLoop ();
}
+
mRecursiveException = TRUE;
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"\n\n%a Exception at 0x%016lx\n", gExceptionTypeString[ExceptionType], SystemContext.SystemContextAArch64->ELR);
- SerialPortWrite ((UINT8 *) Buffer, CharCount);
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n\n%a Exception at 0x%016lx\n", gExceptionTypeString[ExceptionType], SystemContext.SystemContextAArch64->ELR);
+ SerialPortWrite ((UINT8 *)Buffer, CharCount);
if (gST->ConOut != NULL) {
AsciiPrint (Buffer);
}
DEBUG_CODE_BEGIN ();
- CHAR8 *Pdb, *PrevPdb;
- UINTN ImageBase;
- UINTN PeCoffSizeOfHeader;
- UINT64 *Fp;
- UINT64 RootFp[2];
- UINTN Idx;
+ CHAR8 *Pdb, *PrevPdb;
+ UINTN ImageBase;
+ UINTN PeCoffSizeOfHeader;
+ UINT64 *Fp;
+ UINT64 RootFp[2];
+ UINTN Idx;
+
+ PrevPdb = Pdb = GetImageName (SystemContext.SystemContextAArch64->ELR, &ImageBase, &PeCoffSizeOfHeader);
+ if (Pdb != NULL) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "PC 0x%012lx (0x%012lx+0x%08x) [ 0] %a\n",
+ SystemContext.SystemContextAArch64->ELR,
+ ImageBase,
+ SystemContext.SystemContextAArch64->ELR - ImageBase,
+ BaseName (Pdb)
+ ));
+ } else {
+ DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", SystemContext.SystemContextAArch64->ELR));
+ }
- PrevPdb = Pdb = GetImageName (SystemContext.SystemContextAArch64->ELR, &ImageBase, &PeCoffSizeOfHeader);
- if (Pdb != NULL) {
- DEBUG ((DEBUG_ERROR, "PC 0x%012lx (0x%012lx+0x%08x) [ 0] %a\n",
- SystemContext.SystemContextAArch64->ELR, ImageBase,
- SystemContext.SystemContextAArch64->ELR - ImageBase, BaseName (Pdb)));
- } else {
- DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", SystemContext.SystemContextAArch64->ELR));
- }
+ if ((UINT64 *)SystemContext.SystemContextAArch64->FP != 0) {
+ Idx = 0;
- if ((UINT64 *)SystemContext.SystemContextAArch64->FP != 0) {
- Idx = 0;
+ RootFp[0] = ((UINT64 *)SystemContext.SystemContextAArch64->FP)[0];
+ RootFp[1] = ((UINT64 *)SystemContext.SystemContextAArch64->FP)[1];
+ if (RootFp[1] != SystemContext.SystemContextAArch64->LR) {
+ RootFp[0] = SystemContext.SystemContextAArch64->FP;
+ RootFp[1] = SystemContext.SystemContextAArch64->LR;
+ }
- RootFp[0] = ((UINT64 *)SystemContext.SystemContextAArch64->FP)[0];
- RootFp[1] = ((UINT64 *)SystemContext.SystemContextAArch64->FP)[1];
- if (RootFp[1] != SystemContext.SystemContextAArch64->LR) {
- RootFp[0] = SystemContext.SystemContextAArch64->FP;
- RootFp[1] = SystemContext.SystemContextAArch64->LR;
- }
- for (Fp = RootFp; Fp[0] != 0; Fp = (UINT64 *)Fp[0]) {
- Pdb = GetImageName (Fp[1], &ImageBase, &PeCoffSizeOfHeader);
- if (Pdb != NULL) {
- if (Pdb != PrevPdb) {
- Idx++;
- PrevPdb = Pdb;
- }
- DEBUG ((DEBUG_ERROR, "PC 0x%012lx (0x%012lx+0x%08x) [% 2d] %a\n",
- Fp[1], ImageBase, Fp[1] - ImageBase, Idx, BaseName (Pdb)));
- } else {
- DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", Fp[1]));
- }
- }
- PrevPdb = Pdb = GetImageName (SystemContext.SystemContextAArch64->ELR, &ImageBase, &PeCoffSizeOfHeader);
+ for (Fp = RootFp; Fp[0] != 0; Fp = (UINT64 *)Fp[0]) {
+ Pdb = GetImageName (Fp[1], &ImageBase, &PeCoffSizeOfHeader);
if (Pdb != NULL) {
- DEBUG ((DEBUG_ERROR, "\n[ 0] %a\n", Pdb));
- }
-
- Idx = 0;
- for (Fp = RootFp; Fp[0] != 0; Fp = (UINT64 *)Fp[0]) {
- Pdb = GetImageName (Fp[1], &ImageBase, &PeCoffSizeOfHeader);
- if (Pdb != NULL && Pdb != PrevPdb) {
- DEBUG ((DEBUG_ERROR, "[% 2d] %a\n", ++Idx, Pdb));
+ if (Pdb != PrevPdb) {
+ Idx++;
PrevPdb = Pdb;
}
+
+ DEBUG ((
+ DEBUG_ERROR,
+ "PC 0x%012lx (0x%012lx+0x%08x) [% 2d] %a\n",
+ Fp[1],
+ ImageBase,
+ Fp[1] - ImageBase,
+ Idx,
+ BaseName (Pdb)
+ ));
+ } else {
+ DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", Fp[1]));
+ }
+ }
+
+ PrevPdb = Pdb = GetImageName (SystemContext.SystemContextAArch64->ELR, &ImageBase, &PeCoffSizeOfHeader);
+ if (Pdb != NULL) {
+ DEBUG ((DEBUG_ERROR, "\n[ 0] %a\n", Pdb));
+ }
+
+ Idx = 0;
+ for (Fp = RootFp; Fp[0] != 0; Fp = (UINT64 *)Fp[0]) {
+ Pdb = GetImageName (Fp[1], &ImageBase, &PeCoffSizeOfHeader);
+ if ((Pdb != NULL) && (Pdb != PrevPdb)) {
+ DEBUG ((DEBUG_ERROR, "[% 2d] %a\n", ++Idx, Pdb));
+ PrevPdb = Pdb;
}
}
+ }
+
DEBUG_CODE_END ();
DEBUG ((DEBUG_ERROR, "\n X0 0x%016lx X1 0x%016lx X2 0x%016lx X3 0x%016lx\n", SystemContext.SystemContextAArch64->X0, SystemContext.SystemContextAArch64->X1, SystemContext.SystemContextAArch64->X2, SystemContext.SystemContextAArch64->X3));
@@ -255,19 +312,22 @@ DefaultExceptionHandler ( DEBUG ((DEBUG_ERROR, "\n SP 0x%016lx ELR 0x%016lx SPSR 0x%08lx FPSR 0x%08lx\n ESR 0x%08lx FAR 0x%016lx\n", SystemContext.SystemContextAArch64->SP, SystemContext.SystemContextAArch64->ELR, SystemContext.SystemContextAArch64->SPSR, SystemContext.SystemContextAArch64->FPSR, SystemContext.SystemContextAArch64->ESR, SystemContext.SystemContextAArch64->FAR));
- DEBUG ((DEBUG_ERROR, "\n ESR : EC 0x%02x IL 0x%x ISS 0x%08x\n", (SystemContext.SystemContextAArch64->ESR & 0xFC000000) >> 26, (SystemContext.SystemContextAArch64->ESR >> 25) & 0x1, SystemContext.SystemContextAArch64->ESR & 0x1FFFFFF ));
+ DEBUG ((DEBUG_ERROR, "\n ESR : EC 0x%02x IL 0x%x ISS 0x%08x\n", (SystemContext.SystemContextAArch64->ESR & 0xFC000000) >> 26, (SystemContext.SystemContextAArch64->ESR >> 25) & 0x1, SystemContext.SystemContextAArch64->ESR & 0x1FFFFFF));
DescribeExceptionSyndrome (SystemContext.SystemContextAArch64->ESR);
DEBUG ((DEBUG_ERROR, "\nStack dump:\n"));
for (Offset = -256; Offset < 256; Offset += 32) {
- DEBUG ((DEBUG_ERROR, "%c %013lx: %016lx %016lx %016lx %016lx\n",
+ DEBUG ((
+ DEBUG_ERROR,
+ "%c %013lx: %016lx %016lx %016lx %016lx\n",
Offset == 0 ? '>' : ' ',
SystemContext.SystemContextAArch64->SP + Offset,
*(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset),
*(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset + 8),
*(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset + 16),
- *(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset + 24)));
+ *(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset + 24)
+ ));
}
ASSERT (FALSE);
diff --git a/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c b/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c index 26f552622d..13b321e456 100644 --- a/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c +++ b/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c @@ -27,14 +27,14 @@ // The number of elements in a CHAR8 array, including the terminating NUL, that
// is meant to hold the string rendering of the CPSR.
//
-#define CPSR_STRING_SIZE 32
+#define CPSR_STRING_SIZE 32
typedef struct {
- UINT32 BIT;
- CHAR8 Char;
+ UINT32 BIT;
+ CHAR8 Char;
} CPSR_CHAR;
-STATIC CONST CPSR_CHAR mCpsrChar[] = {
+STATIC CONST CPSR_CHAR mCpsrChar[] = {
{ 31, 'n' },
{ 30, 'z' },
{ 29, 'c' },
@@ -72,9 +72,9 @@ CpsrString ( OUT CHAR8 *ReturnStr
)
{
- UINTN Index;
- CHAR8* Str;
- CHAR8* ModeStr;
+ UINTN Index;
+ CHAR8 *Str;
+ CHAR8 *ModeStr;
Str = ReturnStr;
@@ -87,37 +87,37 @@ CpsrString ( }
*Str++ = '_';
- *Str = '\0';
+ *Str = '\0';
switch (Cpsr & 0x1f) {
- case 0x10:
- ModeStr = "usr";
- break;
- case 0x011:
- ModeStr = "fiq";
- break;
- case 0x12:
- ModeStr = "irq";
- break;
- case 0x13:
- ModeStr = "svc";
- break;
- case 0x16:
- ModeStr = "mon";
- break;
- case 0x17:
- ModeStr = "abt";
- break;
- case 0x1b:
- ModeStr = "und";
- break;
- case 0x1f:
- ModeStr = "sys";
- break;
-
- default:
- ModeStr = "???";
- break;
+ case 0x10:
+ ModeStr = "usr";
+ break;
+ case 0x011:
+ ModeStr = "fiq";
+ break;
+ case 0x12:
+ ModeStr = "irq";
+ break;
+ case 0x13:
+ ModeStr = "svc";
+ break;
+ case 0x16:
+ ModeStr = "mon";
+ break;
+ case 0x17:
+ ModeStr = "abt";
+ break;
+ case 0x1b:
+ ModeStr = "und";
+ break;
+ case 0x1f:
+ ModeStr = "sys";
+ break;
+
+ default:
+ ModeStr = "???";
+ break;
}
//
@@ -131,31 +131,47 @@ FaultStatusToString ( IN UINT32 Status
)
{
- CHAR8 *FaultSource;
+ CHAR8 *FaultSource;
switch (Status) {
- case 0x01: FaultSource = "Alignment fault"; break;
- case 0x02: FaultSource = "Debug event fault"; break;
- case 0x03: FaultSource = "Access Flag fault on Section"; break;
- case 0x04: FaultSource = "Cache maintenance operation fault[2]"; break;
- case 0x05: FaultSource = "Translation fault on Section"; break;
- case 0x06: FaultSource = "Access Flag fault on Page"; break;
- case 0x07: FaultSource = "Translation fault on Page"; break;
- case 0x08: FaultSource = "Precise External Abort"; break;
- case 0x09: FaultSource = "Domain fault on Section"; break;
- case 0x0b: FaultSource = "Domain fault on Page"; break;
- case 0x0c: FaultSource = "External abort on translation, first level"; break;
- case 0x0d: FaultSource = "Permission fault on Section"; break;
- case 0x0e: FaultSource = "External abort on translation, second level"; break;
- case 0x0f: FaultSource = "Permission fault on Page"; break;
- case 0x16: FaultSource = "Imprecise External Abort"; break;
- default: FaultSource = "No function"; break;
- }
+ case 0x01: FaultSource = "Alignment fault";
+ break;
+ case 0x02: FaultSource = "Debug event fault";
+ break;
+ case 0x03: FaultSource = "Access Flag fault on Section";
+ break;
+ case 0x04: FaultSource = "Cache maintenance operation fault[2]";
+ break;
+ case 0x05: FaultSource = "Translation fault on Section";
+ break;
+ case 0x06: FaultSource = "Access Flag fault on Page";
+ break;
+ case 0x07: FaultSource = "Translation fault on Page";
+ break;
+ case 0x08: FaultSource = "Precise External Abort";
+ break;
+ case 0x09: FaultSource = "Domain fault on Section";
+ break;
+ case 0x0b: FaultSource = "Domain fault on Page";
+ break;
+ case 0x0c: FaultSource = "External abort on translation, first level";
+ break;
+ case 0x0d: FaultSource = "Permission fault on Section";
+ break;
+ case 0x0e: FaultSource = "External abort on translation, second level";
+ break;
+ case 0x0f: FaultSource = "Permission fault on Page";
+ break;
+ case 0x16: FaultSource = "Imprecise External Abort";
+ break;
+ default: FaultSource = "No function";
+ break;
+ }
return FaultSource;
}
-STATIC CHAR8 *gExceptionTypeString[] = {
+STATIC CHAR8 *gExceptionTypeString[] = {
"Reset",
"Undefined OpCode",
"SVC",
@@ -178,62 +194,68 @@ STATIC CHAR8 *gExceptionTypeString[] = { **/
VOID
DefaultExceptionHandler (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN OUT EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
)
{
- CHAR8 Buffer[100];
- UINTN CharCount;
- UINT32 DfsrStatus;
- UINT32 IfsrStatus;
- BOOLEAN DfsrWrite;
- UINT32 PcAdjust;
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+ UINT32 DfsrStatus;
+ UINT32 IfsrStatus;
+ BOOLEAN DfsrWrite;
+ UINT32 PcAdjust;
PcAdjust = 0;
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"\n%a Exception PC at 0x%08x CPSR 0x%08x ",
- gExceptionTypeString[ExceptionType], SystemContext.SystemContextArm->PC, SystemContext.SystemContextArm->CPSR);
+ CharCount = AsciiSPrint (
+ Buffer,
+ sizeof (Buffer),
+ "\n%a Exception PC at 0x%08x CPSR 0x%08x ",
+ gExceptionTypeString[ExceptionType],
+ SystemContext.SystemContextArm->PC,
+ SystemContext.SystemContextArm->CPSR
+ );
SerialPortWrite ((UINT8 *)Buffer, CharCount);
if (gST->ConOut != NULL) {
AsciiPrint (Buffer);
}
DEBUG_CODE_BEGIN ();
- CHAR8 *Pdb;
- UINT32 ImageBase;
- UINT32 PeCoffSizeOfHeader;
- UINT32 Offset;
- CHAR8 CpsrStr[CPSR_STRING_SIZE]; // char per bit. Lower 5-bits are mode
+ CHAR8 *Pdb;
+ UINT32 ImageBase;
+ UINT32 PeCoffSizeOfHeader;
+ UINT32 Offset;
+ CHAR8 CpsrStr[CPSR_STRING_SIZE]; // char per bit. Lower 5-bits are mode
// that is a 3 char string
- CHAR8 Buffer[80];
- UINT8 *DisAsm;
- UINT32 ItBlock;
-
- CpsrString (SystemContext.SystemContextArm->CPSR, CpsrStr);
- DEBUG ((DEBUG_ERROR, "%a\n", CpsrStr));
-
- Pdb = GetImageName (SystemContext.SystemContextArm->PC, &ImageBase, &PeCoffSizeOfHeader);
- Offset = SystemContext.SystemContextArm->PC - ImageBase;
- if (Pdb != NULL) {
- DEBUG ((DEBUG_ERROR, "%a\n", Pdb));
-
- //
- // A PE/COFF image loads its headers into memory so the headers are
- // included in the linked addresses. ELF and Mach-O images do not
- // include the headers so the first byte of the image is usually
- // text (code). If you look at link maps from ELF or Mach-O images
- // you need to subtract out the size of the PE/COFF header to get
- // get the offset that matches the link map.
- //
- DEBUG ((DEBUG_ERROR, "loaded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader));
-
- // If we come from an image it is safe to show the instruction. We know it should not fault
- DisAsm = (UINT8 *)(UINTN)SystemContext.SystemContextArm->PC;
- ItBlock = 0;
- DisassembleInstruction (&DisAsm, (SystemContext.SystemContextArm->CPSR & BIT5) == BIT5, TRUE, &ItBlock, Buffer, sizeof (Buffer));
- DEBUG ((DEBUG_ERROR, "\n%a", Buffer));
-
- switch (ExceptionType) {
+ CHAR8 Buffer[80];
+ UINT8 *DisAsm;
+ UINT32 ItBlock;
+
+ CpsrString (SystemContext.SystemContextArm->CPSR, CpsrStr);
+ DEBUG ((DEBUG_ERROR, "%a\n", CpsrStr));
+
+ Pdb = GetImageName (SystemContext.SystemContextArm->PC, &ImageBase, &PeCoffSizeOfHeader);
+ Offset = SystemContext.SystemContextArm->PC - ImageBase;
+ if (Pdb != NULL) {
+ DEBUG ((DEBUG_ERROR, "%a\n", Pdb));
+
+ //
+ // A PE/COFF image loads its headers into memory so the headers are
+ // included in the linked addresses. ELF and Mach-O images do not
+ // include the headers so the first byte of the image is usually
+ // text (code). If you look at link maps from ELF or Mach-O images
+ // you need to subtract out the size of the PE/COFF header to get
+ // get the offset that matches the link map.
+ //
+ DEBUG ((DEBUG_ERROR, "loaded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader));
+
+ // If we come from an image it is safe to show the instruction. We know it should not fault
+ DisAsm = (UINT8 *)(UINTN)SystemContext.SystemContextArm->PC;
+ ItBlock = 0;
+ DisassembleInstruction (&DisAsm, (SystemContext.SystemContextArm->CPSR & BIT5) == BIT5, TRUE, &ItBlock, Buffer, sizeof (Buffer));
+ DEBUG ((DEBUG_ERROR, "\n%a", Buffer));
+
+ switch (ExceptionType) {
case EXCEPT_ARM_UNDEFINED_INSTRUCTION:
case EXCEPT_ARM_SOFTWARE_INTERRUPT:
case EXCEPT_ARM_PREFETCH_ABORT:
@@ -244,9 +266,9 @@ DefaultExceptionHandler ( default:
break;
- }
-
}
+ }
+
DEBUG_CODE_END ();
DEBUG ((DEBUG_ERROR, "\n R0 0x%08x R1 0x%08x R2 0x%08x R3 0x%08x\n", SystemContext.SystemContextArm->R0, SystemContext.SystemContextArm->R1, SystemContext.SystemContextArm->R2, SystemContext.SystemContextArm->R3));
DEBUG ((DEBUG_ERROR, " R4 0x%08x R5 0x%08x R6 0x%08x R7 0x%08x\n", SystemContext.SystemContextArm->R4, SystemContext.SystemContextArm->R5, SystemContext.SystemContextArm->R6, SystemContext.SystemContextArm->R7));
@@ -256,7 +278,7 @@ DefaultExceptionHandler ( // Bit10 is Status[4] Bit3:0 is Status[3:0]
DfsrStatus = (SystemContext.SystemContextArm->DFSR & 0xf) | ((SystemContext.SystemContextArm->DFSR >> 6) & 0x10);
- DfsrWrite = (SystemContext.SystemContextArm->DFSR & BIT11) != 0;
+ DfsrWrite = (SystemContext.SystemContextArm->DFSR & BIT11) != 0;
if (DfsrStatus != 0x00) {
DEBUG ((DEBUG_ERROR, " %a: %a 0x%08x\n", FaultStatusToString (DfsrStatus), DfsrWrite ? "write to" : "read from", SystemContext.SystemContextArm->DFAR));
}
diff --git a/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerUefi.c b/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerUefi.c index e9fea40382..752a763f04 100644 --- a/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerUefi.c +++ b/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerUefi.c @@ -33,11 +33,11 @@ GetImageName ( OUT UINTN *PeCoffSizeOfHeaders
)
{
- EFI_STATUS Status;
- EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *DebugTableHeader;
- EFI_DEBUG_IMAGE_INFO *DebugTable;
- UINTN Entry;
- CHAR8 *Address;
+ EFI_STATUS Status;
+ EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *DebugTableHeader;
+ EFI_DEBUG_IMAGE_INFO *DebugTable;
+ UINTN Entry;
+ CHAR8 *Address;
Status = EfiGetSystemConfigurationTable (&gEfiDebugImageInfoTableGuid, (VOID **)&DebugTableHeader);
if (EFI_ERROR (Status)) {
@@ -53,10 +53,12 @@ GetImageName ( for (Entry = 0; Entry < DebugTableHeader->TableSize; Entry++, DebugTable++) {
if (DebugTable->NormalImage != NULL) {
if ((DebugTable->NormalImage->ImageInfoType == EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL) &&
- (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL)) {
+ (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL))
+ {
if ((Address >= (CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase) &&
- (Address <= ((CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase + DebugTable->NormalImage->LoadedImageProtocolInstance->ImageSize))) {
- *ImageBase = (UINTN)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;
+ (Address <= ((CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase + DebugTable->NormalImage->LoadedImageProtocolInstance->ImageSize)))
+ {
+ *ImageBase = (UINTN)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;
*PeCoffSizeOfHeaders = PeCoffGetSizeOfHeaders ((VOID *)(UINTN)*ImageBase);
return PeCoffLoaderGetPdbPointer (DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase);
}
@@ -66,4 +68,3 @@ GetImageName ( return NULL;
}
-
diff --git a/ArmPkg/Library/LinuxBootBootManagerLib/LinuxBootBm.c b/ArmPkg/Library/LinuxBootBootManagerLib/LinuxBootBm.c index 3295c5a070..5a44af5a75 100644 --- a/ArmPkg/Library/LinuxBootBootManagerLib/LinuxBootBm.c +++ b/ArmPkg/Library/LinuxBootBootManagerLib/LinuxBootBm.c @@ -38,19 +38,19 @@ STATIC
VOID
PlatformRegisterFvBootOption (
- CONST EFI_GUID *FileGuid,
- CHAR16 *Description,
- UINT32 Attributes
+ CONST EFI_GUID *FileGuid,
+ CHAR16 *Description,
+ UINT32 Attributes
)
{
- EFI_STATUS Status;
- INTN OptionIndex;
- EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
- UINTN BootOptionCount;
- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_STATUS Status;
+ INTN OptionIndex;
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
+ UINTN BootOptionCount;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
Status = gBS->HandleProtocol (
gImageHandle,
@@ -96,6 +96,7 @@ PlatformRegisterFvBootOption ( Status = EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN);
ASSERT_EFI_ERROR (Status);
}
+
EfiBootManagerFreeLoadOption (&NewOption);
EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
}
@@ -136,7 +137,7 @@ PlatformBootManagerAfterConsole ( VOID
)
{
- EFI_GUID LinuxBootFileGuid;
+ EFI_GUID LinuxBootFileGuid;
CopyGuid (&LinuxBootFileGuid, PcdGetPtr (PcdLinuxBootFileGuid));
@@ -163,7 +164,7 @@ PlatformBootManagerAfterConsole ( VOID
EFIAPI
PlatformBootManagerWaitCallback (
- UINT16 TimeoutRemain
+ UINT16 TimeoutRemain
)
{
return;
diff --git a/ArmPkg/Library/OpteeLib/Optee.c b/ArmPkg/Library/OpteeLib/Optee.c index bedb2edbb3..48e33cb3d5 100644 --- a/ArmPkg/Library/OpteeLib/Optee.c +++ b/ArmPkg/Library/OpteeLib/Optee.c @@ -20,7 +20,7 @@ #include <OpteeSmc.h>
#include <Uefi.h>
-STATIC OPTEE_SHARED_MEMORY_INFORMATION OpteeSharedMemoryInformation = { 0 };
+STATIC OPTEE_SHARED_MEMORY_INFORMATION OpteeSharedMemoryInformation = { 0 };
/**
Check for OP-TEE presence.
@@ -31,7 +31,7 @@ IsOpteePresent ( VOID
)
{
- ARM_SMC_ARGS ArmSmcArgs;
+ ARM_SMC_ARGS ArmSmcArgs;
ZeroMem (&ArmSmcArgs, sizeof (ARM_SMC_ARGS));
// Send a Trusted OS Calls UID command
@@ -41,7 +41,8 @@ IsOpteePresent ( if ((ArmSmcArgs.Arg0 == OPTEE_OS_UID0) &&
(ArmSmcArgs.Arg1 == OPTEE_OS_UID1) &&
(ArmSmcArgs.Arg2 == OPTEE_OS_UID2) &&
- (ArmSmcArgs.Arg3 == OPTEE_OS_UID3)) {
+ (ArmSmcArgs.Arg3 == OPTEE_OS_UID3))
+ {
return TRUE;
} else {
return FALSE;
@@ -54,12 +55,12 @@ OpteeSharedMemoryRemap ( VOID
)
{
- ARM_SMC_ARGS ArmSmcArgs;
- EFI_PHYSICAL_ADDRESS PhysicalAddress;
- EFI_PHYSICAL_ADDRESS Start;
- EFI_PHYSICAL_ADDRESS End;
- EFI_STATUS Status;
- UINTN Size;
+ ARM_SMC_ARGS ArmSmcArgs;
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;
+ EFI_PHYSICAL_ADDRESS Start;
+ EFI_PHYSICAL_ADDRESS End;
+ EFI_STATUS Status;
+ UINTN Size;
ZeroMem (&ArmSmcArgs, sizeof (ARM_SMC_ARGS));
ArmSmcArgs.Arg0 = OPTEE_SMC_GET_SHARED_MEMORY_CONFIG;
@@ -75,10 +76,10 @@ OpteeSharedMemoryRemap ( return EFI_UNSUPPORTED;
}
- Start = (ArmSmcArgs.Arg1 + SIZE_4KB - 1) & ~(SIZE_4KB - 1);
- End = (ArmSmcArgs.Arg1 + ArmSmcArgs.Arg2) & ~(SIZE_4KB - 1);
+ Start = (ArmSmcArgs.Arg1 + SIZE_4KB - 1) & ~(SIZE_4KB - 1);
+ End = (ArmSmcArgs.Arg1 + ArmSmcArgs.Arg2) & ~(SIZE_4KB - 1);
PhysicalAddress = Start;
- Size = End - Start;
+ Size = End - Start;
if (Size < SIZE_4KB) {
DEBUG ((DEBUG_WARN, "OP-TEE shared memory too small\n"));
@@ -102,7 +103,7 @@ OpteeInit ( VOID
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
if (!IsOpteePresent ()) {
DEBUG ((DEBUG_WARN, "OP-TEE not present\n"));
@@ -121,7 +122,7 @@ OpteeInit ( STATIC
BOOLEAN
IsOpteeSmcReturnRpc (
- UINT32 Return
+ UINT32 Return
)
{
return (Return != OPTEE_SMC_RETURN_UNKNOWN_FUNCTION) &&
@@ -140,10 +141,10 @@ IsOpteeSmcReturnRpc ( STATIC
UINT32
OpteeCallWithArg (
- IN UINT64 PhysicalArg
+ IN UINT64 PhysicalArg
)
{
- ARM_SMC_ARGS ArmSmcArgs;
+ ARM_SMC_ARGS ArmSmcArgs;
ZeroMem (&ArmSmcArgs, sizeof (ARM_SMC_ARGS));
ArmSmcArgs.Arg0 = OPTEE_SMC_CALL_WITH_ARG;
@@ -155,18 +156,18 @@ OpteeCallWithArg ( if (IsOpteeSmcReturnRpc (ArmSmcArgs.Arg0)) {
switch (ArmSmcArgs.Arg0) {
- case OPTEE_SMC_RETURN_RPC_FOREIGN_INTERRUPT:
- //
- // A foreign interrupt was raised while secure world was
- // executing, since they are handled in UEFI a dummy RPC is
- // performed to let UEFI take the interrupt through the normal
- // vector.
- //
- break;
-
- default:
- // Do nothing in case RPC is not implemented.
- break;
+ case OPTEE_SMC_RETURN_RPC_FOREIGN_INTERRUPT:
+ //
+ // A foreign interrupt was raised while secure world was
+ // executing, since they are handled in UEFI a dummy RPC is
+ // performed to let UEFI take the interrupt through the normal
+ // vector.
+ //
+ break;
+
+ default:
+ // Do nothing in case RPC is not implemented.
+ break;
}
ArmSmcArgs.Arg0 = OPTEE_SMC_RETURN_FROM_RPC;
@@ -181,8 +182,8 @@ OpteeCallWithArg ( STATIC
VOID
EfiGuidToRfc4122Uuid (
- OUT RFC4122_UUID *Rfc4122Uuid,
- IN EFI_GUID *Guid
+ OUT RFC4122_UUID *Rfc4122Uuid,
+ IN EFI_GUID *Guid
)
{
Rfc4122Uuid->Data1 = SwapBytes32 (Guid->Data1);
@@ -194,10 +195,10 @@ EfiGuidToRfc4122Uuid ( EFI_STATUS
EFIAPI
OpteeOpenSession (
- IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg
+ IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg
)
{
- OPTEE_MESSAGE_ARG *MessageArg;
+ OPTEE_MESSAGE_ARG *MessageArg;
MessageArg = NULL;
@@ -229,12 +230,12 @@ OpteeOpenSession ( MessageArg->NumParams = 2;
if (OpteeCallWithArg ((UINTN)MessageArg) != 0) {
- MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
+ MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
MessageArg->ReturnOrigin = OPTEE_ORIGIN_COMMUNICATION;
}
- OpenSessionArg->Session = MessageArg->Session;
- OpenSessionArg->Return = MessageArg->Return;
+ OpenSessionArg->Session = MessageArg->Session;
+ OpenSessionArg->Return = MessageArg->Return;
OpenSessionArg->ReturnOrigin = MessageArg->ReturnOrigin;
return EFI_SUCCESS;
@@ -243,10 +244,10 @@ OpteeOpenSession ( EFI_STATUS
EFIAPI
OpteeCloseSession (
- IN UINT32 Session
+ IN UINT32 Session
)
{
- OPTEE_MESSAGE_ARG *MessageArg;
+ OPTEE_MESSAGE_ARG *MessageArg;
MessageArg = NULL;
@@ -269,70 +270,70 @@ OpteeCloseSession ( STATIC
EFI_STATUS
OpteeToMessageParam (
- OUT OPTEE_MESSAGE_PARAM *MessageParams,
- IN UINT32 NumParams,
- IN OPTEE_MESSAGE_PARAM *InParams
+ OUT OPTEE_MESSAGE_PARAM *MessageParams,
+ IN UINT32 NumParams,
+ IN OPTEE_MESSAGE_PARAM *InParams
)
{
- UINT32 Idx;
- UINTN ParamSharedMemoryAddress;
- UINTN SharedMemorySize;
- UINTN Size;
+ UINT32 Idx;
+ UINTN ParamSharedMemoryAddress;
+ UINTN SharedMemorySize;
+ UINTN Size;
Size = (sizeof (OPTEE_MESSAGE_ARG) + sizeof (UINT64) - 1) &
- ~(sizeof (UINT64) - 1);
+ ~(sizeof (UINT64) - 1);
ParamSharedMemoryAddress = OpteeSharedMemoryInformation.Base + Size;
- SharedMemorySize = OpteeSharedMemoryInformation.Size - Size;
+ SharedMemorySize = OpteeSharedMemoryInformation.Size - Size;
for (Idx = 0; Idx < NumParams; Idx++) {
- CONST OPTEE_MESSAGE_PARAM *InParam;
- OPTEE_MESSAGE_PARAM *MessageParam;
- UINT32 Attribute;
+ CONST OPTEE_MESSAGE_PARAM *InParam;
+ OPTEE_MESSAGE_PARAM *MessageParam;
+ UINT32 Attribute;
- InParam = InParams + Idx;
+ InParam = InParams + Idx;
MessageParam = MessageParams + Idx;
- Attribute = InParam->Attribute & OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK;
+ Attribute = InParam->Attribute & OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK;
switch (Attribute) {
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE:
- MessageParam->Attribute = OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE;
- ZeroMem (&MessageParam->Union, sizeof (MessageParam->Union));
- break;
-
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT:
- MessageParam->Attribute = Attribute;
- MessageParam->Union.Value.A = InParam->Union.Value.A;
- MessageParam->Union.Value.B = InParam->Union.Value.B;
- MessageParam->Union.Value.C = InParam->Union.Value.C;
- break;
-
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT:
- MessageParam->Attribute = Attribute;
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE:
+ MessageParam->Attribute = OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE;
+ ZeroMem (&MessageParam->Union, sizeof (MessageParam->Union));
+ break;
- if (InParam->Union.Memory.Size > SharedMemorySize) {
- return EFI_OUT_OF_RESOURCES;
- }
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT:
+ MessageParam->Attribute = Attribute;
+ MessageParam->Union.Value.A = InParam->Union.Value.A;
+ MessageParam->Union.Value.B = InParam->Union.Value.B;
+ MessageParam->Union.Value.C = InParam->Union.Value.C;
+ break;
- CopyMem (
- (VOID *)ParamSharedMemoryAddress,
- (VOID *)(UINTN)InParam->Union.Memory.BufferAddress,
- InParam->Union.Memory.Size
- );
- MessageParam->Union.Memory.BufferAddress = (UINT64)ParamSharedMemoryAddress;
- MessageParam->Union.Memory.Size = InParam->Union.Memory.Size;
-
- Size = (InParam->Union.Memory.Size + sizeof (UINT64) - 1) &
- ~(sizeof (UINT64) - 1);
- ParamSharedMemoryAddress += Size;
- SharedMemorySize -= Size;
- break;
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT:
+ MessageParam->Attribute = Attribute;
+
+ if (InParam->Union.Memory.Size > SharedMemorySize) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ CopyMem (
+ (VOID *)ParamSharedMemoryAddress,
+ (VOID *)(UINTN)InParam->Union.Memory.BufferAddress,
+ InParam->Union.Memory.Size
+ );
+ MessageParam->Union.Memory.BufferAddress = (UINT64)ParamSharedMemoryAddress;
+ MessageParam->Union.Memory.Size = InParam->Union.Memory.Size;
+
+ Size = (InParam->Union.Memory.Size + sizeof (UINT64) - 1) &
+ ~(sizeof (UINT64) - 1);
+ ParamSharedMemoryAddress += Size;
+ SharedMemorySize -= Size;
+ break;
- default:
- return EFI_INVALID_PARAMETER;
+ default:
+ return EFI_INVALID_PARAMETER;
}
}
@@ -342,56 +343,56 @@ OpteeToMessageParam ( STATIC
EFI_STATUS
OpteeFromMessageParam (
- OUT OPTEE_MESSAGE_PARAM *OutParams,
- IN UINT32 NumParams,
- IN OPTEE_MESSAGE_PARAM *MessageParams
+ OUT OPTEE_MESSAGE_PARAM *OutParams,
+ IN UINT32 NumParams,
+ IN OPTEE_MESSAGE_PARAM *MessageParams
)
{
- UINT32 Idx;
+ UINT32 Idx;
for (Idx = 0; Idx < NumParams; Idx++) {
- OPTEE_MESSAGE_PARAM *OutParam;
- CONST OPTEE_MESSAGE_PARAM *MessageParam;
- UINT32 Attribute;
+ OPTEE_MESSAGE_PARAM *OutParam;
+ CONST OPTEE_MESSAGE_PARAM *MessageParam;
+ UINT32 Attribute;
- OutParam = OutParams + Idx;
+ OutParam = OutParams + Idx;
MessageParam = MessageParams + Idx;
- Attribute = MessageParam->Attribute & OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK;
+ Attribute = MessageParam->Attribute & OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK;
switch (Attribute) {
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE:
- OutParam->Attribute = OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE;
- ZeroMem (&OutParam->Union, sizeof (OutParam->Union));
- break;
-
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT:
- OutParam->Attribute = Attribute;
- OutParam->Union.Value.A = MessageParam->Union.Value.A;
- OutParam->Union.Value.B = MessageParam->Union.Value.B;
- OutParam->Union.Value.C = MessageParam->Union.Value.C;
- break;
-
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT:
- OutParam->Attribute = Attribute;
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE:
+ OutParam->Attribute = OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE;
+ ZeroMem (&OutParam->Union, sizeof (OutParam->Union));
+ break;
- if (MessageParam->Union.Memory.Size > OutParam->Union.Memory.Size) {
- return EFI_BAD_BUFFER_SIZE;
- }
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT:
+ OutParam->Attribute = Attribute;
+ OutParam->Union.Value.A = MessageParam->Union.Value.A;
+ OutParam->Union.Value.B = MessageParam->Union.Value.B;
+ OutParam->Union.Value.C = MessageParam->Union.Value.C;
+ break;
- CopyMem (
- (VOID *)(UINTN)OutParam->Union.Memory.BufferAddress,
- (VOID *)(UINTN)MessageParam->Union.Memory.BufferAddress,
- MessageParam->Union.Memory.Size
- );
- OutParam->Union.Memory.Size = MessageParam->Union.Memory.Size;
- break;
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT:
+ OutParam->Attribute = Attribute;
+
+ if (MessageParam->Union.Memory.Size > OutParam->Union.Memory.Size) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ CopyMem (
+ (VOID *)(UINTN)OutParam->Union.Memory.BufferAddress,
+ (VOID *)(UINTN)MessageParam->Union.Memory.BufferAddress,
+ MessageParam->Union.Memory.Size
+ );
+ OutParam->Union.Memory.Size = MessageParam->Union.Memory.Size;
+ break;
- default:
- return EFI_INVALID_PARAMETER;
+ default:
+ return EFI_INVALID_PARAMETER;
}
}
@@ -401,11 +402,11 @@ OpteeFromMessageParam ( EFI_STATUS
EFIAPI
OpteeInvokeFunction (
- IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
+ IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
)
{
- EFI_STATUS Status;
- OPTEE_MESSAGE_ARG *MessageArg;
+ EFI_STATUS Status;
+ OPTEE_MESSAGE_ARG *MessageArg;
MessageArg = NULL;
@@ -417,9 +418,9 @@ OpteeInvokeFunction ( MessageArg = (OPTEE_MESSAGE_ARG *)OpteeSharedMemoryInformation.Base;
ZeroMem (MessageArg, sizeof (OPTEE_MESSAGE_ARG));
- MessageArg->Command = OPTEE_MESSAGE_COMMAND_INVOKE_FUNCTION;
+ MessageArg->Command = OPTEE_MESSAGE_COMMAND_INVOKE_FUNCTION;
MessageArg->Function = InvokeFunctionArg->Function;
- MessageArg->Session = InvokeFunctionArg->Session;
+ MessageArg->Session = InvokeFunctionArg->Session;
Status = OpteeToMessageParam (
MessageArg->Params,
@@ -433,7 +434,7 @@ OpteeInvokeFunction ( MessageArg->NumParams = OPTEE_MAX_CALL_PARAMS;
if (OpteeCallWithArg ((UINTN)MessageArg) != 0) {
- MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
+ MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
MessageArg->ReturnOrigin = OPTEE_ORIGIN_COMMUNICATION;
}
@@ -441,12 +442,13 @@ OpteeInvokeFunction ( InvokeFunctionArg->Params,
OPTEE_MAX_CALL_PARAMS,
MessageArg->Params
- ) != 0) {
- MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
+ ) != 0)
+ {
+ MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
MessageArg->ReturnOrigin = OPTEE_ORIGIN_COMMUNICATION;
}
- InvokeFunctionArg->Return = MessageArg->Return;
+ InvokeFunctionArg->Return = MessageArg->Return;
InvokeFunctionArg->ReturnOrigin = MessageArg->ReturnOrigin;
return EFI_SUCCESS;
diff --git a/ArmPkg/Library/OpteeLib/OpteeSmc.h b/ArmPkg/Library/OpteeLib/OpteeSmc.h index b760ec8f82..ff4b4b020f 100644 --- a/ArmPkg/Library/OpteeLib/OpteeSmc.h +++ b/ArmPkg/Library/OpteeLib/OpteeSmc.h @@ -11,26 +11,26 @@ #define OPTEE_SMC_H_
/* Returned in Arg0 only from Trusted OS functions */
-#define OPTEE_SMC_RETURN_OK 0x0
+#define OPTEE_SMC_RETURN_OK 0x0
-#define OPTEE_SMC_RETURN_FROM_RPC 0x32000003
-#define OPTEE_SMC_CALL_WITH_ARG 0x32000004
-#define OPTEE_SMC_GET_SHARED_MEMORY_CONFIG 0xb2000007
+#define OPTEE_SMC_RETURN_FROM_RPC 0x32000003
+#define OPTEE_SMC_CALL_WITH_ARG 0x32000004
+#define OPTEE_SMC_GET_SHARED_MEMORY_CONFIG 0xb2000007
-#define OPTEE_SMC_SHARED_MEMORY_CACHED 1
+#define OPTEE_SMC_SHARED_MEMORY_CACHED 1
#define OPTEE_SMC_RETURN_UNKNOWN_FUNCTION 0xffffffff
#define OPTEE_SMC_RETURN_RPC_PREFIX_MASK 0xffff0000
#define OPTEE_SMC_RETURN_RPC_PREFIX 0xffff0000
#define OPTEE_SMC_RETURN_RPC_FOREIGN_INTERRUPT 0xffff0004
-#define OPTEE_MESSAGE_COMMAND_OPEN_SESSION 0
-#define OPTEE_MESSAGE_COMMAND_INVOKE_FUNCTION 1
-#define OPTEE_MESSAGE_COMMAND_CLOSE_SESSION 2
+#define OPTEE_MESSAGE_COMMAND_OPEN_SESSION 0
+#define OPTEE_MESSAGE_COMMAND_INVOKE_FUNCTION 1
+#define OPTEE_MESSAGE_COMMAND_CLOSE_SESSION 2
-#define OPTEE_MESSAGE_ATTRIBUTE_META 0x100
+#define OPTEE_MESSAGE_ATTRIBUTE_META 0x100
-#define OPTEE_LOGIN_PUBLIC 0x0
+#define OPTEE_LOGIN_PUBLIC 0x0
typedef struct {
UINTN Base;
@@ -41,10 +41,10 @@ typedef struct { // UUID struct compliant with RFC4122 (network byte order).
//
typedef struct {
- UINT32 Data1;
- UINT16 Data2;
- UINT16 Data3;
- UINT8 Data4[8];
+ UINT32 Data1;
+ UINT16 Data2;
+ UINT16 Data3;
+ UINT8 Data4[8];
} RFC4122_UUID;
#endif // OPTEE_SMC_H_
diff --git a/ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c b/ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c index 67cbc46e5c..bc6841b892 100644 --- a/ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c +++ b/ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c @@ -28,10 +28,10 @@ VOID
EFIAPI
SetPeiServicesTablePointer (
- IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
+ IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer
)
{
- ArmWriteTpidrurw((UINTN)PeiServicesTablePointer);
+ ArmWriteTpidrurw ((UINTN)PeiServicesTablePointer);
}
/**
@@ -52,7 +52,7 @@ GetPeiServicesTablePointer ( VOID
)
{
- return (CONST EFI_PEI_SERVICES **)ArmReadTpidrurw();
+ return (CONST EFI_PEI_SERVICES **)ArmReadTpidrurw ();
}
/**
@@ -71,9 +71,9 @@ migration actions are required for Itanium or ARM CPUs. **/
VOID
EFIAPI
-MigratePeiServicesTablePointer(
-VOID
-)
+MigratePeiServicesTablePointer (
+ VOID
+ )
{
return;
}
diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c index 097df3e9e4..2fb1a4aa4f 100644 --- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c +++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c @@ -37,23 +37,23 @@ #include "PlatformBm.h"
-#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) }
+#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) }
#pragma pack (1)
typedef struct {
- VENDOR_DEVICE_PATH SerialDxe;
- UART_DEVICE_PATH Uart;
- VENDOR_DEFINED_DEVICE_PATH TermType;
- EFI_DEVICE_PATH_PROTOCOL End;
+ VENDOR_DEVICE_PATH SerialDxe;
+ UART_DEVICE_PATH Uart;
+ VENDOR_DEFINED_DEVICE_PATH TermType;
+ EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_SERIAL_CONSOLE;
#pragma pack ()
-STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {
+STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {
//
// VENDOR_DEVICE_PATH SerialDxe
//
{
- { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },
EDKII_SERIAL_PORT_LIB_VENDOR_GUID
},
@@ -61,7 +61,7 @@ STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = { // UART_DEVICE_PATH Uart
//
{
- { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },
+ { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },
0, // Reserved
FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits
@@ -91,15 +91,14 @@ STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = { }
};
-
#pragma pack (1)
typedef struct {
- USB_CLASS_DEVICE_PATH Keyboard;
- EFI_DEVICE_PATH_PROTOCOL End;
+ USB_CLASS_DEVICE_PATH Keyboard;
+ EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_USB_KEYBOARD;
#pragma pack ()
-STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {
+STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {
//
// USB_CLASS_DEVICE_PATH Keyboard
//
@@ -124,7 +123,6 @@ STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = { }
};
-
/**
Check if the handle satisfies a particular condition.
@@ -138,12 +136,11 @@ STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = { **/
typedef
BOOLEAN
-(EFIAPI *FILTER_FUNCTION) (
+(EFIAPI *FILTER_FUNCTION)(
IN EFI_HANDLE Handle,
IN CONST CHAR16 *ReportText
);
-
/**
Process a handle.
@@ -153,7 +150,7 @@ BOOLEAN **/
typedef
VOID
-(EFIAPI *CALLBACK_FUNCTION) (
+(EFIAPI *CALLBACK_FUNCTION)(
IN EFI_HANDLE Handle,
IN CONST CHAR16 *ReportText
);
@@ -174,31 +171,41 @@ VOID STATIC
VOID
FilterAndProcess (
- IN EFI_GUID *ProtocolGuid,
- IN FILTER_FUNCTION Filter OPTIONAL,
- IN CALLBACK_FUNCTION Process
+ IN EFI_GUID *ProtocolGuid,
+ IN FILTER_FUNCTION Filter OPTIONAL,
+ IN CALLBACK_FUNCTION Process
)
{
- EFI_STATUS Status;
- EFI_HANDLE *Handles;
- UINTN NoHandles;
- UINTN Idx;
-
- Status = gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid,
- NULL /* SearchKey */, &NoHandles, &Handles);
+ EFI_STATUS Status;
+ EFI_HANDLE *Handles;
+ UINTN NoHandles;
+ UINTN Idx;
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ ProtocolGuid,
+ NULL /* SearchKey */,
+ &NoHandles,
+ &Handles
+ );
if (EFI_ERROR (Status)) {
//
// This is not an error, just an informative condition.
//
- DEBUG ((DEBUG_VERBOSE, "%a: %g: %r\n", __FUNCTION__, ProtocolGuid,
- Status));
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a: %g: %r\n",
+ __FUNCTION__,
+ ProtocolGuid,
+ Status
+ ));
return;
}
ASSERT (NoHandles > 0);
for (Idx = 0; Idx < NoHandles; ++Idx) {
- CHAR16 *DevicePathText;
- STATIC CHAR16 Fallback[] = L"<device path unavailable>";
+ CHAR16 *DevicePathText;
+ STATIC CHAR16 Fallback[] = L"<device path unavailable>";
//
// The ConvertDevicePathToText() function handles NULL input transparently.
@@ -212,7 +219,7 @@ FilterAndProcess ( DevicePathText = Fallback;
}
- if (Filter == NULL || Filter (Handles[Idx], DevicePathText)) {
+ if ((Filter == NULL) || Filter (Handles[Idx], DevicePathText)) {
Process (Handles[Idx], DevicePathText);
}
@@ -220,10 +227,10 @@ FilterAndProcess ( FreePool (DevicePathText);
}
}
+
gBS->FreePool (Handles);
}
-
/**
This FILTER_FUNCTION checks if a handle corresponds to a PCI display device.
**/
@@ -231,16 +238,19 @@ STATIC BOOLEAN
EFIAPI
IsPciDisplay (
- IN EFI_HANDLE Handle,
- IN CONST CHAR16 *ReportText
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- PCI_TYPE00 Pci;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 Pci;
- Status = gBS->HandleProtocol (Handle, &gEfiPciIoProtocolGuid,
- (VOID**)&PciIo);
+ Status = gBS->HandleProtocol (
+ Handle,
+ &gEfiPciIoProtocolGuid,
+ (VOID **)&PciIo
+ );
if (EFI_ERROR (Status)) {
//
// This is not an error worth reporting.
@@ -248,8 +258,13 @@ IsPciDisplay ( return FALSE;
}
- Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0 /* Offset */,
- sizeof Pci / sizeof (UINT32), &Pci);
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0 /* Offset */,
+ sizeof Pci / sizeof (UINT32),
+ &Pci
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status));
return FALSE;
@@ -258,7 +273,6 @@ IsPciDisplay ( return IS_PCI_DISPLAY (&Pci);
}
-
/**
This FILTER_FUNCTION checks if a handle corresponds to a non-discoverable
USB host controller.
@@ -267,29 +281,32 @@ STATIC BOOLEAN
EFIAPI
IsUsbHost (
- IN EFI_HANDLE Handle,
- IN CONST CHAR16 *ReportText
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
)
{
- NON_DISCOVERABLE_DEVICE *Device;
- EFI_STATUS Status;
+ NON_DISCOVERABLE_DEVICE *Device;
+ EFI_STATUS Status;
- Status = gBS->HandleProtocol (Handle,
+ Status = gBS->HandleProtocol (
+ Handle,
&gEdkiiNonDiscoverableDeviceProtocolGuid,
- (VOID **)&Device);
+ (VOID **)&Device
+ );
if (EFI_ERROR (Status)) {
return FALSE;
}
if (CompareGuid (Device->Type, &gEdkiiNonDiscoverableUhciDeviceGuid) ||
CompareGuid (Device->Type, &gEdkiiNonDiscoverableEhciDeviceGuid) ||
- CompareGuid (Device->Type, &gEdkiiNonDiscoverableXhciDeviceGuid)) {
+ CompareGuid (Device->Type, &gEdkiiNonDiscoverableXhciDeviceGuid))
+ {
return TRUE;
}
+
return FALSE;
}
-
/**
This CALLBACK_FUNCTION attempts to connect a handle non-recursively, asking
the matching driver to produce all first-level child handles.
@@ -298,11 +315,11 @@ STATIC VOID
EFIAPI
Connect (
- IN EFI_HANDLE Handle,
- IN CONST CHAR16 *ReportText
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = gBS->ConnectController (
Handle, // ControllerHandle
@@ -310,11 +327,15 @@ Connect ( NULL, // RemainingDevicePath -- produce all children
FALSE // Recursive
);
- DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, "%a: %s: %r\n",
- __FUNCTION__, ReportText, Status));
+ DEBUG ((
+ EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
+ "%a: %s: %r\n",
+ __FUNCTION__,
+ ReportText,
+ Status
+ ));
}
-
/**
This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the
handle, and adds it to ConOut and ErrOut.
@@ -323,60 +344,79 @@ STATIC VOID
EFIAPI
AddOutput (
- IN EFI_HANDLE Handle,
- IN CONST CHAR16 *ReportText
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
)
{
- EFI_STATUS Status;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
DevicePath = DevicePathFromHandle (Handle);
if (DevicePath == NULL) {
- DEBUG ((DEBUG_ERROR, "%a: %s: handle %p: device path not found\n",
- __FUNCTION__, ReportText, Handle));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %s: handle %p: device path not found\n",
+ __FUNCTION__,
+ ReportText,
+ Handle
+ ));
return;
}
Status = EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: %s: adding to ConOut: %r\n", __FUNCTION__,
- ReportText, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %s: adding to ConOut: %r\n",
+ __FUNCTION__,
+ ReportText,
+ Status
+ ));
return;
}
Status = EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: %s: adding to ErrOut: %r\n", __FUNCTION__,
- ReportText, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %s: adding to ErrOut: %r\n",
+ __FUNCTION__,
+ ReportText,
+ Status
+ ));
return;
}
- DEBUG ((DEBUG_VERBOSE, "%a: %s: added to ConOut and ErrOut\n", __FUNCTION__,
- ReportText));
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a: %s: added to ConOut and ErrOut\n",
+ __FUNCTION__,
+ ReportText
+ ));
}
STATIC
VOID
PlatformRegisterFvBootOption (
- CONST EFI_GUID *FileGuid,
- CHAR16 *Description,
- UINT32 Attributes,
- EFI_INPUT_KEY *Key
+ CONST EFI_GUID *FileGuid,
+ CHAR16 *Description,
+ UINT32 Attributes,
+ EFI_INPUT_KEY *Key
)
{
- EFI_STATUS Status;
- INTN OptionIndex;
- EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
- UINTN BootOptionCount;
- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_STATUS Status;
+ INTN OptionIndex;
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
+ UINTN BootOptionCount;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
Status = gBS->HandleProtocol (
gImageHandle,
&gEfiLoadedImageProtocolGuid,
- (VOID **) &LoadedImage
+ (VOID **)&LoadedImage
);
ASSERT_EFI_ERROR (Status);
@@ -385,7 +425,7 @@ PlatformRegisterFvBootOption ( ASSERT (DevicePath != NULL);
DevicePath = AppendDevicePathNode (
DevicePath,
- (EFI_DEVICE_PATH_PROTOCOL *) &FileNode
+ (EFI_DEVICE_PATH_PROTOCOL *)&FileNode
);
ASSERT (DevicePath != NULL);
@@ -403,25 +443,33 @@ PlatformRegisterFvBootOption ( FreePool (DevicePath);
BootOptions = EfiBootManagerGetLoadOptions (
- &BootOptionCount, LoadOptionTypeBoot
+ &BootOptionCount,
+ LoadOptionTypeBoot
);
OptionIndex = EfiBootManagerFindLoadOption (
- &NewOption, BootOptions, BootOptionCount
+ &NewOption,
+ BootOptions,
+ BootOptionCount
);
if (OptionIndex == -1) {
Status = EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN);
ASSERT_EFI_ERROR (Status);
- Status = EfiBootManagerAddKeyOptionVariable (NULL,
- (UINT16)NewOption.OptionNumber, 0, Key, NULL);
+ Status = EfiBootManagerAddKeyOptionVariable (
+ NULL,
+ (UINT16)NewOption.OptionNumber,
+ 0,
+ Key,
+ NULL
+ );
ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);
}
+
EfiBootManagerFreeLoadOption (&NewOption);
EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
}
-
STATIC
VOID
GetPlatformOptions (
@@ -437,11 +485,15 @@ GetPlatformOptions ( UINTN Index;
UINTN BootCount;
- Status = gBS->LocateProtocol (&gPlatformBootManagerProtocolGuid, NULL,
- (VOID **)&PlatformBootManager);
+ Status = gBS->LocateProtocol (
+ &gPlatformBootManagerProtocolGuid,
+ NULL,
+ (VOID **)&PlatformBootManager
+ );
if (EFI_ERROR (Status)) {
return;
}
+
Status = PlatformBootManager->GetPlatformBootOptionsAndKeys (
&BootCount,
&BootOptions,
@@ -450,6 +502,7 @@ GetPlatformOptions ( if (EFI_ERROR (Status)) {
return;
}
+
//
// Fetch the existent boot options. If there are none, CurrentBootCount
// will be zeroed.
@@ -462,8 +515,8 @@ GetPlatformOptions ( // Process the platform boot options.
//
for (Index = 0; Index < BootCount; Index++) {
- INTN Match;
- UINTN BootOptionNumber;
+ INTN Match;
+ UINTN BootOptionNumber;
//
// If there are any preexistent boot options, and the subject platform boot
@@ -491,10 +544,16 @@ GetPlatformOptions ( MAX_UINTN
);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: failed to register \"%s\": %r\n",
- __FUNCTION__, BootOptions[Index].Description, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: failed to register \"%s\": %r\n",
+ __FUNCTION__,
+ BootOptions[Index].Description,
+ Status
+ ));
continue;
}
+
BootOptionNumber = BootOptions[Index].OptionNumber;
}
@@ -513,10 +572,16 @@ GetPlatformOptions ( NULL
);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: failed to register hotkey for \"%s\": %r\n",
- __FUNCTION__, BootOptions[Index].Description, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: failed to register hotkey for \"%s\": %r\n",
+ __FUNCTION__,
+ BootOptions[Index].Description,
+ Status
+ ));
}
}
+
EfiBootManagerFreeLoadOptions (CurrentBootOptions, CurrentBootOptionCount);
EfiBootManagerFreeLoadOptions (BootOptions, BootCount);
FreePool (BootKeys);
@@ -528,11 +593,11 @@ PlatformRegisterOptionsAndKeys ( VOID
)
{
- EFI_STATUS Status;
- EFI_INPUT_KEY Enter;
- EFI_INPUT_KEY F2;
- EFI_INPUT_KEY Esc;
- EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
+ EFI_STATUS Status;
+ EFI_INPUT_KEY Enter;
+ EFI_INPUT_KEY F2;
+ EFI_INPUT_KEY Esc;
+ EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
GetPlatformOptions ();
@@ -541,7 +606,7 @@ PlatformRegisterOptionsAndKeys ( //
Enter.ScanCode = SCAN_NULL;
Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;
- Status = EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);
+ Status = EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);
ASSERT_EFI_ERROR (Status);
//
@@ -551,22 +616,30 @@ PlatformRegisterOptionsAndKeys ( F2.UnicodeChar = CHAR_NULL;
Esc.ScanCode = SCAN_ESC;
Esc.UnicodeChar = CHAR_NULL;
- Status = EfiBootManagerGetBootManagerMenu (&BootOption);
+ Status = EfiBootManagerGetBootManagerMenu (&BootOption);
ASSERT_EFI_ERROR (Status);
Status = EfiBootManagerAddKeyOptionVariable (
- NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL
+ NULL,
+ (UINT16)BootOption.OptionNumber,
+ 0,
+ &F2,
+ NULL
);
ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);
Status = EfiBootManagerAddKeyOptionVariable (
- NULL, (UINT16) BootOption.OptionNumber, 0, &Esc, NULL
+ NULL,
+ (UINT16)BootOption.OptionNumber,
+ 0,
+ &Esc,
+ NULL
);
ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);
}
-
//
// BDS Platform Functions
//
+
/**
Do the platform init, can be customized by OEM/IBV
Possible things that can be done in PlatformBootManagerBeforeConsole:
@@ -626,27 +699,45 @@ PlatformBootManagerBeforeConsole ( //
// Add the hardcoded short-form USB keyboard device path to ConIn.
//
- EfiBootManagerUpdateConsoleVariable (ConIn,
- (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, NULL);
+ EfiBootManagerUpdateConsoleVariable (
+ ConIn,
+ (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard,
+ NULL
+ );
//
// Add the hardcoded serial console device path to ConIn, ConOut, ErrOut.
//
- STATIC_ASSERT (FixedPcdGet8 (PcdDefaultTerminalType) == 4,
- "PcdDefaultTerminalType must be TTYTERM");
- STATIC_ASSERT (FixedPcdGet8 (PcdUartDefaultParity) != 0,
- "PcdUartDefaultParity must be set to an actual value, not 'default'");
- STATIC_ASSERT (FixedPcdGet8 (PcdUartDefaultStopBits) != 0,
- "PcdUartDefaultStopBits must be set to an actual value, not 'default'");
+ STATIC_ASSERT (
+ FixedPcdGet8 (PcdDefaultTerminalType) == 4,
+ "PcdDefaultTerminalType must be TTYTERM"
+ );
+ STATIC_ASSERT (
+ FixedPcdGet8 (PcdUartDefaultParity) != 0,
+ "PcdUartDefaultParity must be set to an actual value, not 'default'"
+ );
+ STATIC_ASSERT (
+ FixedPcdGet8 (PcdUartDefaultStopBits) != 0,
+ "PcdUartDefaultStopBits must be set to an actual value, not 'default'"
+ );
CopyGuid (&mSerialConsole.TermType.Guid, &gEfiTtyTermGuid);
- EfiBootManagerUpdateConsoleVariable (ConIn,
- (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
- EfiBootManagerUpdateConsoleVariable (ConOut,
- (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
- EfiBootManagerUpdateConsoleVariable (ErrOut,
- (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+ EfiBootManagerUpdateConsoleVariable (
+ ConIn,
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole,
+ NULL
+ );
+ EfiBootManagerUpdateConsoleVariable (
+ ConOut,
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole,
+ NULL
+ );
+ EfiBootManagerUpdateConsoleVariable (
+ ErrOut,
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole,
+ NULL
+ );
//
// Register platform-specific boot options and keyboard shortcuts.
@@ -660,16 +751,19 @@ HandleCapsules ( VOID
)
{
- ESRT_MANAGEMENT_PROTOCOL *EsrtManagement;
- EFI_PEI_HOB_POINTERS HobPointer;
- EFI_CAPSULE_HEADER *CapsuleHeader;
- BOOLEAN NeedReset;
- EFI_STATUS Status;
+ ESRT_MANAGEMENT_PROTOCOL *EsrtManagement;
+ EFI_PEI_HOB_POINTERS HobPointer;
+ EFI_CAPSULE_HEADER *CapsuleHeader;
+ BOOLEAN NeedReset;
+ EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "%a: processing capsules ...\n", __FUNCTION__));
- Status = gBS->LocateProtocol (&gEsrtManagementProtocolGuid, NULL,
- (VOID **)&EsrtManagement);
+ Status = gBS->LocateProtocol (
+ &gEsrtManagementProtocolGuid,
+ NULL,
+ (VOID **)&EsrtManagement
+ );
if (!EFI_ERROR (Status)) {
EsrtManagement->SyncEsrtFmp ();
}
@@ -678,33 +772,43 @@ HandleCapsules ( // Find all capsule images from hob
//
HobPointer.Raw = GetHobList ();
- NeedReset = FALSE;
- while ((HobPointer.Raw = GetNextHob (EFI_HOB_TYPE_UEFI_CAPSULE,
- HobPointer.Raw)) != NULL) {
+ NeedReset = FALSE;
+ while ((HobPointer.Raw = GetNextHob (
+ EFI_HOB_TYPE_UEFI_CAPSULE,
+ HobPointer.Raw
+ )) != NULL)
+ {
CapsuleHeader = (VOID *)(UINTN)HobPointer.Capsule->BaseAddress;
Status = ProcessCapsuleImage (CapsuleHeader);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: failed to process capsule %p - %r\n",
- __FUNCTION__, CapsuleHeader, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: failed to process capsule %p - %r\n",
+ __FUNCTION__,
+ CapsuleHeader,
+ Status
+ ));
return;
}
- NeedReset = TRUE;
+ NeedReset = TRUE;
HobPointer.Raw = GET_NEXT_HOB (HobPointer);
}
if (NeedReset) {
- DEBUG ((DEBUG_WARN, "%a: capsule update successful, resetting ...\n",
- __FUNCTION__));
-
- gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
- CpuDeadLoop();
+ DEBUG ((
+ DEBUG_WARN,
+ "%a: capsule update successful, resetting ...\n",
+ __FUNCTION__
+ ));
+
+ gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
+ CpuDeadLoop ();
}
}
-
-#define VERSION_STRING_PREFIX L"Tianocore/EDK2 firmware version "
+#define VERSION_STRING_PREFIX L"Tianocore/EDK2 firmware version "
/**
This functions checks the value of BootDiscoverPolicy variable and
@@ -722,14 +826,14 @@ BootDiscoveryPolicyHandler ( VOID
)
{
- EFI_STATUS Status;
- UINT32 DiscoveryPolicy;
- UINT32 DiscoveryPolicyOld;
- UINTN Size;
- EFI_BOOT_MANAGER_POLICY_PROTOCOL *BMPolicy;
- EFI_GUID *Class;
-
- Size = sizeof (DiscoveryPolicy);
+ EFI_STATUS Status;
+ UINT32 DiscoveryPolicy;
+ UINT32 DiscoveryPolicyOld;
+ UINTN Size;
+ EFI_BOOT_MANAGER_POLICY_PROTOCOL *BMPolicy;
+ EFI_GUID *Class;
+
+ Size = sizeof (DiscoveryPolicy);
Status = gRT->GetVariable (
BOOT_DISCOVERY_POLICY_VAR,
&gBootDiscoveryPolicyMgrFormsetGuid,
@@ -739,7 +843,7 @@ BootDiscoveryPolicyHandler ( );
if (Status == EFI_NOT_FOUND) {
DiscoveryPolicy = PcdGet32 (PcdBootDiscoveryPolicy);
- Status = PcdSet32S (PcdBootDiscoveryPolicy, DiscoveryPolicy);
+ Status = PcdSet32S (PcdBootDiscoveryPolicy, DiscoveryPolicy);
if (Status == EFI_NOT_FOUND) {
return EFI_SUCCESS;
} else if (EFI_ERROR (Status)) {
@@ -776,13 +880,17 @@ BootDiscoveryPolicyHandler ( (VOID **)&BMPolicy
);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_INFO, "%a - Failed to locate gEfiBootManagerPolicyProtocolGuid."
- "Driver connect will be skipped.\n", __FUNCTION__));
+ DEBUG ((
+ DEBUG_INFO,
+ "%a - Failed to locate gEfiBootManagerPolicyProtocolGuid."
+ "Driver connect will be skipped.\n",
+ __FUNCTION__
+ ));
return Status;
}
Status = BMPolicy->ConnectDeviceClass (BMPolicy, Class);
- if (EFI_ERROR (Status)){
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a - ConnectDeviceClass returns - %r\n", __FUNCTION__, Status));
return Status;
}
@@ -790,7 +898,7 @@ BootDiscoveryPolicyHandler ( //
// Refresh Boot Options if Boot Discovery Policy has been changed
//
- Size = sizeof (DiscoveryPolicyOld);
+ Size = sizeof (DiscoveryPolicyOld);
Status = gRT->GetVariable (
BOOT_DISCOVERY_POLICY_OLD_VAR,
&gBootDiscoveryPolicyMgrFormsetGuid,
@@ -845,21 +953,33 @@ PlatformBootManagerAfterConsole ( Status = BootLogoEnableLogo ();
if (EFI_ERROR (Status)) {
if (FirmwareVerLength > 0) {
- Print (VERSION_STRING_PREFIX L"%s\n",
- PcdGetPtr (PcdFirmwareVersionString));
+ Print (
+ VERSION_STRING_PREFIX L"%s\n",
+ PcdGetPtr (PcdFirmwareVersionString)
+ );
}
+
Print (L"Press ESCAPE for boot options ");
} else if (FirmwareVerLength > 0) {
- Status = gBS->HandleProtocol (gST->ConsoleOutHandle,
- &gEfiGraphicsOutputProtocolGuid, (VOID **)&GraphicsOutput);
+ Status = gBS->HandleProtocol (
+ gST->ConsoleOutHandle,
+ &gEfiGraphicsOutputProtocolGuid,
+ (VOID **)&GraphicsOutput
+ );
if (!EFI_ERROR (Status)) {
PosX = (GraphicsOutput->Mode->Info->HorizontalResolution -
(StrLen (VERSION_STRING_PREFIX) + FirmwareVerLength) *
EFI_GLYPH_WIDTH) / 2;
PosY = 0;
- PrintXY (PosX, PosY, NULL, NULL, VERSION_STRING_PREFIX L"%s",
- PcdGetPtr (PcdFirmwareVersionString));
+ PrintXY (
+ PosX,
+ PosY,
+ NULL,
+ NULL,
+ VERSION_STRING_PREFIX L"%s",
+ PcdGetPtr (PcdFirmwareVersionString)
+ );
}
}
@@ -881,8 +1001,8 @@ PlatformBootManagerAfterConsole ( //
// Register UEFI Shell
//
- Key.ScanCode = SCAN_NULL;
- Key.UnicodeChar = L's';
+ Key.ScanCode = SCAN_NULL;
+ Key.UnicodeChar = L's';
PlatformRegisterFvBootOption (&gUefiShellFileGuid, L"UEFI Shell", 0, &Key);
}
@@ -895,13 +1015,13 @@ PlatformBootManagerAfterConsole ( VOID
EFIAPI
PlatformBootManagerWaitCallback (
- UINT16 TimeoutRemain
+ UINT16 TimeoutRemain
)
{
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION Black;
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION White;
- UINT16 Timeout;
- EFI_STATUS Status;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION Black;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION White;
+ UINT16 Timeout;
+ EFI_STATUS Status;
Timeout = PcdGet16 (PcdPlatformBootTimeOut);
@@ -934,17 +1054,19 @@ PlatformBootManagerUnableToBoot ( VOID
)
{
- EFI_STATUS Status;
- EFI_BOOT_MANAGER_LOAD_OPTION BootManagerMenu;
- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
- UINTN OldBootOptionCount;
- UINTN NewBootOptionCount;
+ EFI_STATUS Status;
+ EFI_BOOT_MANAGER_LOAD_OPTION BootManagerMenu;
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
+ UINTN OldBootOptionCount;
+ UINTN NewBootOptionCount;
//
// Record the total number of boot configured boot options
//
- BootOptions = EfiBootManagerGetLoadOptions (&OldBootOptionCount,
- LoadOptionTypeBoot);
+ BootOptions = EfiBootManagerGetLoadOptions (
+ &OldBootOptionCount,
+ LoadOptionTypeBoot
+ );
EfiBootManagerFreeLoadOptions (BootOptions, OldBootOptionCount);
//
@@ -956,8 +1078,10 @@ PlatformBootManagerUnableToBoot ( //
// Record the updated number of boot configured boot options
//
- BootOptions = EfiBootManagerGetLoadOptions (&NewBootOptionCount,
- LoadOptionTypeBoot);
+ BootOptions = EfiBootManagerGetLoadOptions (
+ &NewBootOptionCount,
+ LoadOptionTypeBoot
+ );
EfiBootManagerFreeLoadOptions (BootOptions, NewBootOptionCount);
//
@@ -969,8 +1093,11 @@ PlatformBootManagerUnableToBoot ( //
if (!PcdGetBool (PcdEmuVariableNvModeEnable)) {
if (NewBootOptionCount != OldBootOptionCount) {
- DEBUG ((DEBUG_WARN, "%a: rebooting after refreshing all boot options\n",
- __FUNCTION__));
+ DEBUG ((
+ DEBUG_WARN,
+ "%a: rebooting after refreshing all boot options\n",
+ __FUNCTION__
+ ));
gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
}
}
@@ -980,7 +1107,7 @@ PlatformBootManagerUnableToBoot ( return;
}
- for (;;) {
+ for ( ; ;) {
EfiBootManagerBoot (&BootManagerMenu);
}
}
diff --git a/ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c b/ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c index 80e531921c..6539c01763 100644 --- a/ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c +++ b/ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c @@ -39,18 +39,18 @@ WriteStringToFile ( // This gets you all the symbols except for SEC. To get SEC symbols you need to copy the
// debug print in the SEC into the debugger manually
SemihostWriteString (Buffer);
-/*
- I'm currently having issues with this code crashing the debugger. Seems like it should work.
- UINT32 SemihostHandle;
- UINT32 SemihostMode = SEMIHOST_FILE_MODE_WRITE | SEMIHOST_FILE_MODE_BINARY | SEMIHOST_FILE_MODE_UPDATE;
+ /*
+ I'm currently having issues with this code crashing the debugger. Seems like it should work.
- SemihostFileOpen ("c:\rvi_symbols.inc", SemihostMode, &SemihostHandle);
- SemihostFileWrite (SemihostHandle, &Length, Buffer);
- SemihostFileClose (SemihostHandle);
- */
-}
+ UINT32 SemihostHandle;
+ UINT32 SemihostMode = SEMIHOST_FILE_MODE_WRITE | SEMIHOST_FILE_MODE_BINARY | SEMIHOST_FILE_MODE_UPDATE;
+ SemihostFileOpen ("c:\rvi_symbols.inc", SemihostMode, &SemihostHandle);
+ SemihostFileWrite (SemihostHandle, &Length, Buffer);
+ SemihostFileClose (SemihostHandle);
+ */
+}
/**
If the build is done on cygwin the paths are cygpaths.
@@ -62,12 +62,12 @@ WriteStringToFile ( **/
CHAR8 *
DeCygwinPathIfNeeded (
- IN CHAR8 *Name
+ IN CHAR8 *Name
)
{
- CHAR8 *Ptr;
- UINTN Index;
- UINTN Len;
+ CHAR8 *Ptr;
+ UINTN Index;
+ UINTN Len;
Ptr = AsciiStrStr (Name, "/cygdrive/");
if (Ptr == NULL) {
@@ -88,14 +88,13 @@ DeCygwinPathIfNeeded ( // switch path separators
for (Index = 11; Index < Len; Index++) {
if (Ptr[Index] == '/') {
- Ptr[Index] = '\\' ;
+ Ptr[Index] = '\\';
}
}
return Name;
}
-
/**
Performs additional actions after a PE/COFF image has been loaded and relocated.
@@ -111,20 +110,18 @@ PeCoffLoaderRelocateImageExtraAction ( IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
- CHAR8 Buffer[256];
+ CHAR8 Buffer[256];
-#if (__ARMCC_VERSION < 500000)
- AsciiSPrint (Buffer, sizeof(Buffer), "load /a /ni /np \"%a\" &0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));
-#else
- AsciiSPrint (Buffer, sizeof(Buffer), "add-symbol-file %a 0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));
-#endif
+ #if (__ARMCC_VERSION < 500000)
+ AsciiSPrint (Buffer, sizeof (Buffer), "load /a /ni /np \"%a\" &0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));
+ #else
+ AsciiSPrint (Buffer, sizeof (Buffer), "add-symbol-file %a 0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));
+ #endif
DeCygwinPathIfNeeded (&Buffer[16]);
WriteStringToFile (Buffer, AsciiStrSize (Buffer));
}
-
-
/**
Performs additional actions just before a PE/COFF image is unloaded. Any resources
that were allocated by PeCoffLoaderRelocateImageExtraAction() must be freed.
@@ -141,9 +138,9 @@ PeCoffLoaderUnloadImageExtraAction ( IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
- CHAR8 Buffer[256];
+ CHAR8 Buffer[256];
- AsciiSPrint (Buffer, sizeof(Buffer), "unload symbols_only \"%a\"\n", ImageContext->PdbPointer);
+ AsciiSPrint (Buffer, sizeof (Buffer), "unload symbols_only \"%a\"\n", ImageContext->PdbPointer);
DeCygwinPathIfNeeded (Buffer);
WriteStringToFile (Buffer, AsciiStrSize (Buffer));
diff --git a/ArmPkg/Library/SemiHostingDebugLib/DebugLib.c b/ArmPkg/Library/SemiHostingDebugLib/DebugLib.c index ae762d8bea..c3ea568dc4 100644 --- a/ArmPkg/Library/SemiHostingDebugLib/DebugLib.c +++ b/ArmPkg/Library/SemiHostingDebugLib/DebugLib.c @@ -7,7 +7,6 @@ **/
-
#include <Uefi.h>
#include <Library/DebugLib.h>
#include <Library/PrintLib.h>
@@ -25,7 +24,7 @@ // VA_LIST can not initialize to NULL for all compiler, so we use this to
// indicate a null VA_LIST
//
-VA_LIST mVaListNull;
+VA_LIST mVaListNull;
/**
@@ -49,14 +48,13 @@ DebugPrint ( ...
)
{
- VA_LIST Marker;
+ VA_LIST Marker;
VA_START (Marker, Format);
DebugVPrint (ErrorLevel, Format, Marker);
VA_END (Marker);
}
-
/**
Prints a debug message to the debug output device if the specified
error level is enabled base on Null-terminated format string and a
@@ -76,13 +74,13 @@ DebugPrint ( **/
VOID
DebugPrintMarker (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- IN VA_LIST VaListMarker,
- IN BASE_LIST BaseListMarker
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN VA_LIST VaListMarker,
+ IN BASE_LIST BaseListMarker
)
{
- CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];
+ CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];
//
// If Format is NULL, then ASSERT().
@@ -92,7 +90,7 @@ DebugPrintMarker ( //
// Check driver debug mask value and global mask
//
- if ((ErrorLevel & PcdGet32(PcdDebugPrintErrorLevel)) == 0) {
+ if ((ErrorLevel & PcdGet32 (PcdDebugPrintErrorLevel)) == 0) {
return;
}
@@ -108,7 +106,6 @@ DebugPrintMarker ( SemihostWriteString (AsciiBuffer);
}
-
/**
Prints a debug message to the debug output device if the specified
error level is enabled.
@@ -127,15 +124,14 @@ DebugPrintMarker ( VOID
EFIAPI
DebugVPrint (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- IN VA_LIST VaListMarker
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN VA_LIST VaListMarker
)
{
DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL);
}
-
/**
Prints a debug message to the debug output device if the specified
error level is enabled.
@@ -156,15 +152,14 @@ DebugVPrint ( VOID
EFIAPI
DebugBPrint (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- IN BASE_LIST BaseListMarker
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN BASE_LIST BaseListMarker
)
{
DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker);
}
-
/**
Prints an assert message containing a filename, line number, and description.
@@ -196,7 +191,7 @@ DebugAssert ( IN CONST CHAR8 *Description
)
{
- CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];
+ CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];
//
// Generate the ASSERT() message in Unicode format
@@ -208,14 +203,13 @@ DebugAssert ( //
// Generate a Breakpoint, DeadLoop, or NOP based on PCD settings
//
- if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {
+ if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {
CpuBreakpoint ();
- } else if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {
+ } else if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {
CpuDeadLoop ();
}
}
-
/**
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
@@ -248,10 +242,9 @@ DebugClearMemory ( //
// SetMem() checks for the ASSERT() condition on Length and returns Buffer
//
- return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));
+ return SetMem (Buffer, Length, PcdGet8 (PcdDebugClearMemoryValue));
}
-
/**
Returns TRUE if ASSERT() macros are enabled.
@@ -269,10 +262,9 @@ DebugAssertEnabled ( VOID
)
{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);
}
-
/**
Returns TRUE if DEBUG()macros are enabled.
@@ -290,10 +282,9 @@ DebugPrintEnabled ( VOID
)
{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);
}
-
/**
Returns TRUE if DEBUG_CODE()macros are enabled.
@@ -311,10 +302,9 @@ DebugCodeEnabled ( VOID
)
{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);
}
-
/**
Returns TRUE if DEBUG_CLEAR_MEMORY()macro is enabled.
@@ -332,5 +322,5 @@ DebugClearMemoryEnabled ( VOID
)
{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);
}
diff --git a/ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c b/ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c index b6a07dd466..5ff8a5b7a6 100644 --- a/ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c +++ b/ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c @@ -13,7 +13,6 @@ #include <Library/SemihostLib.h>
#include <Library/SerialPortLib.h>
-
/*
Programmed hardware of Serial port.
@@ -51,55 +50,50 @@ SerialPortInitialize ( UINTN
EFIAPI
SerialPortWrite (
- IN UINT8 *Buffer,
- IN UINTN NumberOfBytes
-)
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
{
- UINT8 PrintBuffer[PRINT_BUFFER_SIZE];
- UINTN SourceIndex;
- UINTN DestinationIndex;
- UINT8 CurrentCharacter;
+ UINT8 PrintBuffer[PRINT_BUFFER_SIZE];
+ UINTN SourceIndex;
+ UINTN DestinationIndex;
+ UINT8 CurrentCharacter;
SourceIndex = 0;
DestinationIndex = 0;
- while (SourceIndex < NumberOfBytes)
- {
- CurrentCharacter = Buffer[SourceIndex++];
+ while (SourceIndex < NumberOfBytes) {
+ CurrentCharacter = Buffer[SourceIndex++];
- switch (CurrentCharacter)
- {
+ switch (CurrentCharacter) {
case '\r':
- continue;
+ continue;
case '\n':
- PrintBuffer[DestinationIndex++] = ' ';
- // fall through
+ PrintBuffer[DestinationIndex++] = ' ';
+ // fall through
default:
- PrintBuffer[DestinationIndex++] = CurrentCharacter;
- break;
- }
+ PrintBuffer[DestinationIndex++] = CurrentCharacter;
+ break;
+ }
- if (DestinationIndex > PRINT_BUFFER_THRESHOLD)
- {
- PrintBuffer[DestinationIndex] = '\0';
- SemihostWriteString ((CHAR8 *) PrintBuffer);
+ if (DestinationIndex > PRINT_BUFFER_THRESHOLD) {
+ PrintBuffer[DestinationIndex] = '\0';
+ SemihostWriteString ((CHAR8 *)PrintBuffer);
- DestinationIndex = 0;
- }
+ DestinationIndex = 0;
+ }
}
- if (DestinationIndex > 0)
- {
- PrintBuffer[DestinationIndex] = '\0';
- SemihostWriteString ((CHAR8 *) PrintBuffer);
+ if (DestinationIndex > 0) {
+ PrintBuffer[DestinationIndex] = '\0';
+ SemihostWriteString ((CHAR8 *)PrintBuffer);
}
return NumberOfBytes;
}
-
/**
Read data from serial device and save the datas in buffer.
@@ -113,16 +107,14 @@ SerialPortWrite ( UINTN
EFIAPI
SerialPortRead (
- OUT UINT8 *Buffer,
- IN UINTN NumberOfBytes
-)
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
{
*Buffer = SemihostReadCharacter ();
return 1;
}
-
-
/**
Check to see if any data is available to be read from the debug device.
@@ -139,4 +131,3 @@ SerialPortPoll ( // Since SemiHosting read character is blocking always say we have a char ready?
return SemihostConnectionSupported ();
}
-
diff --git a/ArmPkg/Library/SemihostLib/SemihostLib.c b/ArmPkg/Library/SemihostLib/SemihostLib.c index d66de71182..9e6fc379d9 100644 --- a/ArmPkg/Library/SemihostLib/SemihostLib.c +++ b/ArmPkg/Library/SemihostLib/SemihostLib.c @@ -23,9 +23,9 @@ SemihostConnectionSupported ( RETURN_STATUS
SemihostFileOpen (
- IN CHAR8 *FileName,
- IN UINT32 Mode,
- OUT UINTN *FileHandle
+ IN CHAR8 *FileName,
+ IN UINT32 Mode,
+ OUT UINTN *FileHandle
)
{
SEMIHOST_FILE_OPEN_BLOCK OpenBlock;
@@ -40,9 +40,9 @@ SemihostFileOpen ( FileName++;
}
- OpenBlock.FileName = FileName;
- OpenBlock.Mode = Mode;
- OpenBlock.NameLength = AsciiStrLen(FileName);
+ OpenBlock.FileName = FileName;
+ OpenBlock.Mode = Mode;
+ OpenBlock.NameLength = AsciiStrLen (FileName);
Result = SEMIHOST_SYS_OPEN (&OpenBlock);
@@ -124,10 +124,11 @@ SemihostFileWrite ( *Length = SEMIHOST_SYS_WRITE (&WriteBlock);
- if (*Length != 0)
+ if (*Length != 0) {
return RETURN_ABORTED;
- else
+ } else {
return RETURN_SUCCESS;
+ }
}
RETURN_STATUS
@@ -148,7 +149,7 @@ SemihostFileLength ( OUT UINTN *Length
)
{
- INT32 Result;
+ INT32 Result;
if (Length == NULL) {
return RETURN_INVALID_PARAMETER;
@@ -178,7 +179,7 @@ SemihostFileLength ( **/
RETURN_STATUS
-SemihostFileTmpName(
+SemihostFileTmpName (
OUT VOID *Buffer,
IN UINT8 Identifier,
IN UINTN Length
@@ -198,15 +199,15 @@ SemihostFileTmpName( Result = SEMIHOST_SYS_TMPNAME (&TmpNameBlock);
if (Result != 0) {
- return RETURN_ABORTED;
+ return RETURN_ABORTED;
} else {
- return RETURN_SUCCESS;
+ return RETURN_SUCCESS;
}
}
RETURN_STATUS
SemihostFileRemove (
- IN CHAR8 *FileName
+ IN CHAR8 *FileName
)
{
SEMIHOST_FILE_REMOVE_BLOCK RemoveBlock;
@@ -217,8 +218,8 @@ SemihostFileRemove ( FileName++;
}
- RemoveBlock.FileName = FileName;
- RemoveBlock.NameLength = AsciiStrLen(FileName);
+ RemoveBlock.FileName = FileName;
+ RemoveBlock.NameLength = AsciiStrLen (FileName);
Result = SEMIHOST_SYS_REMOVE (&RemoveBlock);
@@ -241,7 +242,7 @@ SemihostFileRemove ( **/
RETURN_STATUS
-SemihostFileRename(
+SemihostFileRename (
IN CHAR8 *FileName,
IN CHAR8 *NewFileName
)
@@ -261,9 +262,9 @@ SemihostFileRename( Result = SEMIHOST_SYS_RENAME (&RenameBlock);
if (Result != 0) {
- return RETURN_ABORTED;
+ return RETURN_ABORTED;
} else {
- return RETURN_SUCCESS;
+ return RETURN_SUCCESS;
}
}
@@ -277,7 +278,7 @@ SemihostReadCharacter ( VOID
SemihostWriteCharacter (
- IN CHAR8 Character
+ IN CHAR8 Character
)
{
SEMIHOST_SYS_WRITEC (&Character);
@@ -285,7 +286,7 @@ SemihostWriteCharacter ( VOID
SemihostWriteString (
- IN CHAR8 *String
+ IN CHAR8 *String
)
{
SEMIHOST_SYS_WRITE0 (String);
@@ -293,13 +294,13 @@ SemihostWriteString ( UINT32
SemihostSystem (
- IN CHAR8 *CommandLine
+ IN CHAR8 *CommandLine
)
{
- SEMIHOST_SYSTEM_BLOCK SystemBlock;
+ SEMIHOST_SYSTEM_BLOCK SystemBlock;
SystemBlock.CommandLine = CommandLine;
- SystemBlock.CommandLength = AsciiStrLen(CommandLine);
+ SystemBlock.CommandLength = AsciiStrLen (CommandLine);
return SEMIHOST_SYS_SYSTEM (&SystemBlock);
}
diff --git a/ArmPkg/Library/SemihostLib/SemihostPrivate.h b/ArmPkg/Library/SemihostLib/SemihostPrivate.h index 8864726116..22abbf3bae 100644 --- a/ArmPkg/Library/SemihostLib/SemihostPrivate.h +++ b/ArmPkg/Library/SemihostLib/SemihostPrivate.h @@ -11,14 +11,14 @@ #define SEMIHOST_PRIVATE_H_
typedef struct {
- CHAR8 *FileName;
+ CHAR8 *FileName;
UINTN Mode;
UINTN NameLength;
} SEMIHOST_FILE_OPEN_BLOCK;
typedef struct {
UINTN Handle;
- VOID *Buffer;
+ VOID *Buffer;
UINTN Length;
} SEMIHOST_FILE_READ_WRITE_BLOCK;
@@ -28,127 +28,127 @@ typedef struct { } SEMIHOST_FILE_SEEK_BLOCK;
typedef struct {
- VOID *Buffer;
+ VOID *Buffer;
UINTN Identifier;
UINTN Length;
} SEMIHOST_FILE_TMPNAME_BLOCK;
typedef struct {
- CHAR8 *FileName;
+ CHAR8 *FileName;
UINTN NameLength;
} SEMIHOST_FILE_REMOVE_BLOCK;
typedef struct {
- CHAR8 *FileName;
+ CHAR8 *FileName;
UINTN FileNameLength;
- CHAR8 *NewFileName;
+ CHAR8 *NewFileName;
UINTN NewFileNameLength;
} SEMIHOST_FILE_RENAME_BLOCK;
typedef struct {
- CHAR8 *CommandLine;
+ CHAR8 *CommandLine;
UINTN CommandLength;
} SEMIHOST_SYSTEM_BLOCK;
-#if defined(__CC_ARM)
+#if defined (__CC_ARM)
-#if defined(__thumb__)
-#define SWI 0xAB
-#else
-#define SWI 0x123456
-#endif
+ #if defined (__thumb__)
+#define SWI 0xAB
+ #else
+#define SWI 0x123456
+ #endif
#define SEMIHOST_SUPPORTED TRUE
-__swi(SWI)
+__swi (SWI)
INT32
-_Semihost_SYS_OPEN(
- IN UINTN SWI_0x01,
- IN SEMIHOST_FILE_OPEN_BLOCK *OpenBlock
+_Semihost_SYS_OPEN (
+ IN UINTN SWI_0x01,
+ IN SEMIHOST_FILE_OPEN_BLOCK *OpenBlock
);
-__swi(SWI)
+__swi (SWI)
INT32
-_Semihost_SYS_CLOSE(
- IN UINTN SWI_0x02,
- IN UINT32 *Handle
+_Semihost_SYS_CLOSE (
+ IN UINTN SWI_0x02,
+ IN UINT32 *Handle
);
-__swi(SWI)
+__swi (SWI)
VOID
-_Semihost_SYS_WRITEC(
- IN UINTN SWI_0x03,
- IN CHAR8 *Character
+_Semihost_SYS_WRITEC (
+ IN UINTN SWI_0x03,
+ IN CHAR8 *Character
);
-__swi(SWI)
+__swi (SWI)
VOID
-_Semihost_SYS_WRITE0(
- IN UINTN SWI_0x04,
- IN CHAR8 *String
+_Semihost_SYS_WRITE0 (
+ IN UINTN SWI_0x04,
+ IN CHAR8 *String
);
-__swi(SWI)
+__swi (SWI)
UINT32
-_Semihost_SYS_WRITE(
- IN UINTN SWI_0x05,
- IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *WriteBlock
+_Semihost_SYS_WRITE (
+ IN UINTN SWI_0x05,
+ IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *WriteBlock
);
-__swi(SWI)
+__swi (SWI)
UINT32
-_Semihost_SYS_READ(
- IN UINTN SWI_0x06,
- IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *ReadBlock
+_Semihost_SYS_READ (
+ IN UINTN SWI_0x06,
+ IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *ReadBlock
);
-__swi(SWI)
+__swi (SWI)
CHAR8
-_Semihost_SYS_READC(
- IN UINTN SWI_0x07,
- IN UINTN Zero
+_Semihost_SYS_READC (
+ IN UINTN SWI_0x07,
+ IN UINTN Zero
);
-__swi(SWI)
+__swi (SWI)
INT32
-_Semihost_SYS_SEEK(
- IN UINTN SWI_0x0A,
- IN SEMIHOST_FILE_SEEK_BLOCK *SeekBlock
+_Semihost_SYS_SEEK (
+ IN UINTN SWI_0x0A,
+ IN SEMIHOST_FILE_SEEK_BLOCK *SeekBlock
);
-__swi(SWI)
+__swi (SWI)
INT32
-_Semihost_SYS_FLEN(
- IN UINTN SWI_0x0C,
- IN UINT32 *Handle
+_Semihost_SYS_FLEN (
+ IN UINTN SWI_0x0C,
+ IN UINT32 *Handle
);
-__swi(SWI)
+__swi (SWI)
UINT32
-_Semihost_SYS_TMPNAME(
- IN UINTN SWI_0x0D,
- IN SEMIHOST_FILE_TMPNAME_BLOCK *TmpNameBlock
+_Semihost_SYS_TMPNAME (
+ IN UINTN SWI_0x0D,
+ IN SEMIHOST_FILE_TMPNAME_BLOCK *TmpNameBlock
);
-__swi(SWI)
+__swi (SWI)
UINT32
-_Semihost_SYS_REMOVE(
- IN UINTN SWI_0x0E,
- IN SEMIHOST_FILE_REMOVE_BLOCK *RemoveBlock
+_Semihost_SYS_REMOVE (
+ IN UINTN SWI_0x0E,
+ IN SEMIHOST_FILE_REMOVE_BLOCK *RemoveBlock
);
-__swi(SWI)
+__swi (SWI)
UINT32
-_Semihost_SYS_RENAME(
- IN UINTN SWI_0x0F,
- IN SEMIHOST_FILE_RENAME_BLOCK *RenameBlock
+_Semihost_SYS_RENAME (
+ IN UINTN SWI_0x0F,
+ IN SEMIHOST_FILE_RENAME_BLOCK *RenameBlock
);
-__swi(SWI)
+__swi (SWI)
UINT32
-_Semihost_SYS_SYSTEM(
- IN UINTN SWI_0x12,
- IN SEMIHOST_SYSTEM_BLOCK *SystemBlock
+_Semihost_SYS_SYSTEM (
+ IN UINTN SWI_0x12,
+ IN SEMIHOST_SYSTEM_BLOCK *SystemBlock
);
#define SEMIHOST_SYS_OPEN(OpenBlock) _Semihost_SYS_OPEN(0x01, OpenBlock)
@@ -165,14 +165,14 @@ _Semihost_SYS_SYSTEM( #define SEMIHOST_SYS_RENAME(RenameBlock) _Semihost_SYS_RENAME(0x0F, RenameBlock)
#define SEMIHOST_SYS_SYSTEM(SystemBlock) _Semihost_SYS_SYSTEM(0x12, SystemBlock)
-#elif defined(__GNUC__) // __CC_ARM
+#elif defined (__GNUC__) // __CC_ARM
#define SEMIHOST_SUPPORTED TRUE
UINT32
GccSemihostCall (
- IN UINT32 Operation,
- IN UINTN SystemBlockAddress
+ IN UINT32 Operation,
+ IN UINTN SystemBlockAddress
); // __attribute__ ((interrupt ("SVC")));
#define SEMIHOST_SYS_OPEN(OpenBlock) GccSemihostCall(0x01, (UINTN)(OpenBlock))
@@ -193,8 +193,8 @@ GccSemihostCall ( #define SEMIHOST_SUPPORTED FALSE
-#define SEMIHOST_SYS_OPEN(OpenBlock) (-1)
-#define SEMIHOST_SYS_CLOSE(Handle) (-1)
+#define SEMIHOST_SYS_OPEN(OpenBlock) (-1)
+#define SEMIHOST_SYS_CLOSE(Handle) (-1)
#define SEMIHOST_SYS_WRITE0(String)
#define SEMIHOST_SYS_WRITEC(Character)
#define SEMIHOST_SYS_WRITE(WriteBlock) (0)
diff --git a/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c index 20f873e680..d55aff7620 100644 --- a/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c +++ b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c @@ -45,8 +45,8 @@ STATIC
EFI_STATUS
SendMemoryPermissionRequest (
- IN OUT ARM_SVC_ARGS *SvcArgs,
- OUT INT32 *RetVal
+ IN OUT ARM_SVC_ARGS *SvcArgs,
+ OUT INT32 *RetVal
)
{
if ((SvcArgs == NULL) || (RetVal == NULL)) {
@@ -148,8 +148,8 @@ SendMemoryPermissionRequest ( STATIC
EFI_STATUS
GetMemoryPermissions (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- OUT UINT32 *MemoryAttributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ OUT UINT32 *MemoryAttributes
)
{
EFI_STATUS Status;
@@ -207,9 +207,9 @@ GetMemoryPermissions ( STATIC
EFI_STATUS
RequestMemoryPermissionChange (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT32 Permissions
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT32 Permissions
)
{
INT32 Ret;
@@ -239,13 +239,13 @@ RequestMemoryPermissionChange ( EFI_STATUS
ArmSetMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- EFI_STATUS Status;
- UINT32 MemoryAttributes;
- UINT32 CodePermission;
+ EFI_STATUS Status;
+ UINT32 MemoryAttributes;
+ UINT32 CodePermission;
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);
if (!EFI_ERROR (Status)) {
@@ -256,18 +256,19 @@ ArmSetMemoryRegionNoExec ( MemoryAttributes | CodePermission
);
}
+
return Status;
}
EFI_STATUS
ArmClearMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- EFI_STATUS Status;
- UINT32 MemoryAttributes;
- UINT32 CodePermission;
+ EFI_STATUS Status;
+ UINT32 MemoryAttributes;
+ UINT32 CodePermission;
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);
if (!EFI_ERROR (Status)) {
@@ -278,18 +279,19 @@ ArmClearMemoryRegionNoExec ( MemoryAttributes & ~CodePermission
);
}
+
return Status;
}
EFI_STATUS
ArmSetMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- EFI_STATUS Status;
- UINT32 MemoryAttributes;
- UINT32 DataPermission;
+ EFI_STATUS Status;
+ UINT32 MemoryAttributes;
+ UINT32 DataPermission;
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);
if (!EFI_ERROR (Status)) {
@@ -300,28 +302,32 @@ ArmSetMemoryRegionReadOnly ( MemoryAttributes | DataPermission
);
}
+
return Status;
}
EFI_STATUS
ArmClearMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- EFI_STATUS Status;
- UINT32 MemoryAttributes;
- UINT32 PermissionRequest;
+ EFI_STATUS Status;
+ UINT32 MemoryAttributes;
+ UINT32 PermissionRequest;
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);
if (!EFI_ERROR (Status)) {
- PermissionRequest = SET_MEM_ATTR_MAKE_PERM_REQUEST (SET_MEM_ATTR_DATA_PERM_RW,
- MemoryAttributes);
+ PermissionRequest = SET_MEM_ATTR_MAKE_PERM_REQUEST (
+ SET_MEM_ATTR_DATA_PERM_RW,
+ MemoryAttributes
+ );
return RequestMemoryPermissionChange (
BaseAddress,
Length,
PermissionRequest
);
}
+
return Status;
}
|