ArmPkg: remove unused ArmGicSecLib library implementation

This module is not used anywhere under edk2 or edk2-platforms, so let's
remove it. This removes the only dependency on ArmPlatformLib from ArmPkg.
While at it, remove a mention of ArmPlatformPkg from a comment in the
.dec file as well.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

4 files changed, 2 insertions, 155 deletions

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index f99054a7de..f3fb77c16f 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -224,8 +224,8 @@
 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]

 

   # System Memory (DRAM): These PCDs define the region of in-built system memory

-  # Some platforms can get DRAM extensions, these additional regions will be declared

-  # to UEFI by ArmPlatformLib

+  # Some platforms can get DRAM extensions, these additional regions may be

+  # declared to UEFI using separate resource descriptor HOBs

   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029

   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A

 

diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc
index a396c96bf8..622720ab2a 100644
--- a/ArmPkg/ArmPkg.dsc
+++ b/ArmPkg/ArmPkg.dsc
@@ -121,7 +121,6 @@
   ArmPkg/Drivers/CpuPei/CpuPei.inf

   ArmPkg/Drivers/ArmGic/ArmGicDxe.inf

   ArmPkg/Drivers/ArmGic/ArmGicLib.inf

-  ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf

   ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf

   ArmPkg/Drivers/TimerDxe/TimerDxe.inf

 

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
deleted file mode 100644
index fc2e1bc01e..0000000000
--- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+++ /dev/null
@@ -1,52 +0,0 @@
-#/* @file

-#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.

-#

-#  This program and the accompanying materials

-#  are licensed and made available under the terms and conditions of the BSD License

-#  which accompanies this distribution.  The full text of the license may be found at

-#  http://opensource.org/licenses/bsd-license.php

-#

-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-#

-#*/

-

-[Defines]

-  INF_VERSION                    = 0x00010005

-  BASE_NAME                      = ArmGicSecLib

-  FILE_GUID                      = 85f3cf80-b5f4-11df-9855-0002a5d5c51b

-  MODULE_TYPE                    = SEC

-  VERSION_STRING                 = 1.0

-  LIBRARY_CLASS                  = ArmGicLib

-

-[Sources]

-  ArmGicLib.c

-  ArmGicSecLib.c

-

-  GicV2/ArmGicV2Lib.c

-  GicV2/ArmGicV2SecLib.c

-

-[Sources.ARM]

-  GicV3/Arm/ArmGicV3.S     | GCC

-  GicV3/Arm/ArmGicV3.asm   | RVCT

-

-[Sources.AARCH64]

-  GicV3/AArch64/ArmGicV3.S

-

-[Packages]

-  ArmPkg/ArmPkg.dec

-  ArmPlatformPkg/ArmPlatformPkg.dec

-  MdePkg/MdePkg.dec

-  MdeModulePkg/MdeModulePkg.dec

-

-[LibraryClasses]

-  ArmLib

-  DebugLib

-  IoLib

-  ArmGicArchLib

-

-[Pcd]

-  gArmPlatformTokenSpaceGuid.PcdCoreCount

-

-[FeaturePcd]

-  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy

diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c
deleted file mode 100644
index ac1e0e4945..0000000000
--- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/** @file

-*

-*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.

-*

-*  This program and the accompanying materials

-*  are licensed and made available under the terms and conditions of the BSD License

-*  which accompanies this distribution.  The full text of the license may be found at

-*  http://opensource.org/licenses/bsd-license.php

-*

-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-*

-**/

-

-#include <Base.h>

-#include <Library/ArmLib.h>

-#include <Library/ArmPlatformLib.h>

-#include <Library/DebugLib.h>

-#include <Library/IoLib.h>

-#include <Library/ArmGicLib.h>

-

-/*

- * This function configures the all interrupts to be Non-secure.

- *

- */

-VOID

-EFIAPI

-ArmGicV2SetupNonSecure (

-  IN  UINTN         MpId,

-  IN  INTN          GicDistributorBase,

-  IN  INTN          GicInterruptInterfaceBase

-  )

-{

-  UINTN InterruptId;

-  UINTN CachedPriorityMask;

-  UINTN Index;

-  UINTN MaxInterrupts;

-

-  CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);

-

-  // Set priority Mask so that no interrupts get through to CPU

-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);

-

-  InterruptId   = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);

-  MaxInterrupts = ArmGicGetMaxNumInterrupts (GicDistributorBase);

-

-  // Only try to clear valid interrupts. Ignore spurious interrupts.

-  while ((InterruptId & 0x3FF) < MaxInterrupts) {

-    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal

-    ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId);

-

-    // Next

-    InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);

-  }

-

-  // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).

-  if (ArmPlatformIsPrimaryCore (MpId)) {

-    // Ensure all GIC interrupts are Non-Secure

-    for (Index = 0; Index < (MaxInterrupts / 32); Index++) {

-      MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);

-    }

-  } else {

-    // The secondary cores only set the Non Secure bit to their banked PPIs

-    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);

-  }

-

-  // Ensure all interrupts can get through the priority mask

-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);

-}

-

-VOID

-EFIAPI

-ArmGicV2EnableInterruptInterface (

-  IN  INTN          GicInterruptInterfaceBase

-  )

-{

-  // Set Priority Mask to allow interrupts

-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);

-

-  // Enable CPU interface in Secure world

-  // Enable CPU interface in Non-secure World

-  // Signal Secure Interrupts to CPU using FIQ line *

-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,

-      ARM_GIC_ICCICR_ENABLE_SECURE |

-      ARM_GIC_ICCICR_ENABLE_NS |

-      ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);

-}

-

-VOID

-EFIAPI

-ArmGicV2DisableInterruptInterface (

-  IN  INTN          GicInterruptInterfaceBase

-  )

-{

-  UINT32    ControlValue;

-

-  // Disable CPU interface in Secure world and Non-secure World

-  ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);

-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));

-}