ARM Packages: Force the SEC modules to be 2K aligned for AArch64

The AArch64 Vector Table must be aligned on a 2K boundary.
The FDF specification does not support 2K alignment but support 4K.

A clear comment has been added to help integrator to understand why the
assertion fails when porting to a new AArch64 platform.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15659 6f19259b-4bc3-4df7-8a09-765794883524

2 files changed, 11 insertions, 9 deletions

diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c b/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c
index 59246f80bc..ce1c6ce09a 100644
--- a/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c
+++ b/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c
@@ -1,7 +1,7 @@
 /** @file

 

   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

-  Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>

+  Portions Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -131,11 +131,12 @@ InitializeExceptions (
   FiqEnabled = ArmGetFiqState ();

   ArmDisableFiq ();

 

-  // AArch64 alignment? The Vector table must be 2k-byte aligned (bottom 11 bits zero)?

-  //DEBUG ((EFI_D_ERROR, "vbar set addr: 0x%016lx\n",(UINTN)ExceptionHandlersStart));

-  //ASSERT(((UINTN)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);

+  // The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure 'Align=4K'

+  // is defined into your FDF for this module.

+  ASSERT (((UINTN)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);

 

-  // We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.

+  // We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector

+  // Base Address to point into CpuDxe code.

   ArmWriteVBar ((UINTN)ExceptionHandlersStart);

 

   if (FiqEnabled) {

diff --git a/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c b/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c
index 6da648d990..9fbaeaf430 100644
--- a/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c
+++ b/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c
@@ -1,7 +1,7 @@
 /** @file

 *  Main file supporting the SEC Phase for Versatile Express

 *

-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.

+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.

 *

 *  This program and the accompanying materials

 *  are licensed and made available under the terms and conditions of the BSD License

@@ -283,9 +283,10 @@ InitializeDebugAgent (
   EFI_FFS_FILE_HEADER   *FfsHeader;

   PE_COFF_LOADER_IMAGE_CONTEXT  ImageContext;

 

-  // Now we've got UART, make the check:

-  // - The Vector table must be 32-byte aligned

-  //Need to fix basetools ASSERT(((UINTN)DebugAgentVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);

+  // Now we've got UART, check the Debug Agent Vector Table

+  // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure

+  // 'Align=4K' is defined into your FDF for this module.

+  ASSERT (((UINTN)DebugAgentVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);

   ArmWriteVBar ((UINTN)DebugAgentVectorTable);

 

   // We use InitFlag to know if DebugAgent has been intialized from